JPS58147037A - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPS58147037A
JPS58147037A JP57029294A JP2929482A JPS58147037A JP S58147037 A JPS58147037 A JP S58147037A JP 57029294 A JP57029294 A JP 57029294A JP 2929482 A JP2929482 A JP 2929482A JP S58147037 A JPS58147037 A JP S58147037A
Authority
JP
Japan
Prior art keywords
conductor
integrated circuit
dark
hybrid integrated
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57029294A
Other languages
English (en)
Other versions
JPH0454377B2 (ja
Inventor
Susumu Toba
鳥羽　進
Mamoru Ariga
有賀　守
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP57029294A priority Critical patent/JPS58147037A/ja
Publication of JPS58147037A publication Critical patent/JPS58147037A/ja
Publication of JPH0454377B2 publication Critical patent/JPH0454377B2/ja
Granted legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明はセラミック基板上に半導体チップが塔載され、
半導体チップの電極と基板上の配線導体との間がリード
線によって接続される混成集積回路に関する。
このような混成集積回路の半導体チップの搭載のための
ダイボンデングあるいは半導体チップとの接続のための
ワイヤボンディングを行う場合、以前は顕微鏡を用いて
目視によって位置を確認して作業をしていた。しかし最
近は生産の合理化のためにダイボンディング、ワイヤボ
ンディングの自動化の要請が−１でいる。この場合、ボ
ンディングすべき位置の正確な認識が必要で、そのため
に基板上に位置合わせマークを付ける。位置合わせマー
クは例えば金ペーストを配線導体のための導電材料ペー
ストと同一工程で印刷焼成することによって付けられる
。しかしこの印刷金マークは通常の光学パターン認識機
ではセラミック基板との判別ができないという問題があ
る。
本発明はこのような問題を解決し、通常のパターン認識
機で基板の正確な位置検出ができ、確実なダイメンディ
ング、ワイヤボンディングを行うことのできる混成集積
回路に関する。
この目的は混成集積回路の基板上に暗色の周縁部と明色
の中央部からなる位置合わせｉ−りが付せられることに
よって達成される。暗色周縁部は黒色厚膜抵抗体ペース
ト、明色中央部は〆金属色厚膜導体ペーストの印刷焼成
によって生成するこする。第１図の平面図、第２図の断
面図において、セラミック基板ｌの上に導体ペーストの
印刷、焼成により厚膜導体２および３が形成されている
０位−合わせマーク４は暗色部４１と中央の明色部４２
とからなり、例えば先ず抵抗体ペーストの印刷焼成によ
り暗色（黒色）部４１を形成し、ついで金ペーストの印
刷焼成により明色（金属色）部４２が形成される。暗色
部４１は混成集積回路の厚膜抵抗（図示せず）と、明色
部４２は厚膜導体２．３と同時に印刷焼成することがで
きる。
このような暗色部４１と明色部４２とからなる位置合わ
せマーク４は、両部の色調の相違により通常のパターン
ｇｉｔａｉ機によって判別して明確な２値化信号を出す
ことができ、その信号に基づいて半導体チップ５の導体
２の上へのグイボンディング、チップ５と導体３とを接
続するリード線６のワイヤボンディングを所期の通りに
実施することができる。
マーク４の位置の１１１ｍは暗色部４１と明色部４２と
の境界４３において行われるから、導体ペーストと抵抗
体ペーストのスクリーン印刷の位置ずれがあっても、境
界４３と導体２，３との間には位置ずれはなく、グイボ
ンディング、ワイヤボンディングは所定の位置で正確に
自動的に実施できる。
位置合わせマークは図示した２個所に限定されず、位置
精度の要求の低い場合には１個所でもよく、高い場合に
は３個所以上設けてもよい。またマークを厚膜により形
成することに限定されず、薄膜回路を有する混成集積回
路の場合には基板上への導体部形成の前に導体部構成材
料と色調の異なる暗色部を形成し、導体パターン形成と
同時に位置合わせマークを薄膜で形成しても同様の効果
を得ることができる。
以上述べたように本発明に基づく混成集積回路は基板上
に例えば回路の導体と同時に形成できる明色部を例えば
回路の抵抗体と同時に形成できる暗色部とからなる位置
合わせマークを有するので、通常の光学パターンｇ識機
により＃４ｉｉｌＩな位置＆Ｉ繊　　　゛信号を発信さ
せるーことができ、所定の位置へのグイボンディングあ
るいはワイヤボンディングの自動化が可能になるため、
製造原価の低減の上に得られる効果は極めて大きい。
【図面の簡単な説明】
第１図は本発明の一実施例の要部平面図、第２図は同じ
く要部断面図である。 ｌ・・・セラミック基板、４・・・位置合わせマーク、
４１・・・暗色部、４２・・・明色部。 第１図 １　　　　７　　５

Claims (1)

  1. 【特許請求の範囲】 ｌ）基板上に暗色の周縁部と明色の中央部とからなる位
    置合わせマークが備えられたことを特徴とする混成集積
    回路。 ２、特許請求の範囲第１項に記載の回路において、暗色
    周縁部が黒色抵抗体ペースト、明色中１１導体ペースト
    の印刷焼成によって生成された厘であることを特徴とす
    る混成集積側ｒｈ。
JP57029294A 1982-02-25 1982-02-25 混成集積回路 Granted JPS58147037A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57029294A JPS58147037A (ja) 1982-02-25 1982-02-25 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57029294A JPS58147037A (ja) 1982-02-25 1982-02-25 混成集積回路

Publications (2)

Publication Number Publication Date
JPS58147037A true JPS58147037A (ja) 1983-09-01
JPH0454377B2 JPH0454377B2 (ja) 1992-08-31

Family

ID=12272218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57029294A Granted JPS58147037A (ja) 1982-02-25 1982-02-25 混成集積回路

Country Status (1)

Country Link
JP (1) JPS58147037A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130240U (ja) * 1984-07-26 1986-02-24 富士通株式会社 ダイボンダ−
WO2007057954A1 (ja) * 2005-11-17 2007-05-24 Fujitsu Limited 半導体装置及びその製造方法
JP2008047926A (ja) * 2007-08-24 2008-02-28 Nitto Denko Corp ダイシング・ダイボンドフィルム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56146242A (en) * 1980-04-16 1981-11-13 Hitachi Ltd Positioning method of bonding position at fixed position on substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56146242A (en) * 1980-04-16 1981-11-13 Hitachi Ltd Positioning method of bonding position at fixed position on substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130240U (ja) * 1984-07-26 1986-02-24 富士通株式会社 ダイボンダ−
JPH0525235Y2 (ja) * 1984-07-26 1993-06-25
WO2007057954A1 (ja) * 2005-11-17 2007-05-24 Fujitsu Limited 半導体装置及びその製造方法
JP2008047926A (ja) * 2007-08-24 2008-02-28 Nitto Denko Corp ダイシング・ダイボンドフィルム
JP4618738B2 (ja) * 2007-08-24 2011-01-26 日東電工株式会社 ダイシング・ダイボンドフィルム及び半導体チップの固定方法

Also Published As

Publication number Publication date
JPH0454377B2 (ja) 1992-08-31

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