JPS58146934A - Comparator for size of data - Google Patents

Abstract

PURPOSE:To compare the size of data easily, by inputting binary data groups A, B to a comparator, inputting one of the groups A, B to a NOR or AND circuit and finding OR between the output from the NOR or AND circuit and an output from a data size comparator. CONSTITUTION:The binary data groups A, B are inputted to the size comparator 11 and the data of group B e.g. are inputted to the NOR circuit. When the whole data group B is ''0'', ''1'' is outputted from the NOR circuit and the OR circuit. When the whole data group B is not ''0'', the compared output of the size comparator 11 is outputted through the OR circuit. Consequently, the time required for the comparison of size is sharply reduced when the whole data group B is ''0''. When the maximum value is to be detected, the AND circuit is used in stead of the NOR circuit and the time required for comparison is sharply reduced when all the signals are ''1''.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is applicable to, for example, PWM (Pulse Width
The present invention relates to a magnitude comparison circuit that is used in a circuit (Motalatlam) and compares the magnitude of a digital input.

[Technical background of the invention]

Generally, the magnitude comparison of digital signals is performed as shown in FIG. That is, the signals a.~kame n-11bO~1)n-1 from the two digital data groups A and B
is supplied to the magnitude comparison circuit 11, and the magnitudes are compared and rA
) BJ, rA-BJ.

"Mu (Outputs a predetermined value according to BJ.

[Problems with background technology]

However, in the above configuration, data group A.

There is a relatively large time delay (delay time) from when B is input until output is generated, and it is desired to speed up this circuit.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The objective is to provide an improved nine-large-small comparator circuit that can produce outputs with shorter delay times for specific compared data inputs, such as 2wM circuits.

[Summary of the invention]

That is, in the present invention, a magnitude comparison circuit to which two binary data groups are supplied is provided with a logic circuit that detects whether one or both of the input data groups is a minimum value or a maximum value as a binary number, When the input data group has a minimum value or a maximum value, the output is given priority over the output of the magnitude comparison circuit.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Figure 2 shows its configuration. In the figure, the NOR circuit NOR detects that the signal b・~'+a-1 is the minimum value from the data group B, and the OR circuit OR detects the minimum value of the signal b・~'+a-1 from the data group B. The output is given priority over the output of the magnitude comparison circuit 11. In the above configuration, when the input data group B becomes all @0'', the logic circuit consisting of the NOR circuit NOR and the OR circuit OR outputs @1'', and all the data group B become @θ' Time is magnitude comparison circuit 1
A comparison output of 1 is obtained via an OR circuit OR.

According to such a configuration, the input data group A.

The time required to detect the minimum value of the data to be compared or the minimum value of B is shorter than the time required to output the result of comparing B with the h-pit magnitude comparison circuit 11, so that the speed can be increased.

That is, when one input data is the maximum value or the minimum value, the magnitude comparison result is determined regardless of the value of the other data to be compared. Now, suppose that the function of the magnitude comparison circuit 11 is set to ``1m1'' when ``MU≧B'', and the output is ``0#'' when ``MU≧B'', and the comparison data group is generated.

Set to @01 of B Fin pit or a positive integer. child
.

In this case, when the input data group B is all the minimum value @0'', the output of the magnitude comparison circuit 11 is K"l" regardless of the value of the data group A. Therefore, data group 1 is Detects the state of “all @0” and converts this signal into the magnitude comparison circuit 1
By giving priority to the output of 1 and outputting it, the delay time of the output of the magnitude comparison circuit 11 can be significantly shortened.

Figure 3 shows a circuit that detects the maximum value of input data group A.
In the figure, the AND circuit AND outputs a signal a of data group A.
It detects that o~1n-1 is the maximum value, and the OR circuit OR outputs the output from the AND circuit Munu to the magnitude comparison circuit 1
1 (priority is given to the D output). According to such a configuration, when the input data group is at its maximum value (all @ 1"), the logic circuit consisting of the AND1 block and the OR circuit 11" is output in a short time.

In each of the above embodiments, a logic circuit is provided in one of the input data groups A or B to detect the maximum value or the minimum value.
Of course, the configuration may be such that path A is provided and the maximum value and minimum value are detected.

By the way, there is a PWM circuit shown in FIG. 4 that can obtain particularly great effects by applying the present invention. PWM
The circuit has a number 4 corresponding to the size of the input digital data.
In a circuit that generates a pulse signal with a pulse width of .f, the data group A in the figure is data to be converted into P■, and the reference is the output of the UP counter 12.

In the above configuration, the contents of the UP counter 12 count and tag clock pulses CP,
When it becomes equal to the value of the data group, the output PWM of the magnitude comparison circuit 11 changes from @1'' to @0''. And U
When the P counter 12 overflows and the signals a- to an-1 all change from the state @"1" to the state @0", the output P
WM changes from @0# to 11". Therefore, the output PWM of the magnitude comparison circuit 11 corresponds to the size of the data group A, and a pulse signal with a width of 9 f is obtained. Here, the contents of the UP kakunta 12 is added in 11m increments, so there is no need to compare all bits when comparing with -1 and 1 group, so an output can be obtained in a relatively short time, but if the contents of the UP counter 12 are (1, 1 ,1...1) to (o, o, o
, -o), the ninth magnitude comparison in which all bits change takes the longest time, and the delay time required for this change determines the operating speed of the PWM circuit. Therefore, by providing a logic circuit consisting of a NOR circuit NOR and an OR circuit OR, the minimum value of the UP counter 12 (0, 0, 0, . . .
・By detecting the state of 0) and giving priority to the output of the magnitude comparison circuit 11, the delay time can be significantly reduced. By applying this principle, a high-speed magnitude comparison circuit can be realized with I”L
The circuit realized by this method is approximately 1.5 times faster than conventional circuits9.

Note that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways.The logic circuit that detects the maximum value and the minimum value and prioritizes this output over the output of the magnitude comparison circuit may be implemented using other logic circuits. Togen can also be used for circuits.

〔Effect of the invention〕

As described above, according to the present invention, an improved magnitude comparison circuit can be obtained that can generate an output with a shorter delay time for a specific data input to be compared.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional magnitude comparison circuit, FIG. 2 is a block diagram showing a magnitude comparison circuit according to an embodiment of the present invention, and FIGS. 3 and 4 are diagrams showing other embodiments of the invention, respectively. FIG. 11... Size comparison circuit * A - B... Data group. NOR...NOR circuit, OR...OR circuit, AND
−...AND circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 3

Claims (3)

[Claims] (1) A magnitude comparison circuit that is supplied with two binary data groups and compares their magnitude, and detects that one or both of the input data groups is the minimum or maximum value as a binary number, and A magnitude comparison circuit characterized in that a logic circuit obtains an output with priority over the output of the magnitude comparison circuit at the time of a group minimum value or a group maximum value. (2) The above logic circuit consists of a NOR circuit to which one data group is supplied, and an OR circuit to which the output of the NOR circuit and the output of the magnitude comparison circuit is supplied, and the minimum value of one data group is 2. The magnitude comparison circuit according to claim 1, wherein the magnitude comparison circuit is configured to perform detection. (3) The above logic circuit consists of an AND circuit to which one data group is supplied, and an OR circuit to which the output of the AND circuit and the output of the magnitude comparison circuit are supplied, and detects the maximum value of one data group. A magnitude comparison circuit according to claim 1, characterized in that the circuit is configured to perform the following.