JPS5814610A - Push-pull amplifier - Google Patents

Abstract

PURPOSE:To realize a high-speed operation of a push-pull amplifier, by using two current producing means and a current control means that limits the reduction of the output currents of said current producing means at a prescribed current level after detecting the reduction and then supplying these two output current to a bias circuit provided between the control inputs of pair of a output amplifying elements. CONSTITUTION:The output of an amplifying circuit 1 is applied to the middle point of a bias circuit 2 provided between the base control inputs of a pair of amplifying transistors (TR)Q1 and Q2 of an electric power amplifying circuit 3. The emitter outputs of the TRs Q1 and Q2 give the push-pull driving to a common load RL via the resistances R1 and R2. A resistance R3 and a TRQ3 are used to detect the base control input voltage of the TRQ1 that amplifies the positive side signal. The collector current of the TRQ3 is supplied to a resistance R5, and the voltage drop of the resistance R5 is detected at the base of a TRQ5 to be used to an input current of a current mirror circuit 4 via a reference voltage source E1. In the same way, a resistance R4 and a TRQ4 are provided to detect the base control input voltage of a TRQ2 which amplifies the negative side signal. Then the voltage drop of a resistance R6 is detected at the base of a TRQ10 to be used to an input current I2 of a current mirror circuit 5 via a power supply E2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a class B push-pull amplifier, and more particularly to a non-switching class B push-pull amplifier circuit.

In a 5EPP (single-ended push-pull) amplifier, which is an example of an audio power amplifier, the outputs of a pair of amplifying transistors in one output power stage are connected in common, and the common load is driven in push-pull depending on the positive or negative signal. However, in class B amplifiers in particular, one of the output amplifying elements is turned off depending on whether the signal is positive or negative, so the operation speed decreases due to the accumulation effect of minority carriers accompanying the on/off operation. This also causes switching distortion.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a push-pull amplifier that maintains the high efficiency of a class 8 amplifier, eliminates bulk switching operations, enables high-speed operation, and eliminates switching distortion.

The push-pull amplifier according to the present invention has a first current that generates a current that decreases (or decreases and increases) in response to increases and decreases in the control input voltage of the element that amplifies the positive input signal among a pair of output amplification elements. a second generating means, which generates a current that increases and decreases (or increases and decreases) in accordance with increases and decreases in the control input voltage of the element that amplifies the negative side input signal of the pair of output amplification elements;
current generating means, and first and second current limiting means that respectively detect a decrease in the output current of the first and second current generating means and limit each decreased output current to a predetermined value. The present invention is characterized in that both output currents of the first and second current generating means are supplied to a bias circuit between control inputs of a pair of output amplifying elements.

The present invention will be explained below using the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, where 1 is a voltage amplification circuit, %& is an input resistance, and RB and RC are resistors of a negative feedback circuit that feeds back the circuit output OUT. The output of the amplifier circuit l is supplied to a pair of amplification transistors Q1. of the power amplifier circuit 3. It is applied to the midpoint of the bias circuit 2 provided between the base control inputs of Q2. This bias circuit 2
is made up of, for example, a series connection circuit of a diode and a resistor, and the idle current of the output transistors Qll to Q2 when there is no signal is determined by the DC current to the bias circuit 2 of and. Transistor Q1. Q2 is a mutually complementary element, and both emitter outputs are connected to a resistor R1゜R.
The common negative 4Rt is push-pull driven through the two terminals 2 and 4, respectively.

A resistor R3 and an NPN transistor Q3 are provided to detect the pace control input voltage of the NPN transistor Q1 which amplifies the positive side signal, and the collector current of this transistor Q3 is supplied to the resistor R5.

This voltage drop across the resistor R5 is detected by the base of the NPN transistor Q5 and is passed through the reference voltage source E1 to the current input to the current mirror circuit 40. This current b
-The circuit 4 transfers the input current 1 and supplies it to the bias circuit 2.

In addition, a resistor R4 and a PNP transistor Q4 are provided to detect the base control input voltage of the PNP transistor Q2, which amplifies the negative side signal.
A collector current of 4 is supplied to the resistor R6, and this resistor R
The voltage drop of 5 is detected by the base of the PNP transistor Q1o and is input to the current mirror circuit 5 via the reference voltage source. The current mirror circuit 5 transfers the input current 2 to the bias circuit 2.
We are trying to supply it to

Furthermore, a series circuit 6 consisting of a reference voltage source E3 and a unidirectional diode Di is provided at both ends of the elastic resistor R5.
5 voltage drop to a constant value Ea + VDI (VD
I is clamped to the forward voltage of the diode Dl).

Also, a reference voltage source E4 and a diode D are connected across the resistor &.
A series circuit 7 with 2 is provided to similarly clamp the voltage drop across resistor & to a constant value of E4+VD2.

In such a configuration, consider a case where the control input of the transistor q becomes positive, the output OUT swings to the positive side, and a current approximately twice or more of the idle current Io flows through the load &5. At this time, among the output transistors, the negative side transistor Q2 is about to transition to the cut-off state, so the transistor Q2
VBE (base-emitter voltage) and the voltage across resistor R2 decrease. Accordingly, the detection transistor Q4 connected in parallel with the transistor Q4 also approaches cutoff, and the voltage drop across the collector resistor R6 of the transistor Q4 decreases. Therefore, the current flowing through the transistor Qlo increases, and this increased current I2 flows through the current mirror circuit 5.
is directly transferred to the bias circuit 2, increasing the bias current of the bias circuit 2 and increasing the output transistor Q.
1. Operates to increase the inter-pace bias of Q2.

On the other hand, since a load current corresponding to the output current flows through the transistor Q1, its vBE and the voltage drop across the resistor R1 increase, so that the current flowing through the parallel-connected transistor φ also increases. Therefore, the voltage drop across the resistor R5 increases and the current flowing through the transistor decreases.

The current of the transistor is directly transferred by the current mirror circuit 4 and flows to the bias circuit 2 1, which acts to reduce the current 11 flowing thereto, so that the current of the transistor Q1 . It operates to reduce the base-to-base bias of Q2. However, the voltage drop across the resistor R5 is limited by the limiting circuit 6 and is therefore clamped at a constant value of Ea + VDI. Therefore, the output current 1 of the current mirror circuit 4 does not decrease below a certain value, but settles down to a predetermined value.

However, since the voltage drop across the load resistor R6 of the transistor Q4 is not restricted in any way by the circuit 7 in the direction of decrease, it is further decreased, increasing the output current I2 of the current mirror circuit 5 and lowering the bias voltage of the bias circuit 2. increases, and output transistor Q2 turns on. Now, when the bias voltage increases further and the on-current of the output transistor Q2 attempts to increase, the voltage drop across the resistor & is limited by the limiting circuit 7, and therefore the current of the current mirror circuit 5 increases. I2 becomes constant and the bias voltage stops increasing. Thus, transistor Q1. The pace control input voltage of Q2 increases and the output OU
Even if T swings positive and the load current increases, the transistor Q
2 is controlled so that a constant idle current continues to flow at all times, and the output transistor is also prevented from shifting to the cut-off state.

Conversely, when the pace control input voltage of both output transistors Qt+Q2 falls and the output OUT swings negative, the decrease in the output current 2 of the current mirror circuit 5 is caused by the limit circuit 7.
At the same time, the output current 1 of the current mirror circuit 4 is increased to increase the bias voltage, and the transistor Q1 is controlled to be in the on state. Since the output current 1 is set to a constant value, a constant idle current flows through the transistor Q1 in this case as well.

FIG. 2 is a diagram showing a specific example of the circuit shown in FIG. 1, and parts equivalent to those in FIG. 1 are designated by the same reference numerals.

Bias circuit 2 includes diode D9 and resistor R17+Rt
s and diode Dlo are connected in series in this order, and the output of voltage cold circuit l is connected to resistor R17 and Rl.
A is applied to the connection point with Qts, and both ends of this bias circuit serve as pace inputs of transistors Qts and Q12, respectively.

The current mirror circuit 4 includes a first current mirror consisting of a diode D6 + transistors Qa, Qs, and a resistor R71R91R11, which takes the collector output 1 of the transistor Q5 as an input, and a first current mirror that takes the collector current of the transistor Q6 as an input, and has a diode D5. It has a transistor Q7 and a second current mirror consisting of resistors Rs and R1o. The collector output of the transistor Q7 becomes the collector input of the transistor Q8 via the bias circuit 2.

The current mirror circuit 5 uses the collector output 2 of the transistor Q1o as an input, and includes a diode, a negative D71 transistor Q91 Qll, and a resistor R12+R14s R.
A third current mirror consisting of Ig and a transistor Q
It has a fourth current mirror circuit which takes the collector output of No. 9 as an input, connects it to a diode, and includes a transistor Q12 and a resistor Rxat Rls. The collector output of the transistor Qu becomes the collector input of the transistor Q12 via the bias circuit 2.

Further, the first current limiting circuit 6 is a Zener diode ZD.
1 and a diode D1, and the operating current of the Zener diode ZDl is supplied by a constant current source Ill. The second current limiting circuit 7 consists of a Zener diode ZD2 and a diode 2, and is supplied with the operating current of the Zener diode ZD2 by a constant current source 112.

By doing this, the operation exactly the same as that described in the circuit of FIG. 1 is performed, and the output transistor Q1. Q2 cut-off will be completely prevented.

Note that in the above embodiment, the output transistor Q1.
In response to increases and decreases in the pace control input voltage of Q2,
The output current 1 of the first current generating circuit including the current mirror circuit 4 is made to decrease and increase, respectively, and the output current 2 of the second current generating circuit including the current mirror circuit 5 is conversely increased and increased, respectively. I'm trying to decrease it. However, output transistor Q1. Since the DC bias voltage of the pace bias circuit 2 may be activated in response to an increase or decrease in the pace control input of Q2, the output current of either the first or second current generating means is What is necessary is to increase one and decrease the other. However, if the decrease in current becomes large, it becomes impossible to increase the bias voltage of the DC bias circuit, so a current limiting circuit is added to each of these circuits in order to limit this decrease in current to a constant value. , FIG. 3 is a diagram showing an example of application of the present invention, and parts equivalent to those in FIG. 1 are indicated by the same reference numerals. In the figure, a reference voltage source; So-called auto-bias circuit 1, which is similar to current mirror circuits 4, 5, etc.
0 power supply voltage can be lowered. Therefore, the elements used only need to have a small breakdown voltage, making them suitable for integration. Note that I21s and I22 are bias current sources for generating the voltage source 1E.

As shown above, according to the present invention, it is possible to prevent the output element from turning off while substantially maintaining the high efficiency of a class 3 amplifier.

Since it can operate at high speed and has no switching distortion, it has the advantage of high speed operation and no switching distortion.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of FIG. 1, and FIG. 3 is a diagram showing an application example of the circuit of FIG. 1. Explanation of symbols of main parts 2...Bias circuit 3...Output power amplifier circuit 4
．． 5...Current mirror circuit 6.7...Current limiting circuit Ql, Q2...Output transistor Applicant Pioneer Co., Ltd. Agent Patent attorney Hiko Fujimuramoto - Diagram

Claims (1)

[Claims] A push-pull amplifier configured to push-pull drive a common load by commonly connecting the outputs of a pair of output amplifying elements, the bias circuit provided between the control inputs of the output amplifying elements; A first current generator that generates a current that increases or decreases (or decreases or increases) in response to an increase or decrease in the control input terminal voltage of the element that increases the positive input signal among the pair of output amplification elements, and supplies the generated current to the bias circuit. means and
A second current that generates a current that increases or decreases (or increases or decreases) in response to an increase or decrease in the control input terminal voltage of the element that amplifies the negative side input signal among the pair of output amplification elements, and supplies the generated current to the bias circuit. The current generating means includes a generating means, and first and second current limiting means that respectively detect a decrease in the output current of the first and second current generating means and limit each decreased output current to a predetermined value. push-pull amplifier.