JPS5814572A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a densely integrated, high performance semiconductor device by a method wherein a lamination of a polycrystalline Si layer and a Pt layer is applied to coat electrodes to realize electrodes capped with Pt silicide after heat treatment, in a process of forming electrode layers on a source and drain regions, and a gate electrode built on a semiconductor substrate. CONSTITUTION:An element isolating dielectric thick layer 3 is formed on a P<+> type channel cut layer 2 in the periphery of a P type semiconductor substrate 1, and the part of the substrate 1 surrounded with the layer 3 is coated with a thin gate oxide film 4. Next, at the middle of the film 4, a gate electrode is built consisting of an N<+> type polycrystalline Si layer 5, an Si3N4 film 601, and an SiO2 film 7. The film 4 located on the both sides of the gate electrode is removed and an N type source region 12 and drain region 13 are formed by diffusion. After this, a coating of an N type polycrystalline Si layer 9 is formed and covers the ends of the gate electrode and the layer 3, which in turn is covered with an Si3N4 film 602. The entire surface is then covered with a Pt layer 10 and is subjected to heat treatment for the formation of a Pt silicide layer 11 on the Si layers 5 and 9 to work as respective electrode layers.

Description

[Detailed Description of the Invention] The present invention! P! The present invention provides a method for manufacturing a semiconductor device related to miniaturization or performance improvement of a four-piece lid.

In recent years, the progress of semiconductor devices, especially semiconductor integrated circuits, has been remarkable.
Microfabrication technology (photoetching technology)% Improvements in technologies such as ion implantation technology and etching technology have greatly contributed to this. Here, even if the element dimensions are reduced proportionally, the density can be greatly improved using the conventional technology due to contact hole opening technology, alignment margin, etc. There are limits to things. Therefore, a method of forming this contact hole in a self-aligned manner is used to form Belt-aligned contact holes.
tact (8, A, C), and 8UNAMI et al. have already developed 513LOCO8 (selective Oxid・c
It is called ``Oateng of Si/1con Intea''. According to this, a high d
A No. 9 crystalline silicon pattern is doped with llfP, and this is used as a gate electrode. By doping with high concentration phosphorus and using the property that the oxidation rate of the No. 9 crystalline silicon is faster than that of single silicon, Form a thick oxide film. later,
Etch the entire oxide film.

, even if the drain portion is exposed, the oxide film on the gate remains. Therefore, by using this exposed portion as a contact hole for the source region, it is possible to form the contact hole between the source and the gate or between the drain and the gate in the shortest possible length in a self-aligned manner without having any margin for alignment. . However, the following drawbacks exist.

First, the oxide film around the gate electrode has insufficient breakdown voltage.

In general, when etching a nonaqueous oxide film, weak parts become even weaker and rounded, resulting in greater variation in characteristics. In particular, polycrystalline silicon has holes caused by grain boundaries and permanent pinholes caused by the photoresist process.

During this rounding, the etching solution penetrates into the lower gate oxidation layer. Especially in polycrystalline silicon with high temperature and high concentration of impurities.
9. Crystal grain size is large. Etching the oxide film on polycrystalline silicon with a hydrofluoric acid etchant results in
There is a risk of deterioration of breakdown voltage and gate/source/drain resistance (FE).

Second, the parasitic capacitance between the gate, source, and drain increases. This is because the oxide film is thin, the gate, source, and drain electrodes are very close to each other, and their opposing areas are large. Although this can be solved to some extent circuit-wise, it increases the restrictions on circuit design.

Thirdly, 4+1 paratsurei (variation of threshold value vth)
0gl1 type oxidation (wet oxidatlon)
) The oxidation rate due to fC has a small difference at high temperatures and a large difference at low temperatures.

However, at low temperatures, the film quality deteriorates. 9. The higher the impurity concentration, the greater the difference in oxidation rate.However, if the impurity concentration of polycrystalline silicon is high, the silicon substrate and the unoxidized film formed thereon (warming film for two-layer electrode) will be damaged during oxidation. If impurities in polycrystalline silicon are introduced into the material, the threshold value (vth) will vary.

Fourth, if the oxide film is made thicker (oxidized for a longer period of time) in order to improve the withstand voltage, the difference in oxidation rate disappears, making it impossible to open the north and drain in a self-aligned manner.

Fifth, and most importantly, when polycrystalline silicon is oxidized to a thick thickness and an insulating film is formed, the gate electrode becomes thinner and thinner, which may lead to disconnection, especially in areas where there are steps. In particular, it is very difficult to control the optimization of impurity S+t and the optimization of oxidation. Furthermore, if the gate electrode (polycrystalline silicon) is made finer, the wiring resistance will increase in proportion to it. This in turn prevents high speed performance and reduces the deterioration of device performance.

The present invention has been made in view of this problem, and particularly relates to a method for manufacturing a semiconductor device, which enables miniaturization of the semiconductor device and significantly improves the performance of the device.

Detailed explanation of the present invention will be given below.
This will be explained using FIG. 1 (8) to ff). (First Example): First, in the first IIHa), a channel cup (p+@2) for preventing reversed ions is formed in the p-type semiconductor substrate 1, and a zero-order channel cup (p+@2) is formed to form a galvanic body cavity 3 for element isolation. After forming the gate oxide film 4 with a thickness of, for example, 400 to 1000λ, all impurity ions are implanted into the entire surface (not shown), and the polycrystalline silicon 5 doped with the nil impurity is implanted into the entire surface.
After depositing, for example, 3000 to 4000, CVD-8i3N4601 is further deposited on top of it, for example, 100
and CVD-81027t*t,t 1f3000
~5000 and selectively patterned. [
@1 Figure 16) As shown] Next, as shown in Figure 1(C), the unnecessary gate oxide film 4 is removed.
selectively etched. This method includes the polycrystalline IJ core 5,! : CVD Si3N4601
, Reactimer eIon F! when forming a pattern consisting of CVD-8IO37. tching (RI
It may be etched at the same time using anisotropic etching such as B), or furthermore, the unnecessary gate oxide film 4 may be etched by forming the 5#601.7 pattern and heat-treating it in an N2 atmosphere using the pattern as a mask. You can also use etching. Then, an oxide film 801 is formed on the patterned side of the polycrystalline silicon 5 by wet Oxalization at 700'O to 900[deg.] C., for example, 20oO to aoooXmFlt. At this time, 300~70G is applied on the PAL semiconductor substrate! An oxide film (not shown) of 8111 is formed. Thereafter, the oxide film is etched using self-metal etching (RIP) to expose the p-type semiconductor layer in the region where the source and drain Il interconnections are to be formed.

At this time, after etching the unnecessary gate oxide film 4'' and forming the north and drain holes by, for example, arsenic implantation, the patterned sides of the polycrystalline silicon are oxidized to form the north and drain contact holes. It may be formed.

Next, the whole is coated with, for example, arsenic-doped polycrystalline silicon yst.
For example, 3000-4000g and cvD-43N4
602 is selectively patterned using, for example, xoooX deposited material. At this time, the paper source 12. The electrode (polycrystalline silicon 9) of the drain 13 is formed, but in some cases the position may shift and the S pH semiconductor substrate may be exposed, but by pouring arsenic into the entire surface, No problems will occur. Next, CVD-8i027 t IIIE CVD- on the gate electrode (polycrystalline silicon 5)
813N4605 After etching the opening of the polycrystalline V silicon 9 as a mask, a thermal oxide film 802 is selectively formed on the patterned side of the polycrystalline silicon 9. 'At this time, the north 12° drain 13 region is also formed. This situation is shown in FIG. 1(d). Next, CV'D is performed using hot phosphoric acid or Freon dry etching at 160°C, for example.
- After removing 813N4601 and 602 at the same time, use a high-yield metal such as platinum 10, for example, SO
Q~100OK is applied. [Figure 1 (e)] After that,
By performing heat treatment in an N2 atmosphere at 500° C. to 600° C., the platinum on the polycrystalline silicon 5 and 9 undergoes a chemical reaction and becomes platinum silicide 11, while the platinum on the insulating film, for example, the oxide film 802, remains as it is. Afterwards, the platinum on the oxide film 802 remains as it is. Later, by boiling with aqua regia, the platinum on the oxide film 8G2 is etched, and the polycrystalline silicon 5
．． Platinum silicide 11 is formed on 8 in a self-aligning manner. [@Figure 1 (f)] With the above, the gate, source, and drain electrode wirings are all made of polycrystalline silicon! It is made of metal silicide with low IiJ resistance.

Note that the amount of polycrystalline silicon to be silinized is usually determined by the thickness of the platinum film. For example, film thickness 500λ
Platinum at 550℃ N! When heat treated in an atmosphere, approximately 10
1000A1! The platinum silicide 75E is formed, and eventually the polycrystalline silicon may not be completely converted into silicide and remain, but it doesn't matter.By the way, the wiring resistance (sheet resistance) under the above conditions is 2G/gate. Yes, nine.

Further, if necessary, phosphorus and gettering may be performed after forming the oxide film 802 shown in FIG. 1(d). Furthermore, in this embodiment, the oxide films 801 and 802 were formed by thermal oxidation treatment, but the methods shown in FIGS. 2(1m) to 2(e) may also be used. (Second Embodiment) First, in the p-type semiconductor substrate 1, a channel-cut p"
12 and dielectric-3, the above pa! .

Semiconductor substrate 10 surface rfUK gate oxide film 4. n
Impurity-doped polycrystalline silicon/S and 10th CVD process 14
After forming a pattern consisting of 1, in order to form an insulating film on the side surface of the pattern of polycrystalline silicon 5, a second (or higher) film is deposited at 9x, for example 2000 to 3000x, and rounding and heating are performed to improve the film quality. After that, for example 2000~3000'
1. undoped polycrystalline silicon 15 is deposited, and is formed like a wall (hereinafter referred to as a polysilicon wall) on the side surface of the n 2 impurity-doped polycrystalline silicon 5 with a second CVD film 142 interposed therebetween using ttRIg. [Illustrated in FIG. 2(a)] The 20th VD film 142 is then selectively etched using the polysilicon wall as a mask to form the north 12. The surface of the drain 13 region is exposed. Next, after etching the polysilicon layer (in some cases, it may be used as is without etching), deposit polycrystalline silicon 16 doped with the n1 impurity and selectively pattern it. The CVD film 141 on the polycrystalline silicon 5 is also etched at the same time. This situation is shown in FIG. 2(b). After depositing the G0 film 143 over the entire surface, for example, undoped polycrystalline is deposited on top of it, and the polysilicon wall is formed using RIB via the CVD film 143 to form the polycrystalline silicon 16 (turn side [IK] , [not shown] After that, cvog 143 is selectively formed on the side surface of the polycrystalline silicon 16 using the polysilicon layer as a mask, and the polysilicon wall is removed by etching, as shown in FIG. 2 (C3). North and drain electrodes (polycrystalline silicon) 1
6 and gate electrode (n polycrystalline silicon) 5 are CVD films 14
3 in a self-aligned manner, n+ polycrystalline silicon 5 and 1
An insulating film (CVD film 142
and 143) can be formed. Although not shown below, the source, drain, and gate electrodes can be made into platinum silicide wiring by depositing platinum on the entire structure and heat-treating it. Thereafter, by removing unsilicided platinum on the CVD film 143 with aqua regia or the like, each region is formed into an insulating film.

Next, as another example (practical example 3), a p-ch MO8m) transistor will be described. Figure 3 (
Simple examples are shown in a) to (C).

First n! [1 Dielectric isolation 43 on semiconductor substrate 101.

An n++ conductor layer 201 for channel cutting is formed.

nII semiconductor substrate 101 surrounded by the electric conductor dividing layer 3
A pattern consisting of gate oxide JII4, p10 impurity dope polycrystalline silicon 501, and CvD film 141 is formed on the 0 surface.Next, using this pattern as a mask, 9, for example lX
Implant p-stage impurity ions very shallowly at a dose of 10" to 1x10131-2 at 120°130°, as shown in Figure 3(a). After that, C Films 141, 142, 143, p++ impurity-doped polycrystalline silicon 160, and extremely shallow activation regions 120 and 130 impregnated with the p-type impurity ions 2
and 131 and 5ptJ1 diffusion from impurity doping - of 12
After forming 3 and 132, platinum 10 was applied to the whole, for example 500X, and the appearance of 9 is shown in the 3rd open mountain), and then 55
Silicide in an N2 atmosphere at 0'O, etching excess platinum with aqua regia, etc., and then make a sauce.

FIG. 3C shows how the drain and gate regions are formed of platinum silicide 11.

As described above, in the semiconductor device according to the present invention, the distance between the source and the gate or between the drain and the gate is made as short as possible, and each electrode is separated by forming an insulating film in a self-aligned manner. It is possible to improve the performance and integration of semiconductor devices without the need for extra margin. The quality of the insulating film is very good, especially in Example 2.3, and even if the film thickness is increased, the polycrystalline silicon of the gate electrode does not become thinner, so there is no thinning between the north gate or the drain and gate. There is no electrical discharge caused by metal electrodes, and the capacitance can be further reduced.

Father, the gate withstand voltage can also be greatly increased.

Next, as semiconductor devices become smaller and smaller, in areas where polycrystalline silicon is used for electrode lead wiring (for example, gate electrodes), wiring resistance increases in proportion to the miniaturization. The use of metal silicide, which has a sheet resistance less than 1/10 that of polycrystalline silicon, is used for wiring, making it possible to form low-resistance wiring even when semiconductor devices are miniaturized. Moreover, each electrode wiring is covered with an insulating film (thermal oxide film 80).
2 or CVDIE 143 tv film thickness 2G00~3
000 K > Te can be separated in a self-consistent manner. (Example 1.2.3) Father, expand the north drain by 1M by diffusion from polycrystalline silicon! 11 can be formed shallowly in a self-aligned manner (Example 1.2), or in particular, it is possible to form 9p in a self-aligned manner, which was previously impossible.
-chMD8) The 8hal1w of the north and drain diffusion layers of the u/distor has a low attenuation rate as in Example 3, for example.
tt impurity ions are formed by implantation (source 121
．． Drain 131) After that, by controlling the diffusion from polycrystalline silicon 160 to the necessary conditions, diffusion-1
21 and 131 can be formed to have a thickness of 0.1 to 0.2 μm or more. Moreover, since the impurity concentration of the polycrystalline silicon 160 can be increased and metal silicide can be formed on the surface, a high-speed, high-performance semiconductor device can be manufactured with OT capability.

Furthermore, the present invention is applicable not only to MO8m) transistors but also to bipolar transistors.

This situation is shown in FIG. 4 as a fourth embodiment.

102 is an n-type epitaxial layer, 103 is an n-type epitaxial layer, and 3 is a # solder body portion 1w1I-. Ozun @ Epitaxial III 103 pm! Semiconductor II 10B
form an internal booth.

Next, n Il Akira Shiri! 162 and CVD 111
After selectively forming a pattern consisting of .41, a CvD film 142 is formed on the side end portions of the n-multilevel crystal 7-recon 162.

At this time, an n0-type semiconductor 106 (exiter) is formed.

Then, using the above pattern as a mask, 9+ impurity ions are implanted into the epitaxial layer.
form 4. Then on top of each pal silicone 16
A CVD film 143 is selectively formed at the side edge of the p-deca polycrystalline silicon pattern 1610. At this time, CVD film 1 is deposited and selectively patterned.
41 is removed by etching, and the surfaces of the p-type silicon 161 and the n+ polycrystalline silicon 162 are exposed.

Thereafter, platinum silicide is formed in the same manner to complete the process.

Furthermore, in relation to the above, since the north and drain/semiconductor layers can be formed extremely shallowly, the p-type semiconductor layer 2 for channel cutting and the n+-type half layer 201 can be
Without contact, the value capacity can be reduced by 1%, which is also a factor that allows high-4 operation. Furthermore, along with this, the dielectric film S* can also be made shallower, and therefore the thermal oxidation time for forming the IIl electric isolation layer (essentially the thermal oxide film) can be shortened. It is possible to reduce the increase in crystal defects that occur in one central area. All of this is due to improvements in high performance and high-speed operation.

Note that the impurity-doped polycrystal 7 used in this example
Recon may be doped with impurities during deposition,
A certain i may be implanted or diffused as an impurity into undoped polycrystalline silicon.

Father, gate multi-connection 1 silicon can be undoped, and instead of multi-gate silicon, 1 mole 7-a silicon can also be used.
Further, the oxidation-resistant insulating film used in Example 1 may be made of aluminum nitride or an alumina compound.Although platinum was used as the high melting point metal film, for example, N1, Mo, 'I'i,
Ta etc. also g1t4. Father, P and N in this embodiment may all be reversed.

[Brief explanation of the drawing]

1a) to 1) are rounded cross-sectional views for explaining one embodiment of the present invention, JIEZ diagrams (a) to <C) are sectional views for explaining another embodiment, and FIG. al~(c) and the fourth
The diagram is. FIG. 7 is a rounded cross-sectional view illustrating yet another example of real power. In the figure, 1... PIl semiconductor substrate, 2... p-type semiconductor for channel cut - 13... dielectric isolation 1.4... gate oxide film, 511. n10 impurity-doped polycrystalline silicon (gate electrode), 601-ii + acid (tJillHII [(C
VD-8i3N4)602... Oxidation-resistant insulating film (CV
[)-pull3N4). 7...C■ membrane (CVD-8102), 801.802
...Heat soaked film, 9...N+ type impurity rod dobe polycrystalline silicon, 10...High melting point metal (white @), 11...
Platinum silicide, 12... n+ type semiconductor - (source) 13... l (drain) 141.14
2,143... ■Membrane, 15... Undoped polycrystalline silicon (polysilicon), 101... N1ll semiconductor, 201... All semiconductor for channel cut 1.120... North I
[JF) pal ion implantation, 130...drain
1 121... Shallow n-type semiconductor layer (source) 123...
N-type semiconductor (north) 131... Shallow n-type semiconductor - (dray/) 132 ・n+fi'! Conductor +il・
('l do V in) 160... p"l L impurity doped polycrystalline silicon/(source, drain electrode) 501,... I I I (gate electrode) 102... n+11 buried layer 103... NFI epitaxial layer 104...p type semiconductor 11i (external base) 10
5...pH 11' (internal base) 106...
n-type l (emitter) 161...n+-type Takata Mukurikon 162...pm' Agent Patent attorney Nori Chika Kai Yu (and 1 other person) Figure 1 Figure 1 Figure 12 '4z Figure f33 Kuwara 3 Figure 4 Figure 12

Claims (1)

[Claims] (1) Step of forming a TSL conductor or semiconductor pattern whose upper surface is covered with a first insulating film on a semiconductor or a part of a substrate having an insulating film formed on the surface of the semiconductor. #, a step of forming a second insulating film on the side edge of the conductor or semiconductor pattern, a step of opening the substrate using the pattern as a mask, and forming a third insulating film at least on the opening. a step of forming a second conductor semiconductor pattern coated with a second conductor semiconductor pattern; a step of forming a third insulating film or @4 insulating film on the side edge of the conductor or semiconductor pattern;
A first insulating film on one conductor or semiconductor pattern, and a third or fourth insulating film on the second conductor or semiconductor pattern.
A method for manufacturing a semiconductor device, comprising the step of etching and removing a portion of the insulating film so that at least the surface of the first conductor or semiconductor pattern and the second conductor field are exposed. . (2) The first semiconductor whose surface is exposed (the second semiconductor
At least the third insulating film or t4
2. The method of manufacturing a semiconductor device 1 according to claim 1, wherein the metal silicided first semiconductor pattern and the second semiconductor pattern are separated from each other by a four-insulating film. (3) A step of forming second semiconductor patterns in at least two places and forming a semiconductor 1 of one conductivity type in at least a part of the semiconductor substrate directly under the second semiconductor pattern; 83. A method of manufacturing a semiconductor device according to claim 1 and 82, characterized in that one semiconductor pattern is used for regions such as gates and electrode wiring. (4) Manufacture of a semiconductor device according to claim (1) and (2), characterized in that the second semiconductor pattern is used as a paste and the first semiconductor pattern is used as an emitter region and electrode wiring. Method. 15) Forming a first semiconductor pattern MQ whose upper surface is covered with a first insulating film on a substrate having an insulating film formed on the semiconductor surface, and adding impurities into the substrate using the pattern as a mask. a step of performing ion implantation, a step of forming a second insulating film on a side edge of the first semiconductor pattern, a step of opening at least two or more places in the substrate using the first semiconductor pattern as a mask, and at least the openings. opening a second semiconductor pattern whose upper surface is covered with a third insulating film in at least two places; diffusing impurities from the second semiconductor pattern into the substrate; a step of forming a third insulating film or a fourth insulating film on the side edge portion of the pattern, and etching a part of the first insulating film on the first semiconductor pattern, the third insulating film on the second semiconductor pattern, etc. A step of exposing at least the surfaces of the first semiconductor pattern and the second semiconductor pattern by removing them, a step of depositing metal at a single point on the entire surface, and a step of forming metal silicide on at least the surface of the chain pattern. By etching the melting point metal, at least the third insulating film,
Alternatively, the method for manufacturing a semiconductor device, wherein the first semiconductor pattern and the second semiconductor pattern subjected to metal silicide are insulated and separated by a fourth insulating film. (6) The semiconductor device according to claim 1, wherein the conductor or semiconductor pattern is made of polycrystalline silicon, amorphous silicon, a high melting point metal, metal silicide, or a metal such as an AI compound. manufacturing method. (7) The method of manufacturing a semiconductor device according to claim 2, wherein the conductor or semiconductor pattern is made of polycrystalline silicon or amorphous silicon. (8) Above 1. The third insulating film is an oxidation-resistant insulating film. @2. □ A method for manufacturing a semiconductor device as set forth in claims (1), (2), and (7), wherein the fourth insulating layer is a thermal oxide film. (9) Said 2. Claim (1) characterized in that the fourth insulating film is a silicon oxide film grown in a vapor phase.
A method for manufacturing a semiconductor device according to items (7). Hobbies first. Second. Third. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the fourth insulating film is a silicon oxide film grown in a vapor phase.