JPS58141638U - level shift circuit - Google Patents
level shift circuitInfo
- Publication number
- JPS58141638U JPS58141638U JP1675483U JP1675483U JPS58141638U JP S58141638 U JPS58141638 U JP S58141638U JP 1675483 U JP1675483 U JP 1675483U JP 1675483 U JP1675483 U JP 1675483U JP S58141638 U JPS58141638 U JP S58141638U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- circuit point
- conductive
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例の回路図、第２図は第１図の
各部の電圧波形図１、第３図は第１図の一実施例に記憶
回路と安定回路を付加した回路図、第４図は第３図の各
部の電圧波形図、第５図は第３図の変形例の回路図、第
６図は第５図の各部の電圧波形図である。
１・・・・・・第１回路点、２・・・・・・出力回路点
、３・・・・・・第２回路点、Ｑｌ・・・・・・第１の
Ｉ（、−ＦＥＴ、 Ｑ２・・・・・・第２のＩＧ−ＦＥ
ＴＸＱ３・・・・・・第３のＩＣ−ＦＥＴ、ｉ Ｑ・・
・・・・レベルシフ”ト回路、１１・・・・・・記憶回
路、１２・・・・・・安定回路、１３・・・・・・記憶
回路、１４・・・・・・インバーター。Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a diagram of voltage waveforms at various parts in Figure 1, and Figure 3 is a circuit in which a memory circuit and a stabilizing circuit are added to the embodiment of Figure 1. 4 is a voltage waveform diagram of each part in FIG. 3, FIG. 5 is a circuit diagram of a modification of FIG. 3, and FIG. 6 is a voltage waveform diagram of each part in FIG. 5. 1...First circuit point, 2...Output circuit point, 3...Second circuit point, Ql...First I(, -FET , Q2...Second IG-FE
TXQ3...Third IC-FET, iQ...
... Level shift circuit, 11 ... Memory circuit, 12 ... Stabilization circuit, 13 ... Memory circuit, 14 ... Inverter.
Claims (1)
路点と該出力回路点間に、基準電圧Ｅ。 及び第１の電圧レベルＥ工の論理レベルを有する論理信
号をゲート入力とする一方のチャンネル形の第１のＩＧ
−ＦＥＴ及び第１のパルス信号をゲート入力とする前記
ＦＥＴと同一チャンネル形の第２のＩＧ−ＦＥＴの直列
回路配置と、前記第２回路点との間に接続され、第２の
パルス信号をゲート入力信号とする他のチャンネル形の
第３のＩＧＦＥＴとを具備し、前記第１のパルス信号の
パルス巾を第２のパルス信号の巾より小さくし、かつ第
１及び第２のパルス信号を互いに同期させ、該第３のＩ
Ｇ−ＦＥＴが不導通の時に、前記第１及び第２のＩＧ−
ＦＥＴが共に導通し、次に前記第３のＩＣ−ＦＥＴが導
通するまで前記出力回路点に前記基準電圧Ｅ３の出力信
号を与え、前記第３のＩＧ−ＦＥＴが導通の場合は、前
記第２回路点から前記出力回路点にｌ Ｅｌ−ＥＯｌ
＜ ｌ Ｅ２−ＥＯｌなる第２の電圧レベルＥ２を出力
信号として与え、更に前記第３のＩＧ−ＦＥＴが不導通
になっても、前記第１及び第２のＩＧ−ＦＥＴが共に導
通するまで前記出力端子に前記第２の電圧レベルＥ２を
出力信号として与えることを特徴とするレベルシフト回
路。[Claims for Utility Model Registration] A first circuit point, a second circuit point, an output circuit point, and a reference voltage E between the first circuit point and the output circuit point. and one channel type first IG having a logic signal having a logic level of a first voltage level E as a gate input.
- a series circuit arrangement of a FET and a second IG-FET of the same channel type as the FET, which receives the first pulse signal as a gate input, and is connected between the second circuit point and receives the second pulse signal; a third IGFET of another channel type as a gate input signal, the pulse width of the first pulse signal is smaller than the width of the second pulse signal, and the first and second pulse signals are synchronized with each other, the third I
When the G-FET is non-conducting, the first and second IG-
FETs are both conductive, and then the output signal of the reference voltage E3 is applied to the output circuit point until the third IC-FET is conductive, and when the third IC-FET is conductive, the second IC-FET is conductive. l El−EOl from the circuit point to the output circuit point
A second voltage level E2 of < l E2-EOl is applied as an output signal, and even if the third IG-FET becomes non-conductive, the above-mentioned voltage level E2 is applied until both the first and second IG-FETs become conductive. A level shift circuit characterized in that the second voltage level E2 is applied to an output terminal as an output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1675483U JPS58141638U (en) | 1983-02-09 | 1983-02-09 | level shift circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1675483U JPS58141638U (en) | 1983-02-09 | 1983-02-09 | level shift circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58141638U true JPS58141638U (en) | 1983-09-24 |
Family
ID=30029110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1675483U Pending JPS58141638U (en) | 1983-02-09 | 1983-02-09 | level shift circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58141638U (en) |
-
1983
- 1983-02-09 JP JP1675483U patent/JPS58141638U/en active Pending
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