JPS5814093B2 - Pulse multiplier circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a pulse multiplier circuit.

By the way, since a pulse generator that obtains a pulse frequency proportional to the speed of an object has many mechanical factors, it is extremely difficult to obtain a high frequency with satisfactory accuracy.

Generally, the practical limit of the response frequency of a pulse generator is about 200 KHz, so if a frequency higher than this is required, the output pulses must be multiplied by a multiplier circuit.

Regarding this multiplication, conventionally a logic circuit is configured to detect the timing of two series of pulses with a phase difference of 90°, which are the output signals of a pulse generator, but this method only has a multiplication capability of up to 4 times.

Further, in high-precision speed control, proportional-integral control is generally adopted.

In this case, both the proportional and integral functions may be performed using an analog system, but in order to eliminate drift in analog control, a system in which the integral is performed digitally is also commonly used.

A speed generator is generally used for speed detection required for analog proportional control, but since the output voltage of the speed generator includes rotational ripple, temperature drift, etc., feedback control using this This places significant constraints on the gain that can be secured.

In addition, if proportional control is implemented digitally, the above disadvantages will be eliminated, but in order to obtain the continuity achieved with analog proportional control and the resolution that is intended to be achieved with a digital system, sampling time seconds, detection resolution 30
000 sampling rate detection is required.

This speed detection is impossible with a combination of a conventional pulse multiplier circuit whose upper limit is 4 times and a pulse generator whose practical upper limit is about 200 KHz.

As mentioned above, in a digital speed control device, high-resolution digital speed detection is required to configure a proportional-integral speed control circuit that performs precise speed control, and along with this, high-frequency feedback is required. Pulses are required, but the practical limit of the current pulse generator's response frequency is about 200 KHz, and it is difficult to mechanically obtain a higher frequency, so pulse multiplication is used to electrically double the frequency. A circuit is becoming necessary.

Therefore, an object of the present invention is to provide a pulse multiplier circuit that does not dramatically improve the multiplication ability of pulse output.

This invention will be explained below.

This invention consists of a differential signal generation circuit that generates a differential signal for each cycle of an input pulse train, an oscillator that generates a reference high-frequency pulse, and a first circuit that measures the length of the pulse cycle.
a counter, a memory circuit that holds the contents of 1/n of its length, a second counter that counts the reference pulse and is reset every time it becomes equal to the memory value of the memory circuit, and a comparison between the memory value and the memory circuit. and a third counter that counts the number of pulses output during one pulse period of the input pulse train. This is designed to generate a pulse train at n intervals.

That is, in the attached drawings showing one embodiment of the present invention,
101 is a crystal oscillator that oscillates and outputs pulses of a constant frequency (8 MHz) as a reference; 107 is a differential signal generation circuit that obtains a differential signal DS of the input pulse train fi; and 102 is a circuit 2 for measuring the period of the input pulse train fi. decimal counter (16
103 is a memory circuit (12 bits) that holds the counting output of the binary counter 102, 105 is a binary counter (12 bits) for determining the period of the output pulse, 1
04 is a comparison circuit (12 bits) that compares the output of the memory circuit 103 and the output of the binary counter 105, 106 is a binary counter (4 bits) for counting and monitoring the number of output pulses, and 108 to 112 are gates, respectively. It is a circuit.

In such a configuration, the binary counter 102 constantly counts the output pulses of the crystal oscillator 101 via the gate circuit 108, and calculates the differential signal DS output from the differential signal generation circuit 107 for every pulse period of the input pulse train fi. It is reset by .

Therefore, the memory circuit 103 is on the verge of being reset.
The contents of the decimal counter 102 are held shifted by 4 bits (3A).

Here, the contents of the memory circuit 103 represent the length κ of the last pulse period of the input pulse train fi.

Furthermore, the binary counter 105 counts the output pulses of the crystal oscillator 101 at the same timing as the binary counter 102, but when the content of the memory circuit 103 is compared with the comparator circuit 104 and the content becomes equal, the gate circuit 109 is reset via .

That is, for each pulse period of the input pulse train fi,
If the periodic fluctuation before and after that is within κ, the comparator circuit 1
The coincidence output signal CS of 04 is output 15 times during one pulse period of the input pulse train Fi.

However, when the frequency is lower than the lowest input frequency determined by the capacity of the binary counter 102, the gate circuit 108 is closed and the binary counter 102 is held at the maximum value.
If this continues, the coincidence output signal CS of the comparison circuit 104 may be output 16 times or more during one pulse period of the input pulse train fi.

Here, the binary counter 106 counts the coincidence output signal CS of the comparison circuit 104 and closes the gate circuits 110 and 111 when it counts "15".
The coincidence output signal CS from the sixth time onwards is blocked.

Furthermore, the binary counter 106 is reset every pulse period of the input pulse train fi.

The gate circuit 112 receives the coincidence output signal CS of the comparison circuit 104.
and a gate circuit for passing the differential signal DS from the differential signal generating circuit 107, and its output is always 16 pulse trains, ie, 16 fi, during one pulse period of the input pulse train fi.

Thus, according to the pulse multiplier circuit of the present invention, it is possible to obtain a signal that is multiplied by 16 times with respect to the input pulse train.

Note that the oscillation frequency of the crystal oscillator 101 and each counter,
By changing the capacities of the memory circuit and comparison circuit,
It is also possible to widen the frequency range that can be multiplied, and if it is desired to obtain a pulse wave with a duty of 50% for the multiplied output pulse, the coincidence output signal CS of the comparator circuit 104 may be outputted through a flip-flop.

[Brief explanation of drawings]

The figure is a circuit configuration diagram showing an embodiment of the present invention. 101...Crystal oscillator, 102, 105, 106...2
digit counter, 103...memory circuit, 104...comparison circuit.

Claims (1)

[Claims] 1 A differential signal generation circuit that generates a differential signal for each cycle of a pulse train, an oscillator that generates a reference high-frequency pulse, a first counter that measures the length of one pulse cycle, and a first counter that measures the length of one pulse cycle. a memory circuit that holds the contents of 1/n; a second counter that counts the reference pulse and is reset each time the value becomes equal to the memory value of the memory circuit; A comparator circuit that generates one pulse at a time, and a third counter that counts output pulses of the comparator circuit and suppresses excessive output, and generates a pulse train with an interval of 17n, which is the last pulse interval of the input pulse train. A pulse multiplier circuit characterized by: