JPS58140825A - Generating circuit of reference voltage - Google Patents
Generating circuit of reference voltageInfo
- Publication number
- JPS58140825A JPS58140825A JP2306082A JP2306082A JPS58140825A JP S58140825 A JPS58140825 A JP S58140825A JP 2306082 A JP2306082 A JP 2306082A JP 2306082 A JP2306082 A JP 2306082A JP S58140825 A JPS58140825 A JP S58140825A
- Authority
- JP
- Japan
- Prior art keywords
- source
- gate
- channel
- output terminal
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 101100478187 Arabidopsis thaliana MOS4 gene Proteins 0.000 abstract 3
- 101100461812 Arabidopsis thaliana NUP96 gene Proteins 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 2
- 101000730540 Homo sapiens MOB-like protein phocein Proteins 0.000 description 1
- 102100032587 MOB-like protein phocein Human genes 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Description
【発明の詳細な説明】
不発明はＩＣの轟準司圧発生ｌ！２１路に関するもので
ある。[Detailed Description of the Invention] The uninvention is the generation of low pressure in IC! This is related to Road 21.
従来の基準１圧発生回路は、絹１図に示すよう４Ｃ１Ｎ
チャネルデプレッションＭ０８１とＮチャネルエノハン
スメン）ＭＯ８２からなっていたが基準電圧は（ｌ Ｖ
ＴＩＩＬ ｉ ＋ Ｖテｍｍ ｌで表ｇｎ、ｙチャネル
スレッショルド甫圧であるＶＰｋｌＬとｖ？ＩＩＩ＋の
変動に対して、基準電圧値が変動するという欠点があっ
た。The conventional reference 1 pressure generation circuit is 4C1N as shown in Figure 1.
The reference voltage was (l V
TIIL i + Vtemm l and gn, y channel threshold pressure VPklL and v? There was a drawback that the reference voltage value fluctuated in response to fluctuations in III+.
なおＶＯυテは基準重圧の出力端子である。Note that VOυte is an output terminal for reference pressure.
不発明は上記の欠点を克服するためになさ−ｒしたもの
τあり、スレッショルド重圧であるＶテ鼠の変動に対し
ばらつきの少い基準１圧値を与えることを０門とした１
ｇｌ路を傍供するものである。The invention was made in order to overcome the above-mentioned drawbacks, and the aim was to provide a standard pressure value with little variation in response to fluctuations in the threshold pressure.
It serves as a GL road.
以下不発明の実施例を８２図を用いて詳細に説明する。Hereinafter, an embodiment of the present invention will be described in detail using FIG. 82.
第２図に示す逼り、Ｐチャネルデブレツショ７ＭＯ８！
ＳのソースとゲートＦｉ電源の一端ＶＤＤＫ。As shown in Fig. 2, P channel debt 7MO8!
One end of the S source and gate Fi power supply VDDK.
ドレインは出力端子７００丁に接続芒ｎ１又Ｎチャネル
エンハンスメントＭ０８４のドレインとゲートは出力端
子ＶＯＵＴにソースはｔ＋％Ｉの他端ＧＮＤにそｎぞｎ
接１ｐｊｅざｎている。The drain is connected to the output terminal 700, and the drain and gate of the N-channel enhancement M084 are connected to the output terminal VOUT, and the source is connected to the other end GND of t+%I.
I'm close to 1 pje.
出力端子ｖｏａｔから出力嘔する基準電圧値をｙｏｏｔ
と丁ｎ＃ｉ畢麹路をａｒする゛廖護はそｎぞｎｉ ＝ｌ
ｐ（−１ｉｐ ｌ ）” −■ｉ ＝ ＫＭ （Ｖ
ＯＵ’ｒ −Ｖ’ｒｌｌ ）諺−■ＣＣに１ｍ’、［
ＭはそｎぞれＭ２Ｂ５とＭＯ８４の４１１１係砂て、ｖ
ｔｐとＶ？ＭＨ同じくＭ２Ｂ５とＭＯｔ３４のスレッシ
ョルド電圧である。The reference voltage value to be output from the output terminal voat is yoot.
And I'm going to go to Kojiro.
p(-1ip l)"-■i = KM (V
OU'r -V'rll) Proverb - ■ 1m' to CC, [
M is 4111 of M2B5 and MO84, respectively, and v
tp and V? Similarly to MH, this is the threshold voltage of M2B5 and MOt34.
ＫＰ＝ｘｍＫａ定すｎば
ＶｏＵＴ ｗ ｑＴＭ ＋ｌ Ｖ？Ｐ ｌ −＄ ト
４９１源１圧の一端ＶＤＤと他端ＧＮ、Ｄ間の電圧に依
存しない一足の定弯圧基準回路となる。If KP=xmKa is determined, then VoUT w qTM +l V? It becomes a constant pressure reference circuit that does not depend on the voltage between one end VDD and the other ends GN and D of the P l -$ source 1 voltage.
二股にプロ竜スによるｖＴＨの変＠ＵＶ？Ｂ−ＩＶテＰ
１の和は一定の関係で変動する◎
よって不発ＩＪＫＪ：ｆＬばプロセスパラメータのＶＴ
Ｍとｙｔｐの変＠に対して椿めてばらつきの少ない基準
電圧値を祷ることができる。VTH change @UV due to Proryusu in two forks? B-IVteP
The sum of 1 fluctuates in a certain relationship ◎ Therefore, misfire IJKJ: fL is the process parameter VT
It is possible to obtain a reference voltage value with very little variation with respect to variations in M and ytp.
更に基準電圧の−ａ度時性についてｔ正・負、ゼロいず
ｒＬＯｌをとることも可りヒである。Furthermore, it is also possible to take t positive/negative, zero or rLO1 for the -a degree temporality of the reference voltage.
即ち第２因において漏電−ＴにおけるＭ２Ｂ５のスレッ
ショルド電圧’ｔ ＶＴＰｓ Ｊ鴫係数をＫＰと＆倉、
又ｆｌｌｌｌｌＫ１１ｆＴＫｊＩＦけるＭＯＢ４のスレ
ッショルド電圧をＶ’ｒＭ、導電係数をＫＭとおくと、
基準電圧ｉｊ Ｖｏａｔ＝Ｖｔｍ＋ａｌＶｔ＋ｐｌ−
■ となる。That is, in the second factor, the threshold voltage of M2B5 at leakage -T is t VTPs J Shizu coefficient is KP and &Kura,
Also, if the threshold voltage of MOB4 in flllllK11fTKjIF is V'rM and the conductivity coefficient is KM, then
Reference voltage ij Voat=Vtm+alVt+pl-
■ It becomes.
ここにα＝Ｃ１τスｊ”である。Here, α=C1τsj''.
スレッショルド電圧Ｖ’ｒＭとｖｔｙｏｍｌｌ係畿をそ
ｎぞＴＬ Ｂｌ ＋ Ｂ曹とおき、導電係数に菫とＫＰ
のｉｉ＊係数をそｎぞれ０１うＣ１とおくと、
Ｖｔｍ ＝ｌｉｎ ＋Ｂ１ （Ｔ−Ｔ＠ ）−■ＶＴＰ
＋＝ＶＴＰ＃ ＋Ｂ、 （Ｔ−Ｔ、 ）−■Ｖｌｌφと
ＶＴＰφにそｎぞｎ室温の値ＫＭ＝ＫＭφ＋Ｃ１（Ｔ−
Ｔ６） −■ＫＰ＝［Ｐφ＋Ｏ，（Ｔ−’ｒ、 ）
−（ｊｌＫ”＊ ｅ ＫＰφ はそｎぞｎ室温の偵よ
って室温における基準電圧値は
Ｖｏｏｔ＄ ＝ ＶＴＩ ＋ａ。ｌ Ｖｔｍ４１−５Ｑ
）ここでαｏ＝ｎグｐ百Ｔである。Let's set the threshold voltage V'rM and vtyomll as TL Bl + B, and set the conductivity coefficient as violet and KP.
If the ii* coefficients of are respectively set as 01 and C1, then Vtm = lin + B1 (T-T@)-■VTP
+=VTP# +B, (T-T, )-■Vllφ and VTPφ respectively have the room temperature value KM=KMφ+C1(T-
T6) -■KP=[Pφ+O, (T-'r, )
-(jlK"* e KPφ is the same as the room temperature, so the reference voltage value at room temperature is Voot$ = VTI +a.l Vtm41-5Q
) where αo=ngp100T.
温［ＴＫｓ？ける基準電圧値は
Ｖｏａｔ ＝Ｖｔｍ ＋ａ １Ｖｙｐｌ −ｑｇ
となる。Warm [TKs? The reference voltage value is Voat = Vtm +a 1Vypl -qg
becomes.
漏１ｆＴＫおける１準電圧の変化１１に式（吟−■）ｔ
−ｔｌ：ＪＩして、■、■、■、■式を代人丁ｎばΔν
Ｏ（Ｉ？”！（Ｂｌ −〆αＢｙ）（Ｔ ％）
と な 夛１準電圧のＩＩＡ縦係数は
＃Ｖｏｕｔ ／ Ｊｔ Ｔ −Ｂ＊ −ｒｌＢ＊
Ｑ となる。The change in quasi-voltage at leakage 1fTK 11 is expressed by the formula (Gin-■) t
-tl: JI and change the expressions ■, ■, ■, ■ to the representative number Δν
O(I?”!(Bl −〆αBy)(T %)
The IIA vertical coefficient of the first quasi-voltage is #Vout / Jt T -B* -rlB*
It becomes Q.
ココでＢｌ ｍ Ｂ菅口Ｖ？ｌｌ・ＶテＰの固有の値で
あるがρ「はＫＰとＫＭの比に１って任意に選ぶことが
てきる。Bl m B Sugaguchi V here? Although ρ is a unique value of ll·VteP, it can be arbitrarily selected as 1 for the ratio of KP and KM.
よって不発明の基準電圧によｎば湛膚係Ｖを正、負、ゼ
ａいずｎが任意の債ＫＡぶことが可能である。Therefore, it is possible to set the voltage value V to be any value, whether positive or negative, using the uninvented reference voltage.
第１図は従来のだ電圧基準回路図であり、１８２図は本
発明の貢勝例１の足電圧羞準Ｕ路図である。
１・・・・・・Ｎ＋ヤネルデブレッショ７Ｍ０Ｂ２・・
・・・・ＵチャネルエンへンスメントＭ０８ＶＯ＋７７
・・・出力趨子
ｖＤＤ・・・電源電圧
ＩＭＤ・・・接地電圧
Ｖｔｍ１１・・・ＮチャネルテブレッションＭＯ８のス
レッショルド電圧
ＶＴＩＩＩ（・・・Ｎ＋ヤネルエン八へスメントＭＯｋ
３ｑ）スレッショルド電圧
３・・・・・・ＰチャネルデプレッションＭＯ８４・・
団・ＮチャネルエンハンスメントＭＯ８ＫＰ・・・ＭＯ
８トランジスタ５の導電係数ＫＭ ・・・Ｍ０８トラ
ンジスタ４の導電係数以 上
第１図
第２図
１ＪＤ
１６５−FIG. 1 is a conventional foot voltage reference circuit diagram, and FIG. 182 is a foot voltage standard U circuit diagram of Tribute Example 1 of the present invention. 1...N+Yanel Debrecho 7M0B2...
...U channel enhancement M08VO+77
... Output trend vDD ... Power supply voltage IMD ... Ground voltage Vtm11 ... Threshold voltage of N-channel tessellation MO8 VTIII ( ... N+Yanel en 8 hesment MOk
3q) Threshold voltage 3...P channel depression MO84...
Group/N channel enhancement MO8KP...MO
8 Conductivity coefficient of transistor 5 KM ...More than conductivity coefficient of M08 transistor 4 Figure 1 Figure 2 Figure 1 JD 165-
Claims (1)
ネルエンハンスメントＩＭＭＯ８ＩＰｆｆｉＴＯドレイ
ンどうしを接続して出力端子とすると共に、前ｉ１Ｆチ
ャネルＭＯ８ＦＢｌｊＴのソースとゲートを１源の−１
に、ドレインをＦｉＪ記出力熾子に各々接続し、灸に＋
１１１紀ＮチャネルＭＯＢＦＷＴのゲートを陶配出力趨
子に誉綬するとともに、ソースを前記１１１＃の他端に
接続して前記出力端子と前記’１１源の他端から一足な
出力の１圧１直を得ることを％書とした１準電圧発生１
！！ｌＷ！Ｉ０The drains of the P channel depletion field MOBIPWT and the N channel enhancement IMMO8IPffiTO are connected together to form an output terminal, and the source and gate of the previous i1F channel MO8FBljT are connected to the -1 source.
Then, connect the drains to the FiJ output terminals, and connect the moxibustion +
The gate of the 111th generation N-channel MOBFWT is connected to the output terminal, and the source is connected to the other end of the 111#, and a sufficient output voltage 1 is generated from the output terminal and the other end of the '11 source. 1 Quasi-voltage generation 1 with the aim of obtaining direct voltage as a percentage
! ! lW! I0
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2306082A JPS58140825A (en) | 1982-02-16 | 1982-02-16 | Generating circuit of reference voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2306082A JPS58140825A (en) | 1982-02-16 | 1982-02-16 | Generating circuit of reference voltage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58140825A true JPS58140825A (en) | 1983-08-20 |
Family
ID=12099880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2306082A Pending JPS58140825A (en) | 1982-02-16 | 1982-02-16 | Generating circuit of reference voltage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58140825A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102200792A (en) * | 2010-03-26 | 2011-09-28 | 罗姆股份有限公司 | Constant voltage circuit, comparator and voltage supervision circuit equipped therewith |
| CN104035472A (en) * | 2014-06-24 | 2014-09-10 | 吴江圣博瑞信息科技有限公司 | Full-CMOS (complementary metal oxide semiconductor) reference voltage source generator circuit |
-
1982
- 1982-02-16 JP JP2306082A patent/JPS58140825A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102200792A (en) * | 2010-03-26 | 2011-09-28 | 罗姆股份有限公司 | Constant voltage circuit, comparator and voltage supervision circuit equipped therewith |
| CN104035472A (en) * | 2014-06-24 | 2014-09-10 | 吴江圣博瑞信息科技有限公司 | Full-CMOS (complementary metal oxide semiconductor) reference voltage source generator circuit |
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