JPS58140646U - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPS58140646U
JPS58140646U JP3827182U JP3827182U JPS58140646U JP S58140646 U JPS58140646 U JP S58140646U JP 3827182 U JP3827182 U JP 3827182U JP 3827182 U JP3827182 U JP 3827182U JP S58140646 U JPS58140646 U JP S58140646U
Authority
JP
Japan
Prior art keywords
semiconductor device
resin
encapsulated semiconductor
lead
resin material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3827182U
Other languages
English (en)
Inventor
近藤　松悟
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP3827182U priority Critical patent/JPS58140646U/ja
Publication of JPS58140646U publication Critical patent/JPS58140646U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図及び第２図は従来の半導体装置の一例を示す一部
省略斜視図及びＸ−Ｘ線に沿う断面図、第３図は第１図
製品の電気配線図、第４図及び第５図は本考案の一実施
例を示す一部断面平面図及び側面図、第６図は第４図製
品の電気配線図、第７図は第４図製品の製造に用いるリ
ードフレームの平面図、第８図及び第９図は本考案の他
の実施例を示す一部断面平面図及びＹ−Ｙ線に沿う断面
図、第１０図は第８図製品の電気配線図である。 Ｔ□、　Ｔ２．　Ｔ３・・・半導体ペレット（トランジ
スタ）、１３〜１９・・・リード、２２・・・外装樹脂
材、ｍ、ｎ・・・タイバ一部、Ｄ□、Ｄ２．Ｄ３・・・
半導体ペレット（ダイオード）、２８〜３３・・・１−
ド、ｍ′ｎ′・・・タイバ一部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 複数の半導体ペレットを封入した外装樹脂材から各半導
    体ペレットと電気的接続された複数のリードを導出した
    樹脂封止型半導体装置であって、各リードの外装樹脂材
    より突出する部分を予めリードと一体に成形されたタイ
    バ一部で各半導体ペレットのそれぞれの電極の種類や極
    性に対応させて選択的に連結したことを特徴とする樹脂
    封止型半導体装置。
JP3827182U 1982-03-17 1982-03-17 樹脂封止型半導体装置 Pending JPS58140646U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3827182U JPS58140646U (ja) 1982-03-17 1982-03-17 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3827182U JPS58140646U (ja) 1982-03-17 1982-03-17 樹脂封止型半導体装置

Publications (1)

Publication Number Publication Date
JPS58140646U true JPS58140646U (ja) 1983-09-21

Family

ID=30049624

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3827182U Pending JPS58140646U (ja) 1982-03-17 1982-03-17 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPS58140646U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009272578A (ja) * 2008-05-12 2009-11-19 Nippon Inter Electronics Corp 樹脂封止型半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009272578A (ja) * 2008-05-12 2009-11-19 Nippon Inter Electronics Corp 樹脂封止型半導体装置の製造方法

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