JPS58140148A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the destruction of junction according to secular change of a semiconductor device by a method wherein a reversely conductive resistance region from a conductive semiconductor substrate and a conductive region the same conductive type with the resistance region thereof having impurity concentration lower than the resistance region thereof and to surround the resistance region thereof are formed in the conductive semiconductor substrate. CONSTITUTION:The P<+> type region 2 to come in contact with an aluminum wiring layer 3 is formed in the P<-> type region 9 having impurity concentration lower than the region thereof. Accordingly because P-N junction for protection to be formed between the N type substrate 1 is decided by depth of the region 9, even when an alloy layer is formed directly under the wiring layer 3, advance of the alloy layer thereof, namely penetration of aluminum up to reach the substrate 1 is prevented sufficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having means for protecting against excessive input such as static electricity.

Conventionally, input or output sections of semiconductor devices have been provided with input destruction protection means to protect them from excessive inputs such as static electricity or surges, especially in input circuit sections using MO8 type field effect transistors. As a means for preventing gate destruction, a protective PM junction diode is often provided. FIG. 1 is a schematic cross-sectional view showing the structure of a protective PN junction diode of such an MO8 field effect transistor. The aluminum wiring layer 3 and lead wire 4 are connected to the gate wiring layer 6 of an internal MO8 field effect transistor through the aluminum wiring layer 3, and the lead wire 4 is connected to an external input terminal. In addition,
In the figure, 6 and 7 are insulating films. According to the gate protection means having the configuration shown in the first diagram, the external input terminal and the gate of the MO8 field effect transistor are connected through the resistor in the pm region 2, so that the gate protection effect is reduced. However, a local alloy layer is formed between the aluminum wiring layer 3 and the P-trench region 2, and through this alloy layer there is an excessively high conductivity from the P-jaw region 2 to the R-type substrate. When a current flows, the alloy layer 8 locally advances to a deep part, and finally, as shown in FIG. 1, the alloy layer 8 reaches a depth exceeding the region 2 of P1, and becomes There is a problem in that the bond can be destroyed. Usually, the p”y
Region 2 of i is the source of the MO8 field effect transistor,
Since it is formed simultaneously with each region of the drain, the resulting junction is relatively shallow, and therefore, as the alloy layer 8 is formed and the effective depth of the py region 2 is reduced, this This is accompanied by the phenomenon that the breakdown current of the PN junction is concentrated in the alloy layer 8, and even if the initial characteristics are stable, the breakdown of the junction as described above may occur as a result of changes over time.

This invention solves the above-mentioned problems.

That is, in this invention, as shown in the cross-sectional view of the embodiment in FIG. It is something. According to the configuration shown in the second diagram above, the “
The protective PM junction formed between the mold substrate 1 and the P1
Since the depth is in the region 9, even if an alloy layer is formed directly under the aluminum wiring layer 3, the progress of the alloy layer, that is, the penetration of aluminum is sufficient to reach the N-type substrate 1. is prevented. This is because, in addition to the increase in the depth of the PN junction, the breakdown current caused by excessive input is appropriately dispersed by the presence of the P1 region 9, and the phenomenon of local heating due to the current does not occur. This is a major factor.

The r-type region 9 can usually be formed by low impurity concentration diffusion, but as in a complementary MO8 semiconductor device, N1
It can be implanted at the same time as a P-type well which is implanted when forming an N-type channel MO8 field effect transistor on the substrate 1. Also, according to experience, the depth of the P-type area is more than twice the depth of the p"W area 2, and the P-type area 9 is more than twice the depth of the P-jaw area 2. Sufficient effects can be expected by providing the same amount of distance on the side surfaces.

The present invention is not limited to the case where the N-type substrate 1 is used and the P-1 and PN regions 2 and 9 are formed thereon as in the above-mentioned embodiment; The present invention can also be constructed in the same way, and can be applied to integrated circuits on a single substrate, thereby making it possible to provide a desired input circuit section or output circuit section with useful protection means.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a conventional device, and FIG. 2 is a sectional view of a main part of an embodiment of the present invention. 1...N-type substrate, 2...p"W region, 3...aluminum wiring layer, 4...
Lead wire, 5... Gate wiring layer, 6.7.
...Insulating film, 8...Alloy layer, 9...
...P-type region. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 1'1

Claims (1)

[Claims] A resistor region of a conductivity type opposite to that of the substrate and a region of the same conductivity type and lower impurity concentration than the resistor region are formed in a semiconductor substrate of a predetermined conductivity type, surrounding the resistor region. A semiconductor device characterized in that a conference wiring layer is brought into contact with the region and connected to an external input terminal or output terminal.