JPS58140130A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58140130A JPS58140130A JP2320382A JP2320382A JPS58140130A JP S58140130 A JPS58140130 A JP S58140130A JP 2320382 A JP2320382 A JP 2320382A JP 2320382 A JP2320382 A JP 2320382A JP S58140130 A JPS58140130 A JP S58140130A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- insulator
- phosphorus
- semiconductor device
- vapor phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000012212 insulator Substances 0.000 claims abstract description 25
- 238000000576 coating method Methods 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 55
- 229910052698 phosphorus Inorganic materials 0.000 claims description 50
- 239000011574 phosphorus Substances 0.000 claims description 50
- 239000011521 glass Substances 0.000 claims description 41
- 238000001947 vapour-phase growth Methods 0.000 claims description 19
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 44
- 238000001259 photo etching Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 description 26
- 229910052751 metal Inorganic materials 0.000 description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000005260 corrosion Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000009499 grossing Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 241000208140 Acer Species 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 241001474791 Proboscis Species 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法にかかシ、とくに段差
を有する半導体装置の段部を滑らかにし。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and in particular, to smoothing a stepped portion of a semiconductor device having a step.
容易に微細な金鵬配麹を可能にする製造方法に関する。The present invention relates to a manufacturing method that allows fine Kinpo-distributed koji to be easily produced.
近年、半導体装置は、高密度化、高速化を実現する為に
、微細パターン化が進むとともに、多結晶シリコン層を
積極的に用いる技術が利用されている。例えば、シリコ
ンゲート型ＭＯ８半導体装皺では、多結晶シリコン層を
ゲート電極及び配線ルとして用いておシ、絶縁物を介し
て削記多結晶シリコン階を横切って金属配線層が形成さ
れている。これら多結晶シリコン服を用いる半導体装置
では、多結晶シリコン層を横切る金属配ＩＩＩが多結晶
シリコン層の段部で断線しないように、多結晶シリコン
層の段部を滑らかにしている。本発明は、多結晶シリコ
ン層段部に於ける金属配線の断線を防止するとともに、
樹脂封入に耐え得る信頼性を有する半導体装置の製造方
法に関するものである。2. Description of the Related Art In recent years, in order to achieve higher density and higher speed in semiconductor devices, fine patterning has progressed, and technology that actively uses polycrystalline silicon layers has been utilized. For example, in a silicon gate type MO8 semiconductor device, a polycrystalline silicon layer is used as a gate electrode and a wiring layer, and a metal wiring layer is formed across the etched polycrystalline silicon layer via an insulator. In semiconductor devices using these polycrystalline silicon layers, the stepped portions of the polycrystalline silicon layer are made smooth so that the metal wiring III that crosses the polycrystalline silicon layer is not disconnected at the stepped portions of the polycrystalline silicon layer. The present invention prevents disconnection of metal wiring in the stepped portion of a polycrystalline silicon layer, and
The present invention relates to a method for manufacturing a semiconductor device having reliability that can withstand resin encapsulation.
従来の多結晶シリコン層を用いている半導体装置の製法
について、シリコングー）５ＭＯ８ＩＣを例に１ｇ１図
を用いて説明する。A conventional method for manufacturing a semiconductor device using a polycrystalline silicon layer will be explained using FIG.
シリコン基板１上に通常の選択酸化法を用いて、フィー
ルド酸化膜２を形成した彼、熱酸化によシ、ゲート酸化
膜３を形成する。次に多結晶シリコンＦｆＩ４を全面に
形成し通常のフォトエッチングエ稚を用いて、ゲート電
極５及び配線用の多結晶シリコン〜のパターン６を形成
する。この場合バターニングされた多結晶シリコン層の
断面形状は、非常に急峻であるので、絶縁物を介して前
記多結晶シリコシ層を横切って形成された金・属配線は
、前記多結晶シリコン層の段部で切断される。この金属
配線の断線を防止する為従来の技術では、多結晶シリコ
ン層のパターンを形成した後、高濃度のリンを含んだリ
ンガラス膜７を気相成長法によ多形成し、高温熱処理を
行うことによって、リンガラス膜の流動性を利用して多
結晶シリコン層の段部の形状を滑らかにし、多結晶シリ
コン層を横断する配線金属８の形成を可能にしていた。A field oxide film 2 is formed on a silicon substrate 1 using a conventional selective oxidation method, and then a gate oxide film 3 is formed by thermal oxidation. Next, polycrystalline silicon FfI 4 is formed on the entire surface, and a pattern 6 of polycrystalline silicon for gate electrode 5 and wiring is formed using a normal photoetching process. In this case, since the cross-sectional shape of the patterned polycrystalline silicon layer is very steep, the metal/metal wiring formed across the polycrystalline silicon layer through the insulator is It is cut at the step. In order to prevent this metal wiring from breaking, in the conventional technology, after forming a pattern of a polycrystalline silicon layer, a phosphorus glass film 7 containing a high concentration of phosphorus is formed using a vapor phase growth method, and then subjected to high temperature heat treatment. By doing so, the shape of the stepped portion of the polycrystalline silicon layer is made smooth by utilizing the fluidity of the phosphorous glass film, and it is possible to form the wiring metal 8 that crosses the polycrystalline silicon layer.
しかしながら従来方法では、多結晶シリコン層段部を滑
らかにし、配線金属の断縁を防止することはできたが、
多結晶シリコン層の段部を滑らかＫする為に形成してい
た高濃度のリンを含んだリンガラス膜と配線金属が反応
を起し、配線金属が腐食されるという欠点があった。つ
ｔｂ、従来方法で製造した半導体装置を樹脂封入し、高
湿中で動作させた場合、樹脂中を浸入してきた水分とリ
ンガラス中のリンによシ、リン酸ができ、このリン酸が
配線金属を溶解させ、半導体装置の動作を不能にすると
いう重大な欠点があった。However, with the conventional method, it was possible to smooth the step part of the polycrystalline silicon layer and prevent the disconnection of the wiring metal.
There was a drawback that the wiring metal reacted with the phosphorus glass film containing a high concentration of phosphorus, which was formed to smooth the steps of the polycrystalline silicon layer, and the wiring metal was corroded. When a semiconductor device manufactured by the conventional method is encapsulated in resin and operated in high humidity, the moisture that has entered the resin and the phosphorus in the phosphorus glass combine to form phosphoric acid. This had the serious drawback of melting the wiring metal and rendering the semiconductor device inoperable.
仁の問題を解決する為に、リンガラス膜中のリン嬢度を
８モル参以下に下けれは配線金属の腐食は防止できたか
、リン濃度を下げたことによシリンガラス暎の充分な流
＆性が得られず、多結晶シリコン服の段差部で配線金属
が断線する。また配線金属の断線を防止する為に１多結
晶シリコン簾のパターンエツチング工程で、多結晶シリ
コン層の工、チング拶の形状にテーパーをつけようとす
ると、加工寸法精度か悪くなる等の間組があシ容易にこ
の間勉の解決をみる方法がなかった。In order to solve the phosphorus problem, it was found that if the phosphorus concentration in the phosphorus glass film was lowered to 8 mol phosphorus or less, corrosion of the wiring metal could be prevented. The metal wiring breaks at the stepped portion of the polycrystalline silicon clothing. In addition, in the pattern etching process of the polycrystalline silicon screen to prevent metal wiring from breaking, if you try to taper the shape of the polycrystalline silicon layer, the dimensional accuracy of the process will deteriorate, etc. There was no easy way to see Tsutomu's solution the other day.
本発明は、前述した欠点を解決しながら、多結晶シリコ
ン服の段部を滑らかにし、金楓配艙の断縁をなくすとと
もに、配線金属の腐食をなくし、かつ、微細パターン化
に逸した新規な製造方法に関するものである。つｔｂ、
本発明の目的とするところは、段差を有する半導体装置
の表面を滑らかにし、絶縁物を介して割記段差部を横断
する金属配線の断縁な防止するとともに、配線金属の腐
食をも防止する新規な製造方法を提供することにある。The present invention solves the above-mentioned drawbacks, smoothes the steps of polycrystalline silicon clothing, eliminates the disconnection of the metal maple distribution, eliminates corrosion of the wiring metal, and provides a new method that has not been achieved in the field of fine patterning. It relates to a manufacturing method. Tsutb,
It is an object of the present invention to smooth the surface of a semiconductor device having a step, to prevent metal wiring that crosses the marked step through an insulator from breaking, and to also prevent corrosion of the metal wiring. The objective is to provide a new manufacturing method.
すなわち本発明の％黴は、段差を有する半導体基板の表
面に、気相成長による第１の絶縁物を形成する工程と１
．塗布法による第２の絶縁物を形成する工程と、気相成
長による第３の絶縁物を形成する工程を含み、熱処理を
行うことによって、半導体基板の前記段部を滑らかにす
る半導体装置の製造方法にある。この場合気相成長によ
る第１及び第３の絶縁物が、４〜８モル優のリンガラス
膜であることが好ましい。又は、塗布法による第２の絶
縁物が８モル参以下のリンガラス膜であることが好まし
い。又は、気相成長による第１及び第３の絶縁物が、同
一のリン濃度を有するリンガラス膜であることが好まし
い。又は、気相成長による第１及び第３の絶縁物を形成
した彼の工程でそれぞれ高温熱処理を行い絶縁物の高温
における流動性を利用して段差部上の絶縁物形状を滑ら
かｋすることが好ましい。In other words, the mold of the present invention includes the step of forming a first insulator by vapor phase growth on the surface of a semiconductor substrate having steps, and step 1.
．． Manufacture of a semiconductor device including a step of forming a second insulator by a coating method and a step of forming a third insulator by vapor phase growth, and smoothing the stepped portion of the semiconductor substrate by performing heat treatment. It's in the method. In this case, it is preferable that the first and third insulators formed by vapor phase growth are phosphorus glass films having a concentration of 4 to 8 moles. Alternatively, it is preferable that the second insulator formed by coating is a phosphorous glass film having 8 mol sulfur or less. Alternatively, it is preferable that the first and third insulators formed by vapor phase growth are phosphorus glass films having the same phosphorus concentration. Alternatively, in his process of forming the first and third insulators by vapor phase growth, it is possible to perform high-temperature heat treatment on each insulator and use the fluidity of the insulator at high temperatures to smooth the shape of the insulator on the stepped portion. preferable.
以下１本発明をシリコングー）２ＭＯ８ＩＣに適用した
実施例について第２図を用いて説明する。An example in which the present invention is applied to a silicon 2MO8 IC will be described below with reference to FIG.
（１） シリコン基板上ｌに、フィールド酸化膜２を
通常の選択熱酸化によって０．８〜１．０μ程度形成す
る。この場合フィールド部分のシリコン基板表面濃度は
、フィールド部分の１′界による反ＩＩ２層の形成を防
ぐ為、他の部分よシも１桁程度濃くしておく。(1) A field oxide film 2 of approximately 0.8 to 1.0 μm is formed on a silicon substrate by ordinary selective thermal oxidation. In this case, the silicon substrate surface concentration in the field portion is set to be about one order of magnitude higher than in other portions in order to prevent the formation of an anti-II2 layer due to the 1' field in the field portion.
（２）通常の熱酸化によってゲート酸化膜３を１０００
Ａ＆度形成する。(2) Gate oxide film 3 is coated with a thickness of 1,000 yen by normal thermal oxidation.
A & degree formation.
（３） ８ｉＨ，ガスの熱分解を利用した減圧気相成
長法により、多結晶シリコン層４を全面に０．３〜０．
７μ程度形成する。(3) Polycrystalline silicon layer 4 is deposited on the entire surface with a thickness of 0.3 to 0.8iH by low pressure vapor phase growth using thermal decomposition of gas.
Form about 7μ.
（４） 通常のフォトエツチング工程を用いて、ゲー
ト電極５及び配置に６となる多結晶シリコン服のパター
ンを形成する微細パターンでかっｈ密な加工寸法を必要
とする場合、エツチング工程で社、平行平板型のドライ
エ、テング装置を用いているので、断面形状は、非常に
急峻となる。(4) Using a normal photo-etching process to form a polycrystalline silicon cloth pattern with a gate electrode 5 and arrangement 6, if a fine pattern and dense processing dimensions are required, the etching process Since a parallel plate type dryer and proboscis device are used, the cross-sectional shape is very steep.
（５） ソース、ドレイン領域及び多結晶シリコン４
５．６へ熱拡散法もしくはイオン注入法部によ）、不純
物をドープし、ソース、ドレイン領域の拡散層９．１０
を形成する。(5) Source, drain region and polycrystalline silicon 4
5.6) to dope impurities (by thermal diffusion method or ion implantation method) to form diffusion layers in the source and drain regions 9.10
form.
（６） ８１Ｈ４，ＰＨ，ガスを用いて獣素雰曲気中
で気相成長法によ）、８モルチ以下のリンを含んだ第１
のリンガラス膜１１をα２〜０．７μ程度形成する。(6) 81H4, PH, by vapor phase growth method in a beastly atmosphere using gas), the
A phosphor glass film 11 with a thickness of about α2 to 0.7μ is formed.
（７） ９００℃〜１１００℃の温度で熱処理を行い
、リンガ２不膜の流動性を利用して、多結晶シリコン層
段部を若干滑らかｋする。(7) Heat treatment is performed at a temperature of 900° C. to 1100° C., and the step portion of the polycrystalline silicon layer is slightly smoothed by utilizing the fluidity of the ringer 2 non-film.
（８）塗布法によってリンを含んだリンガラス膜法によ
るリンガラス膜は、段部に厚く、平担部に薄く形成され
るので第２図（Ｃ）に示すように段部な埋めるような形
状に形成できる。(8) The phosphorus glass film produced by the phosphorus glass film method, which contains phosphorus through the coating method, is formed thickly on the stepped portions and thinly on the flat portions. Can be formed into shapes.
（９） ８ ｉｎ、 ；ｐＨ，ガスを用いて％腋素雰
囲気中で気相成長法によシ８モル憾以下のリンを含んだ
第３のリンガマス膜１３をｏ、５〜ＬＯμ程度形成する
。塗布法によるリンガラス膜が多結晶シリコン層段部を
埋めるように形成されているので、多結晶シリ；ン脂段
部では、かなシ滑らかなリンガラス膜を形成することが
できる。(9) Form a third phosphorus mass film 13 containing 8 moles or less of phosphorus in a thickness of about 5 to LO μ by vapor phase growth in an atmosphere of 8 in. . Since the phosphorus glass film formed by the coating method is formed so as to fill the stepped portion of the polycrystalline silicon layer, a smooth phosphorus glass film can be formed at the stepped portion of the polycrystalline silicon layer.
Ｑ（１９００℃〜１１００℃の温度で熱処理を行い、リ
ンガラス膜の流動性をオＵ用して多結晶シリコン層の段
部を更に滑らかにする。Q (Heat treatment is performed at a temperature of 1900° C. to 1100° C., and the step portion of the polycrystalline silicon layer is further smoothed by utilizing the fluidity of the phosphorus glass film.
αυ 通常のフォトエツチング工程を用いて拡散層９及
び多結晶シリコン＆６からの電極引き出し用のコンタク
トホールを形成する。αυ Contact holes for leading out electrodes from the diffusion layer 9 and the polycrystalline silicon &6 are formed using a normal photoetching process.
醤 配緑金ＩＩ４を全面に被着し、通常の７オトエ、チ
ング工程を用いて、金属配線８のパターンを形成を行う
。The green metal II 4 is deposited on the entire surface, and a pattern of the metal wiring 8 is formed using the usual seven etching and etching processes.
（１３４００℃〜５００℃のフォーミングガス中でシン
ターを行い、配線金ｌＩ４８と拡散層９及び多結晶シリ
コン層６とのオーミックコンタクトを形成する。(Sintering is performed in a forming gas at 13,400° C. to 500° C. to form ohmic contact between the interconnection gold lI 48, the diffusion layer 9, and the polycrystalline silicon layer 6.
α尋 バ、シペーシ、ン用のリン刀フスＨｔ気相成長法
によシ全面に成形し、通常のフォトエツチング工程を用
いて電極引き出し用バット部を１孔して半導体装置の完
成となる。The semiconductor device is completed by molding the entire surface using a phosphor film Ht vapor phase epitaxy method for α-thickness bars, plates, and plates, and using a normal photoetching process to make one hole for drawing out the electrodes.
上記実施例に示したように、本発明によれは、多結晶シ
リコン層段部を気相成長によるリンガラス膜を形成した
彼、高温熱処理によって段部を若干滑らかＫし塗布法に
よるリンガラス膜を形成することによシ段部を埋め、再
び気相成長によるリンガラス膜を形成し熱処理によるリ
ンガラスの流動性を利用してさらに多結晶シリコン層段
部を滑らかにすることによって容易に微細な金属配線パ
ターンの形成を可能にできる。As shown in the above embodiment, according to the present invention, a phosphorus glass film is formed on the stepped portion of a polycrystalline silicon layer by vapor phase growth, and the stepped portion is slightly smoothed by high temperature heat treatment, and then a phosphorous glass film is formed by a coating method. The step part is filled by forming a polycrystalline silicon layer, a phosphorus glass film is again formed by vapor phase growth, and the fluidity of phosphor glass is utilized by heat treatment to further smooth the step part of the polycrystalline silicon layer. This makes it possible to form a metal wiring pattern with a wide range of shapes.
本実雄側において塗布法によるリンガラス膜で多結晶シ
リコン層段部を滑らかにした後、直に金属配線を形成し
た場合は、段部の滑らかさは不充分であシ、配線金属の
断線を引き起し、また、塗布法によるリンガラス膜は非
常に軟らかく、後工程の配線金属のパターン形成の際工
、チングされてしまうという欠点がある。If the step part of the polycrystalline silicon layer is smoothed with a phosphor glass film by coating method and then the metal wiring is formed directly, the step part will not be smooth enough and the metal wiring will break. Furthermore, the phosphorus glass film produced by the coating method is very soft and has the disadvantage that it is easily chipped during pattern formation of wiring metal in the subsequent process.
また、塗布法によってリンを含んだ酸化膜を形成し、多
結晶シリコン層段部を滑らかＫした後、熱処理によるリ
ンガラス膜の流動性を利用してさらに段部を滑らかＫし
ようとす為場合、塗布法によって形成したリンを含んだ
酸化膜を高温で熱処理を行うと酸化膜に亀裂が住じ、こ
の方法にも不具合がある。In addition, after forming an oxide film containing phosphorus by a coating method and smoothing the step part of the polycrystalline silicon layer, an attempt is made to further smooth the step part using the fluidity of the phosphorus glass film by heat treatment. However, when an oxide film containing phosphorus formed by a coating method is heat-treated at a high temperature, cracks form in the oxide film, and this method also has problems.
従って本発明で示したように、気相成長によるリンガラ
ス膜を形成して、高温熱処理によって段部を若干溝らか
にし、塗布法によるリンガラス膜で多結晶シリコン層段
部をかなシ滑らかにした彼、気相成長によるリンガラス
膜を形成し熱処理を行い、さらに段部を滑らかＫする方
法が、酸化膜亀裂を発生されることもなく、シかも多結
晶シリコン鳩段部を滑らかにし配線全島の断線を防止で
きる。Therefore, as shown in the present invention, a phosphorus glass film is formed by vapor phase growth, the step part is made slightly grooved by high temperature heat treatment, and the step part of the polycrystalline silicon layer is slightly smoothed with a phosphor glass film by coating. He found that the method of forming a phosphorous glass film by vapor phase growth, heat treatment, and smoothing the stepped portions could smooth out the stepped portions of polycrystalline silicon without causing cracks in the oxide film. Can prevent disconnection of all wiring islands.
次に、樹脂封止を行った前記製法を用いて作製した半導
体装置において、リンガラス膜中のリン濃度とＡＪの腐
食の関係を調べてみると、リンガラス膜中のリン濃度を
８モルチ以下にすれば配糾金−の腐食が起シ難くなる。Next, when we investigated the relationship between the phosphorus concentration in the phosphorus glass film and the corrosion of AJ in a semiconductor device manufactured using the above-mentioned manufacturing method in which resin sealing was performed, it was found that the phosphorus concentration in the phosphorus glass film was 8 molar or less. If this is done, corrosion of the metal oxide will be less likely to occur.
しかし、リンガラス膜の熱処理による流動性を−べた結
果、４モルラ以下では、リンガラス膜の熱処理による流
動性を観察することはできなかった。従って本発明に示
すように４モルＩｓ〜８モルー〇リンガラス膜を用いれ
ば、リンガラス膜の流動性を利用して、段部の形状をさ
らに滑らかにするとともに、リンガラス膜による配線金
楓の腐食を防止することができるＯ
また本実施例において、気相成長によって形成する第１
のリンガラス膜のリン濃度と第３のリンガラス層のリン
濃度を同一にすれば、作業ミスを防止でき製造管理上有
利であシ、また同一装置を用いて、第１のリンガラス層
、第２のリンガラス層を成長することができるのでｌ室
上非常に好都合である。However, as a result of examining the fluidity of the phosphorus glass film due to heat treatment, it was not possible to observe the fluidity of the phosphorus glass film due to heat treatment at 4 molar or less. Therefore, if a 4 mol Is to 8 mol phosphorus glass film is used as shown in the present invention, the fluidity of the phosphorus glass film can be utilized to further smooth the shape of the stepped portion, and the wiring metal maple formed by the phosphorus glass film can be made even smoother. In addition, in this example, the first
If the phosphorus concentration of the phosphorus glass film and the phosphorus concentration of the third phosphorus glass layer are made the same, it is possible to prevent operational errors and is advantageous in terms of manufacturing control. This is very advantageous in that it allows the growth of a second phosphorus glass layer.
さらに、気相成長によって形成した第１．第２のリンガ
ラス層と塗布法によって形成した酸化膜中のリン濃も同
一にすれば、同一の膨張係数１ ｒｅ！＋−の流動性を
有するので、高温の熱処理工程を行っても熱履歴による
ひずみ（クラ、り等→の発生を心配する必要がない。Furthermore, the first layer formed by vapor phase growth. If the phosphorus concentration in the second phosphorus glass layer and the oxide film formed by the coating method are also the same, the expansion coefficient will be the same, 1 re! Since it has +/- fluidity, there is no need to worry about the occurrence of distortion (cracks, cracks, etc.) due to thermal history even if a high-temperature heat treatment process is performed.
本実施例では、多結晶シリコン層による段差について述
べたが、高融点金属による段差についても同様である。In this embodiment, the step difference due to the polycrystalline silicon layer has been described, but the same applies to the step difference due to the high melting point metal.
また塗布法による酸化膜で段部を埋めたが、他の塗布法
によって形成できる高温熱処理に耐え得る絶縁物で本可
能である。Furthermore, although the stepped portions were filled with an oxide film formed by a coating method, it is possible to use an insulator that can be formed by other coating methods and can withstand high-temperature heat treatment.
本実施例では、シリコンゲート２ＭＯ８ＩＣについて述
べたが、他の半導体基板上に段差を有するすべての半導
体に＆について有効である。In this embodiment, a silicon gate 2MO8IC is described, but the present invention is also effective for all semiconductors having a step on a semiconductor substrate.
第１図は、従来法によるシリコン基板）ＩＪＭＯ８ＩＣ
の製造方法の例について示す図である。第２図は、本発
明による実施例のシリコンゲート型ＭＯ８ＩＣの製造方
法について示す図である。
図において、１・・・・・・シリコン基板、２・・・・
・・フィールド酸化膜、３・・・・・・ゲート酸化膜、
４・・・・・・多結晶シリコン、５・・・・・・ゲート
電極、６・・・・・・配線多結晶シリコン、７・・・・
・・高濃度リンガラス膜、８・・・・・・配線用会議、
９．１０・・・・・・拡散層、１１，１３・・・・・・
リンガラス膜、１２・・・・・・塗布法によって形成し
たリンガラス膜である。
第１図Figure 1 shows a conventional silicon substrate (IJMO8IC).
FIG. 2 is a diagram showing an example of a manufacturing method. FIG. 2 is a diagram illustrating a method of manufacturing a silicon gate MO8IC according to an embodiment of the present invention. In the figure, 1... silicon substrate, 2...
...Field oxide film, 3...Gate oxide film,
4... Polycrystalline silicon, 5... Gate electrode, 6... Wiring polycrystalline silicon, 7...
・・High concentration phosphorus glass film, 8・・・・・・Wiring meeting,
9.10...Diffusion layer, 11,13...
Phosphorus glass film, 12... Phosphorus glass film formed by a coating method. Figure 1
Claims (5)
による第１の絶縁物を形成する工程と、塗布法による第
２の絶縁物を形成する工程と、気相成長による第３の絶
縁物を形成する工程とを含み、熱処理を行うことによっ
て半導体基板の前記段部を清らかにすることを％黴とす
る半導体装置の製造方法。(1) A step of forming a first insulator by vapor phase growth on the surface of a semiconductor substrate having a step, a step of forming a second insulator by coating, and a third insulator by vapor phase growth. 1. A method of manufacturing a semiconductor device, the method comprising: forming a mold, and cleaning the stepped portion of the semiconductor substrate by performing heat treatment to remove mold.
〜８モルチのリンガラス膜であることを特徴とする特許
諸本の範囲第（１）項記載の半導体装置の製造方法。(2) The first and third insulators formed by vapor phase growth are 4
A method for manufacturing a semiconductor device according to item (1) of the patent books, characterized in that the phosphorus glass film has a thickness of 8 to 8 mol.
リンガラス膜であることを特徴とする特許論求の範囲第
（１）項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to item (1) of the patent claims, characterized in that the second insulator formed by the coating method is a phosphorous glass film having a molar density of 8 or less.
物が四−のリン濃度を有するリンガラス膜であることを
特徴とする特許論求の範囲第（１）項記載の半導体装置
の製造方法。(4) The semiconductor device according to item (1) of the patent claims, characterized in that the first and third insulators formed by vapor phase growth are phosphorus glass films having a phosphorus concentration of 4-. Production method.
した後の工程でそれぞれ高温熱処理を行い絶縁物の高温
における流動性を利用して段差部上の絶縁物形状を滑ら
かにすることを特徴とする特許蛸求の範囲第（１）項の
半導体装置の製造方法。(5) In the step after forming the first and third insulators by vapor phase growth, high-temperature heat treatment is performed on each insulator to smooth the shape of the insulator on the stepped portion by utilizing the fluidity of the insulator at high temperature. A method for manufacturing a semiconductor device according to item (1) of the patent claim, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2320382A JPS58140130A (en) | 1982-02-16 | 1982-02-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2320382A JPS58140130A (en) | 1982-02-16 | 1982-02-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58140130A true JPS58140130A (en) | 1983-08-19 |
| JPS6343886B2 JPS6343886B2 (en) | 1988-09-01 |
Family
ID=12104105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2320382A Granted JPS58140130A (en) | 1982-02-16 | 1982-02-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58140130A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61237449A (en) * | 1985-04-12 | 1986-10-22 | Ricoh Co Ltd | Manufacture of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5133575A (en) * | 1974-09-17 | 1976-03-22 | Nippon Telegraph & Telephone | TASOHAISENKOZO |
| JPS53105385A (en) * | 1977-02-25 | 1978-09-13 | Fujitsu Ltd | Manufacture for semiconductor |
-
1982
- 1982-02-16 JP JP2320382A patent/JPS58140130A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5133575A (en) * | 1974-09-17 | 1976-03-22 | Nippon Telegraph & Telephone | TASOHAISENKOZO |
| JPS53105385A (en) * | 1977-02-25 | 1978-09-13 | Fujitsu Ltd | Manufacture for semiconductor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61237449A (en) * | 1985-04-12 | 1986-10-22 | Ricoh Co Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6343886B2 (en) | 1988-09-01 |
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