JPS58137839A - Production of mask for semiconductor - Google Patents
Production of mask for semiconductorInfo
- Publication number
- JPS58137839A JPS58137839A JP57019546A JP1954682A JPS58137839A JP S58137839 A JPS58137839 A JP S58137839A JP 57019546 A JP57019546 A JP 57019546A JP 1954682 A JP1954682 A JP 1954682A JP S58137839 A JPS58137839 A JP S58137839A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- elements
- reticle
- semiconductor
- sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【発明の詳細な説明】
(発明の技術分野〕
この発明は半導体用マスクの製造方法にかか′す、特に
半導体素子の製造に用いられるマスク寸法を選定するた
めの製造方法を提供するものである。[Detailed Description of the Invention] (Technical Field of the Invention) The present invention relates to a method of manufacturing a semiconductor mask, and in particular provides a manufacturing method for selecting the dimensions of a mask used in the manufacture of semiconductor elements. be.
半導体基板に不純物拡散を施して活性領域の形成、電気
絶縁膜の写真蝕刻、電極ないし配線パターンの形成等が
施されて多数の半導体素子が形成されるが、上記をはじ
め多くの工程にマスクが用いられている。最近の半導体
装置の傾向として高密1化が進められるに伴なって、用
いられるマスクのパターンも着るしく微細化し、かつ、
その寸法精度によって作られる半導体素子の電気的特性
が大きく左右されるようになっている。実際に半導体素
子の製造に用いられるマスクはマスクの製造上からみる
とマスターマスクまたはコピーマスクで、これらはパタ
ーンサイズが例えば10倍に形成されたレティクルを縮
小して投影形成されている。従来の方法は第1図に示す
ように、相互の寸法に微差を設けたパターンサイズのレ
ティクルを例えば3種(図示省略)を作成し、これらか
らマスクを形成することによって3種のマスク(3)。A large number of semiconductor devices are formed by diffusing impurities into a semiconductor substrate to form active regions, photo-etching electrical insulating films, and forming electrodes or wiring patterns, but masks are used in many of the steps including the above. It is used. As the recent trend in semiconductor devices has been toward higher density, the patterns of the masks used have also become more and more minute.
The electrical characteristics of manufactured semiconductor devices are greatly influenced by the dimensional accuracy. A mask actually used in manufacturing semiconductor devices is a master mask or a copy mask from the viewpoint of mask manufacturing, and these masks are formed by projecting a reticle whose pattern size is reduced, for example, by 10 times. As shown in Fig. 1, the conventional method is to create, for example, three types of reticles (not shown) with pattern sizes that have slight differences in their dimensions, and to form masks from these three types of reticles (not shown). 3).
(B) 、 (Qを得る。ついで、これらのマスクを用
い、ウェハプロセスを経て半導体素子(X)、(白、(
d)を形成し評価して適合するマスクパターンの選定を
行なっていた。(B), (Q are obtained. Then, using these masks, semiconductor elements (X), (white, (
d) was formed and evaluated, and a suitable mask pattern was selected.
背景技術によれば、ウェハプロセスに常時生ずる微差に
よりマスクパターンの適否の判定を誤ることが多く、ま
た、レティクルも例えば3枚を必要とするので高価につ
(などの問題点がある。According to the background art, there are problems in that the suitability of the mask pattern is often erroneously determined due to slight differences that constantly occur in the wafer process, and that the reticle is expensive because it requires, for example, three reticles.
この発明は背景技術の問題点を改良するための半導体用
マスクの製造方法を提供する。The present invention provides a method for manufacturing a semiconductor mask to improve the problems of the background art.
半導体素子の製造に用いるガラスマスクの製造にあたり
、予め1枚のレティクルに順次寸法の微差を有する複数
のマスク要素を形成し、上記マスク要素の中から要求さ
れる半導体素子の電気的特性に適合するものを選定する
ものである。When manufacturing a glass mask used in the manufacture of semiconductor devices, a plurality of mask elements having slight differences in dimensions are sequentially formed on a single reticle in advance, and one of the mask elements is matched to the required electrical characteristics of the semiconductor device. The purpose of this is to select the items to be used.
次にits例tごつき図面を参照して詳細1こ説明する
。第2図に示すマスク(財)(マスターマスクまたはコ
ピーマスク)には1枚のレティクル(図示省略)に形成
されたものと同じ、1例として3つのマスク要素(AI
) 、(Bt) 、 (C1)が行または列ごと1ご整
列配置されている。次に、このマスクによってウェハプ
ロセスを施し、1回のウェハプロセスでマスク(AI)
、 (1,(C−による半導体素子(AI’)。Next, details will be explained with reference to the drawings of its example. The mask (master mask or copy mask) shown in FIG. 2 includes three mask elements (AI
), (Bt), and (C1) are arranged one by one in each row or column. Next, a wafer process is performed using this mask, and the mask (AI) is formed in one wafer process.
, (1, (Semiconductor element (AI') by C-.
この発明によれば、まず、1枚のレティクルで3つのマ
スク要素が収められるので従来3枚要したレティクルが
1枚で済むという経済上の利点と、3枚のレティクルを
作成し夫々をマスクに形成しさらにウェハプロセスを流
す労力、およびウェハ、ウェハプロセスなどあらゆる面
での資材、労力、時間が大幅に節減できる。次lこ、ウ
ェハプロセスが1回で済むので、工程の処理条件に対す
る微少のばらつきが問題でなくなる。これはマスク要素
の選定を行なう場合が多い上に時間的に急がれることに
対しても著効がある。According to this invention, first, three mask elements can be accommodated in one reticle, so one reticle is required instead of three in the past, which is an economical advantage, and three reticles can be created and each can be used as a mask. The effort required to form and carry out the wafer process, as well as the materials, labor, and time involved in all aspects of wafers and wafer processing, can be significantly reduced. Next, since the wafer process only needs to be carried out once, slight variations in process conditions are no longer a problem. This is extremely effective when selecting mask elements, which is often done in a timely manner.
第1図は従来の方法を説明するための工程図、第2図は
1実施例の方法を説明するための工程図である。
AH* J s CI マスク要素A、 、B、
、C,半導体素子
M マスクFIG. 1 is a process diagram for explaining a conventional method, and FIG. 2 is a process diagram for explaining a method of one embodiment. AH* J s CI Mask elements A, , B,
, C, semiconductor element M mask
Claims (1)
、予め1枚のレティクルで順次寸法の微差を有する複数
のマスク要素を形成し、上記マスク要素の中から要求さ
れる半導体素子の電気的特 ′性ζこ適合するものを選
定することを特徴とする半導体用マスクの製造方法。In order to manufacture a glass mask used in the manufacture of semiconductor devices, a plurality of mask elements having minute differences in size are sequentially formed using one reticle in advance, and the required electrical characteristics of the semiconductor device are determined from among the mask elements. 1. A method for manufacturing a semiconductor mask, characterized by selecting a mask that is compatible with the characteristics ζ.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57019546A JPS58137839A (en) | 1982-02-12 | 1982-02-12 | Production of mask for semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57019546A JPS58137839A (en) | 1982-02-12 | 1982-02-12 | Production of mask for semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58137839A true JPS58137839A (en) | 1983-08-16 |
Family
ID=12002308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57019546A Pending JPS58137839A (en) | 1982-02-12 | 1982-02-12 | Production of mask for semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58137839A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55129333A (en) * | 1979-03-28 | 1980-10-07 | Hitachi Ltd | Scale-down projection aligner and mask used for this |
JPS55132039A (en) * | 1979-04-02 | 1980-10-14 | Mitsubishi Electric Corp | Forming method for repeated figure |
JPS55165629A (en) * | 1979-06-11 | 1980-12-24 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS5634142A (en) * | 1979-08-25 | 1981-04-06 | Hitachi Maxell Ltd | Magnetic recording medium |
-
1982
- 1982-02-12 JP JP57019546A patent/JPS58137839A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55129333A (en) * | 1979-03-28 | 1980-10-07 | Hitachi Ltd | Scale-down projection aligner and mask used for this |
JPS55132039A (en) * | 1979-04-02 | 1980-10-14 | Mitsubishi Electric Corp | Forming method for repeated figure |
JPS55165629A (en) * | 1979-06-11 | 1980-12-24 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS5634142A (en) * | 1979-08-25 | 1981-04-06 | Hitachi Maxell Ltd | Magnetic recording medium |
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