JPS5813517Y2 - Recording level setting device - Google Patents

Description

[Detailed explanation of the invention] This invention is a tape recorder constructed using a digital circuit←
This relates to a recording level setting device such as the above.

Conventionally, in recording level setting devices such as tape recorders, an analog circuit, that is, a peak holding circuit using a capacitor, is generally used to set the recording level, but since the hold time is in seconds, The drawback was that it was extremely difficult to set the recording level.

The present invention was developed in view of the above-mentioned drawbacks, and it is possible to sufficiently lengthen the holding time of the peak value, and in order to swing the level meter of a tape recorder, etc., an AC signal voltage equivalent to the held peak value can be generated. It is an object of the present invention to provide a recording level setting device which makes it extremely easy to set the recording level and which is constructed simply and inexpensively using a digital circuit.

An embodiment of the present invention will be described below with reference to the drawings.

Fig. 1 is a circuit diagram showing one embodiment of the device of the present invention;
The figure is a time chart of waveforms at various parts of the circuit.

In Fig. 1, ζ1 is a comparator, 2 is a digital counter, Ra-Rd and Ra1 to Rd□ are ladder resistances, comparator 1, counter 2, ladder resistance Ra
-Rd XRa =Rd 1 constitutes a peak value holding section that holds the peak value of the input signal.

3 is Nantes Gate N1. N2, a square wave oscillator consisting of a resistor, a capacitor, etc., Na-Nd is a Nant gate, R0 to R4 are resistors, and the resistance values of these resistors R1 to R4 are respectively in the ratio of 8:4:2:1 with a double cord. By setting , addition and weighting are performed simultaneously via resistor R5 and amplifier 4.

The gate and adder together form an AC signal generating section that generates a signal with a voltage equivalent to the peak value held.

The device is started by resetting the contents of the counter to zero using the reset switch of counter 2.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the timing chart shown in FIG.

The unswitched input signal a is converted into DC by the diode D1,
Input b shown by a solid line at one terminal of the input of comparator 1
Added as 1.

The output C of the comparator 1 is input to the counter 2, and the pulse d of A-D is outputted to the output of the counter 2.

These pulses d are caused by the ladder resistance Ra = Rd and the resistance Ra
1 to Rd1, and is further applied to the other input terminal of the comparator 1 as a signal b2 shown by the dotted line in b in FIG. 2, and compared with the signal b1.

When the counter 20 count number increases, the ladder resistance R
The analog output signal b2 converted by a to Rd and Ra1 to Rd also increases, and this output signal b2
No pulse will appear at the output of comparator 1 unless a larger input signal b□ is input.

In this way, the peak value of input signal a is determined by the counter 2.
is retained as the output of

The binary code output d(A-D) of the counter 2 held at this peak value is input to one terminal of the NAND game (Na-Nd), respectively.

In addition, the output e of a square wave oscillator 3 consisting of a Nand gate N1, N2, a resistor, a capacitor, etc. is input to the other terminal of the Nand's gate (Na-Nd).

Since the square wave oscillator 3 is composed of a logic circuit, the signal e
is "1" and "O", or ") (It L Il+
It has two levels of 1010, . . . square waves.

The counter outputs A to D of the 204-bit counter control the output signal e of the square wave oscillator 3 which is input to the other end of the Nant gates Na to Nd.

When the counter output is at the "1" level, a square wave appears in the output of the Nant's gate, and when the counter output is at the On level, the output of the Nant's gate is always at the "1" level.

This situation is shown by the timing chart d-f in FIG.

These Nant gate outputs are each added and have the weight of the binary code, so when adding them, it is necessary to add the ones with corresponding weights lost.

In the embodiment, if the resistance values of the resistors R1 to R4 are set at a ratio of 8:4:2:1, addition and weighting are performed simultaneously via the amplifier 4 and the resistor R5.

In this case, since the output of the amplifier 4 is connected to a tape recorder or the like, it is necessary to remove harmful direct current components, so capacitors are inserted into the outputs of the Nandt gates Na to Nd, respectively.

In this way, the peak value of the input signal a is held as a counter output, and a square wave output equal to the peak value is obtained as the adder output g in FIG.

A square wave output is sufficient to cause the level meter to swing and does not necessarily have to be a sine wave.

As described above, in this invention, the circuit that holds the peak value of the input signal and the circuit that generates the AC signal equivalent to the peak value are configured digitally, so the peak holding time can be sufficiently long and level setting is extremely easy. Moreover, the circuit configuration is simple and inexpensive.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the recording level setting device of the present invention, and FIG. 2 is a timing chart of the same circuit. In the figure, 1: Comparator, 2: Counter, 3: Square wave oscillator, 4- Amplifier, D- Diode, Ra=RdXR
a1~Rdl: Ladder resistance, Na~Nd% N1
, N2: Nand Gate.

Claims (1)

[Scope of utility model registration request] It consists of a peak value holding section that holds the peak value of the input signal, and an AC signal generation section that generates an AC signal equivalent to the peak value. A comparator that compares the value with
The AC signal generator includes a counter that outputs a signal according to the output from the converter, and the AC signal generator includes a plurality of gate circuits that control on/off the output from the oscillator according to the output from the counter, and A recording level setting device comprising an adder for adding outputs.