SU1370756A1 - Comparator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in analog-to-digital converters (ADC), in threshold devices of precision measuring equipment, in particular when monitoring the accuracy of parameters of microelectronic digital-analog converters and ADCs. The purpose of the invention — improving accuracy and resolution — is achieved by eliminating the influence of destabilizing factors. The device contains terminals 1 and 2 for connecting the comparison voltage, key modulators 3 and 4, differential amplifier 5, terminal 8, voltage divider 9, comparator 10, triggers 11, 23, counters 12.24, JK-trigger 13, integrators 14, 20, block 15 threshold elements, phase-sensitive detector 16, switches 17 and 18, elements AND 19.21 and 22.26, multiplexer 25, element 27 Iira-I, delay elements 28 and 29, driving oscillator 30, terminal 31 launch. Compared with the known, the proposed device has a high accuracy and resolution. This is provided by an additional balancing of the modulated signal and its integration with the coupling of control signals to the phase of the mains voltage. 3 il. e (L

Description

00 about SP

Od

The invention relates to a pulse technique and can be used in analog-to-digital converters (AUII), in threshold devices of a precision meter (equipment, in particular when monitoring the accuracy parameters of microelectronic PAP and ADC.

The aim of the invention is to improve the accuracy and resolution of its ability by changing the influence of destabilizing factors.

FIG. 1 shows a functional diagram of the device, FIG. 2 and 3 are diagrams of voltages at the outputs of the main elements of the device.

The comparison device contains terminals 1 and 2 connections are comparable

The first element And 19 and with the output of the second bit of the first counter 12, the counting input of which is connected to the output of the third element And 22, and the output of the third discharge is connected to the second (inverse) input of the third element And 22, the first input of which is connected to the control input of the first key modulator 3, to the control input of the phase-sensitive detector 16 and to the output of the second trigger -23, the counting input of which is connected to the high-gain output of the second counter 24 and to the high-bit input of the multiplexer 25, the remaining control inputs of which th bitwise connected to the outputs of the second counter 24 whose input is connected to vyho

voltages to the inputs of the first key fourth fourth element I 26, the first modulator 3, the second key modulator 4, the differential amplitude of which is connected to the output of the JK flip-flop 13 and to the input of the V-resolution of the multiplexer 25, n high and The first information inputs of which are connected to a single-level voltage source, and the rest are connected to a zero bus, the output is connected to the first input of the W1N element 27 and through the first delay element 28 to the control input of the second key modulator 4 and the second delay element 29, out which is connected to the second input of the element 1 27, the output of which is connected to the control input of the first switch 17, and the output of the master oscillator 30 is connected to the second input of the fourth element And 26 and to the synchronization input of the JK trigger 13. The input of which is connected to zero bus, and the input zeroing R is connected to the triggering terminal 31.

5, while the output of the first key modulator 3 is connected through a circuit) 1sator 6 to the first input of the second key modulator 4 connected via a resistor 7 to a common bus connected to the second input of the second modulator 4, the coohHineH with I} with the woody input of the differential amplifier 5, and the terminal 8 connects the mains voltage through the voltage divider 9 connected to the forward input of the comparator 10, the inverse input of which is connected to the general iiniHoii, and the output connected to the counting input of the first trigger 11, direct output which is connected to the zeroing input of the first counter 12, to the J-input of the JK-trigger 13, and the inverse to the input to the zero of the PII of the first I1 of the integrator 14, the output of which is connected to the input of the block 15 of the threshold elements, and the input connected to the phase-sensitive detector 16 There is a switch 17 and with the first input of the second 18, the control input of which is connected to Biii- stroke of the first element I 19, the second input is connected to the main bus, and the output is connected to the input of the second integrator 20, the output of which is connected to the pr. amplifier 6, and the zero input is output This is the second element of element 21, the dervine of which is connected to the first input of the first element I 19 and c. the output of the first Bogo discharge of the first 5S (t of the counter 12, and the second, inverse input of the HTiiporo element I 21 is connected to the second (1 m BXOZTOM

0 house of the fourth element And 26, the first

5 0 5 0

five

0

five

the input of which is connected to the output of the JK-flip-flop 13 and to the input of the V-resolution of the multiplexer 25, the higher and lower informational inputs of which are connected to a voltage source of one level, and the rest is connected to the zero bus, the output is connected to the first input of the Sh1I element 27 and through the first delay element 28 to the control input of the second key modulator 4 and to the input of the second delay element 29, the output of which is connected to the second input of the element 1 shiro 27, the output of which is connected to the control input of the first switch 17, and I ask The generator 30 is connected to the second input of the fourth element I 26 and to the synchronization input of the JK flip-flop 13. Its input is connected to the zero bus, and the zero input R is connected to the triggering terminal 31.

The device works as follows.

The compared voltages U and U are applied to terminals 1 and 2. Terminal 8 is supplied with alternating voltage (presumably from the secondary winding of the mains transformer of the power supply unit of the device) with a frequency of 50 Hz. In the initial state 1, terminal 31 has a high voltage level which keeps trigger 13 in the zero state. An alternating voltage of 50 Hz is driven by divider 9 to the level required for the normal operation of the voltage comparator 10. Starting the device is performed by applying to terminal 31 a zero

potential (logical zero -0). Thus, switching to the single state of the JK-flip-flop 13 occurs after the comparator Yu changes its state on the front of the pulse arriving at the synchronous input of the JK-flip-flop 13 from the output of the master oscillator 30. At the transition of the JK-flip-flop 13 to the single state element 26 is opened and permission is given (input v) for operation of multiplexer 25.

Figure 2 shows the voltage plots generated at the outputs of multiplexer 25 and trigger 23, where it is shown that the front Ujj is in the middle of a pulse. The beginning of the formation of these voltages i occurs at the signal from the output of the JK-flip-flop 13. Thus, control signals are tied to the phase of the network signal (-50 Hz). At the input of the JK-flip-flop 13, the pulses come from the output of the flip-flop 11 with a frequency of 25 Hz and a duty cycle of 2. As a result, 20 ms at the zeroing input of the R-counter 12 there is a level keeping the counter 24 in the zero state. The unit voltage level, taken from the output of the JK-flip-flop 13, opens the element 26 at the moment of the network signal passing through the zero level. In this case, the counting pulses arrive at the input of the counter 24, which controls the operation of the multiplexer 25. At the output of the multiplexer 25, pulses and a high duty cycle are formed. The middle of these pulses coincides with the front of pulses taken from the output of trigger 23 (diagrams, U ,,, Fig. 2) On the fronts of signals taken from the output of trigger 23, the duty cycle of which is two and does not depend on the pulse ratio of the master oscillator 30, and the pulses taken from the output of the delay element 28, the key modulators 3 and 4 are switched. As a result, a resistor 7 produces an alternating voltage, generally asymmetrical about the zero level. This is due to the fact that the emissions (glitches) in the positive region in principle cannot be equal to the emissions in the negative voltage region, in turn, due to the different parameters of the sources of the compared voltages, due to different length, inductance

- Q

J5 20 25 so, - -dd. d

50

five

and capacitances of conductors connecting the sources of the compared voltages. Emissions at resistor 7 (FIG. 3, U), occurring at the moment of switching the key modulator 3, also depend on the values of the compared voltages and in the range of the compared voltages of 10 V can reach several hundred millivolts.

Thus, the signal U, coming from the output of the key modulator 4 to the inverting input of the differential amplifier 5, does not lead to an appreciation of the differential amplifier 5 on the entire time axis. The amplified signal Uy, removed from the output of amplifier 5, is gated by means of switch 17 so that you & dew, arising along the fronts of the control signal with key modulator 4, passed through amplifier 5, amplified by K ,, times (K "is the gain the differential amplifier 5) does not pass to the input of the controlled switch 17.

The delay elements 28 and 29 and the logic element OR 27 form pulses, and gating the measurement signal so that the output of the controlled switch 17 contains no glitches on the measurement signal U, j (Fig. 3).

Suppose that the feedback circuit of the differential amplifier 5 through switches 17 and 18 and the integrator 20 is open, and its non-inverting input is connected to the common bus. In this case, the stepwise measuring signal is also not symmetrical with respect to the zero level (FIG. 3 and), and, and Uj. Considering a signal as a function consisting of the sum of a periodic component and a constant level, we can write

and „f (t) and ,, (1)

where f (t) is a periodic function

and „- constant level. If we integrate over the period T, where T is the period Uj,, then the voltage at the integrator output is 20

equally

t

and, i J (f (t) (/ „) dt | and„.)

about

where T is the time constant of the integrator 20;

Ku - transfer coefficient of the integrator 20.

Let the signal 5 on the inverting input of the amplifier 5 and (Fig. 3) also represent the sum of the periodic function and the constant component

q (t) + c., (3)

With offset 1

In this way, the integrator 20 is reset by resetting from output 21, and then connecting the input of integrator 20 to the output of switch 17 by means of switch 18 (plot UjQ, FIG. 3). The formation of the next value of the compassing level occurs through

F) The differential input is 10 ms at the input. Net integration time

for integrator 14 is 20 ms, which excludes the influence on the accuracy and measurement of the network pickup on high-resistance measuring channel and input circuit

Single 5 for a closed system, you can write

- chso-ls

(and, to

+ 1

f (t) + Un

CM

By expanding the brackets in the expression by grouping the members, we get

 (4) (4) and

-q (t) k. -C-KU + Un (Ku K

  f (t).

-l) .K

(t); 45)

Balancing the step signal Uf. consisting of a positive pulse in amplitude T (J, and negative amplitude Uj before receiving a signal U with amplitude UL (dotted plot line U,,

Fig. 3), where C - - - - - 5 is carried out, - by introducing feedback g Media

switches 17 and 18 and integrator 20.

The absence of the signal amplitude Uj constant component at the output of the switch 17 suggests that the non-periodic terms of the expression (5) are directed to zero value

, (k, k, -1) + (6)

From vfazheni (6) we get

Un (С - 1. „) / К .. (7)

Thus, an introduction to a gadget detector, two integrators, two counting triggers, a JK trigger, a voltage divider, a comparator, two

Comparison of the amplifier with the integrator 45 OR, the multiplexer, the first and second rum in the feedback circuit leads the counters, the chip of the AND element, phase-sensing not only to the balancing of the measuring signal, but also to the reduction of the measurement error due to the non-ideality of the differential force itself. gg controlled switch, tel 5 terminal at. The formation of a compensating voltage coming to the non-inverting input of amplifier 5 occurs in the time interval when the integrator 14 is zero. In this interval, the counter 12 is operating in de55 mode

connecting a trigger signal, a capacitor, a resistor and a terminal for connecting a mains voltage; the output of the first key modulator is connected via a capacitor to the first input of the second key modulator connected through a resistor to a common bus connected to the second input of the modulator, the output of the frequency converter, by means of elements, And 19 and 21 pulses of duration T, placed on a temporary

07566

axes in such a way that the integrator 20 is first resetted by the signal from output 21, and then g is connected to the input of integrator 20 to the output of switch 17 by means of switch 18 (diagrams UjQ, fig. 3). The formation of the next value of the compensating level occurs through

 ms Net integration time

for integrator 14 is 20 ms, which excludes the influence on the measurement accuracy of the network pickups on the high impedance circuit of the measuring channel and the input circuits of the integrator 20 due to the zero integration of the periodic signal. In addition, integration eliminates random failures and improves the accuracy of comparisons. In general, the proposed device, in comparison with known devices, has a high accuracy and resolution, which is achieved by an additional balancing of the modulated

signal and its integration at the frequency

terval l / f. where

in the mains supply, with control signals connected to the mains voltage phase.

Claims (1)

Invention Formula A comparison device containing the terminals for connecting the compared voltages, a block of threshold elements, a master oscillator, a differential amplifier, two key modulators, to the inputs of the first of which are connected the terminals for the comparison of the compared voltages, in order to improve the accuracy and resolution, additionally introduced the first and second delay elements, the element detector, two integrators, two counting triggers, JK-trigger, voltage divider, comparator, two OR, multiplexer, first and second counters, element AND circuit, phase-shifting controlled switches, terminal OR, multiplexer, first and second counters, element AND circuit, phase-shifting controlled switches, terminal connecting a trigger signal, a capacitor, a resistor, and a terminal for connecting a mains voltage; the output of the first key modulator is connected via a capacitor to the first input of the second key modulator connected through a resistor to a common bus connected to the second input of the modulator whose output is 713 poro is connected to the inverter input of a differential amplifier, and the mains voltage connection terminal is connected via a voltage divider to the direct input of a comparator, whose inverse 4th pass is connected to the common bus and the output is connected to the counting input of the first trigger, the forward output is connected to the zero input of the first counter, to the J-input of the JK-flip-flop, and inverse to the zeroing input of the first integrator connected by Vphod to the input of the block of threshold elements, and the input is connected via a phase-sensitive detector with the output About the switch and with the first input BTopoi o, the control input of which is connected to the output of the first element I, the second input is connected to the common input, and the output is connected to the input of the second integrator connected to the front input of the differential amplifier, and neither with the output of the second element And, the first input of which is connected to the first input of the second element And and with the output of the first discharge of the first counter, the second input BTopoi o of the element And is connected to the second input of the first element And and with the output the second about the discharge of the first counter, sch the input of which is connected to the output of the third ettement, and the output of the third discharge is connected to the input 0756 ° the third element II, connected by the first input to the control input of the first key modulator, to the control input of the phase-sensitive detector and to the output of the second trigger, the counting input of which is connected to the high-voltage output of the second counter and the control input of the older TO bit of the multiplexer, which inputs are connected in series with the outputs of the second counter connected by the input to the output of the fourth element I, the first The 15 input of which is connected to the output of the JK-flip-flop and to the input V of the resolution of the multiplexer; delays - to the control input of the second key modulator and to 25 to the input of the second delay element, the output of which is connected to the second input of the OR element connected by the output to the control input of the first 1G (; p; switch, the generator setting output of the generator is connected to the second input of the fourth element I and the synchronization input of the JK trigger, K The input of which is connected to the zero bus, and the zeroing input R is connected to the trigger signal terminal. %% ige ig TP P m P P q tJ2 P pp pp and P1 t3Z  n p n p nt Ui UL five 7 gums Sarssintech  l and pp pp P1 CSooc Integr. 7 Shos Integral Raootin-t mf} .20u  lus fie.Z