JPS58134304A - Monitor device - Google Patents

Monitor device

Info

Publication number
JPS58134304A
JPS58134304A JP57017318A JP1731882A JPS58134304A JP S58134304 A JPS58134304 A JP S58134304A JP 57017318 A JP57017318 A JP 57017318A JP 1731882 A JP1731882 A JP 1731882A JP S58134304 A JPS58134304 A JP S58134304A
Authority
JP
Japan
Prior art keywords
pulse
elements
signal
pulses
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57017318A
Other languages
Japanese (ja)
Inventor
Takami Sakai
堺 高見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57017318A priority Critical patent/JPS58134304A/en
Publication of JPS58134304A publication Critical patent/JPS58134304A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00Safety arrangements
    • G05B9/02Safety arrangements electric
    • G05B9/03Safety arrangements electric with multiple-channel loop, i.e. redundant control systems

Abstract

PURPOSE:To monitor a fault with high accuracy with a device that integrates plural pulse input signals, by deciding a fault when a signal which is not coincident with other signals is detected and that the detected signal has no change for a period longer than a prescribed time. CONSTITUTION:Input signals UA-UC are fed to one side of each of OR elements 12-14, and the outputs of these OR elements are supplied to AND elements 15-17 and an OR element 18 which form a 2-out-of-3 circuit. Discordance detecting circuits 20-22 deliver 1 when the pulses are not coincident with each other. Timers 35-40 deliver 1 when the pulse supplies 1 for a period longer than a prescribed time. The circuits 20 and 22 are set at an output 1 with the output of an AND25 and the timer 35 set at 1 respectively when pulses UB and UC are set at 0 with only the pulse UA kept at 1. Thus it is decided that the pulse UA is faulty. An approximately similar operation is carried out when the pulses UB and UC are set at 1 with only the pulse UA kept at 0. Then it is also decided that the pulse UA is faulty. In such a way, a fault of an input signal is detected with high accuracy.

Description

【発明の詳細な説明】 〔斃明の技術分野〕 本宛#4は、多重化された装置の出力信号の内。[Detailed description of the invention] [Bunmei's technical field] Direct address #4 is among the output signals of the multiplexed device.

いづれの出力01号が異常かをすみゃかに検出する為の
監lI装置K11iする。
A monitoring device K11i is used to instantly detect which output No. 01 is abnormal.

〔斃明の技術的背景〕[Technical background of Shumei]

籐1−及び#&2図は、多1化された装置の構成−を示
す。第11[において、J〜Sは、例えば鯛#装置であ
り、その出力信号は、装置4によって一つの信号に集約
される。又、亀2園は、上記制御装置1〜Sの出力信号
を装置5〜1によってインターロックやタイミング協調
な纏って次段の制御装置1l−jFへ信号な送信し、災
に装置JJKよって−っの信−1tにIs約される。
Figures 1 and 2 show the configuration of a multi-unit device. In the eleventh [, J to S are, for example, sea bream # devices, and the output signals thereof are aggregated into one signal by the device 4. In addition, in Kame 2 Garden, the output signals of the control devices 1 to S are interlocked and coordinated with the timing by the devices 5 to 1, and the signals are transmitted to the next stage control devices 1l-jF. Is contracted to -1t.

亀2図の制御装置の構成−を貝際の制御装置へ過応した
ガとしては、例えばtイリスタ変畿装置がある・その場
合には、l−1は、点弧角を決定する位相餉*装置であ
り、その位相−−直重の出力信1(変!I4器が6相ブ
リツジ構成ならば・個の点弧パルス)は、jlouto
f3fal踏5−FKよってインターロックを施され、
次段のゲート餉御執l1l−J#へ送られ、jI!にゲ
ー)mlliitJl〜10で樟々のインターロックが
施されて、2outof3回路11によつニ一つの信号
に集約されてサイリスタへゲート信号を送出する。
An example of a device that adapts the configuration of the control device shown in Figure 2 to a control device at the edge of the shell is a t-iristor variable device.In that case, l-1 is a phase shifter that determines the firing angle. *It is a device, and its phase-direct output signal 1 (if the I4 transformer has a 6-phase bridge configuration, ignition pulses) is jlouto
Interlocked by f3fal 5-FK,
Sent to the next stage of gate goshi l1l-J#, jI! 2 out of 3 circuit 11 aggregates the signals into one signal and sends out a gate signal to the thyristor.

〔背景技術の間魅点〕[Attractions of background technology]

さてこのような構成においては、例えば1181−1I
I121Nノ#IilJ〜l(1)lBBi2号、或イ
ハ第2−の装置8〜9の出力信号を冨時監視して。
Now, in such a configuration, for example, 1181-1I
I121N #IilJ~l (1) IBBi No. 2, or Iha No. 2-, monitors the output signals of devices 8 and 9 at peak times.

いづれかの信号が異常になった場合、その異常を的確に
、且つすみやかに!f’Uw#して、その異常系列の制
御鉄線な切離したり、或いは何らかの処置を施してシス
テム停止を防止する必費がある。そこで、近年多重化さ
れたit[における、各装置の異常を的確に、且つすみ
やかに判断する為の虻視装置゛が賛望されている。
If any signal becomes abnormal, identify the abnormality accurately and promptly! f'Uw#, it is necessary to disconnect the control wire of the abnormal series or take some other measures to prevent the system from stopping. Therefore, in recent years, a monitoring device for accurately and quickly determining abnormalities in each device in multiplexed IT systems has been highly desired.

〔発明の目的〕[Purpose of the invention]

従って、本発明の目的は、この上うな賛望を満たすべく
なされたものであって、多1化された輪重の出力信号の
異常9″′有無をすみやかに検出して拡大事故を防止し
たり、保守時間を短縮する為の中膜として便用する覧仇
装置を提供す〔発明の夷m例〕 菖S−は一本発明の一実施例を示す甑伐装置である・菖
3幽において、オア素子12−14ノ各々の一方の入方
信号(以F、パルスUム、パルスU1%パルスυCと略
記する・)は1例えば1162−における処置J〜1の
一つの出力信号である・16〜11はアンド素子、11
1はオア素子、11はモノマルチであるejll知のご
とく、アンド素子IJ〜17及びオア素子18によって
*2outof31i1路が構成されて獣り、史に又、
後述する皺伐装置が異常を検出すると、その出力信号に
より等価的に1loutof3回路がオア細路の機能を
もった一路となる。
Therefore, it is an object of the present invention to promptly detect the presence or absence of an abnormality in the output signal of a multi-wheel load to prevent an escalating accident. [Example of the Invention] Iris S- is a clearing device that is an embodiment of the present invention. In , one input signal of each of the OR elements 12-14 (hereinafter abbreviated as F, pulse Um, pulse U1% pulse υC) is one output signal of treatment J to 1 in 1162-, for example.・16 to 11 are AND elements, 11
1 is an OR element, and 11 is a monomultiple.As is well known, the AND element IJ~17 and the OR element 18 form a *2 out of 31 i 1 path, and in history,
When the crinkling device, which will be described later, detects an abnormality, its output signal equivalently turns the 1lout of 3 circuit into a single path with the function of an or-narrow path.

J#−xxは、不−歇検aii8HIe、Ahスが不−
款の場合には、パルス@l”を出方する。
J#-xx has no intermittent inspection aii8HIe, Ah
In the case of a clause, a pulse @l" is issued.

17−77は1ンド嵩子、J2〜J4はオア嵩・: 子、71〜40は″、、タイマーで、入方僅号か所定時
間以上パルス”l″の場合にパkX”l″vas力する
。41〜4Jは反転素子%44〜4#はフリップフロッ
プである。
17-77 is 1nd volume, J2 to J4 is or volume, 71 to 40 is ``,, with a timer, if the input signal is small or the pulse is ``l'' for a predetermined time or more, the pass kX ``l'' vas 41-4J are inverting elements 44-4# are flip-flops.

次に作用について述べる。Next, we will discuss the effect.

さて、このような構成において、今パルスUム、Us、
Llcがすべて正常で、パルスlの状態を考える。この
とき不一致検出蘭@go〜12の各々の出力信号はパル
ス0である。又、タイマー36〜37の設定時間は正常
時におけるパルスITR11の期間よりも大きく設にし
ているのでやはりパルス0を出力している。従って、ア
ンド素子26〜28の出力はすべてパルス0である・又
、タイマー38〜40の入刃傷号は、反に素子41〜4
3によってパルス0となるのでタイマー38〜40の出
力信号、促ってアンド素子29〜31の出力信号はパル
ス0となる、それ故、オア素子32−34の出力信号は
パルスOで、フリップフロップ41〜−9はすべてセッ
トされずその出力信号はすべてパルス0で正常と判定す
る・パルスロム、Us、Ucがすべて正常で、パルス”
0”の秋塾を4える。このとき、やはり不−叙検出關路
10〜j2の各々の出力信号はパルス″0′″であるの
で、アンド素子J6〜18の出力信号もパルス0である
。又、タイマー38−40(1)設定時間は、パルス0
状態の期間よりも大きく設定しているので、その出力信
号はすべてパルス0で、従ってアンド素子29〜31の
出力信号もパルス“0となる。それ故、フリップフロッ
プ41〜4gの出力信号はすべてパルス0で正常と判定
する・ さて、側らかの異常が尭生して、パルスロムがパルス1
状態のままになったとすれは、パルスロムのみがパルス
l状態で、パルスLJI。
Now, in such a configuration, now the pulse Um, Us,
Consider a situation where Llc is all normal and pulse l is present. At this time, each output signal of the mismatch detection circuit @go~12 is pulse 0. Further, since the set time of the timers 36 to 37 is set longer than the period of the pulse ITR11 during normal operation, the pulse 0 is still outputted. Therefore, the outputs of the AND elements 26 to 28 are all pulse 0. Also, the input signal of the timers 38 to 40 is, on the contrary, the output of the elements 41 to 4.
3 makes the pulse 0, so the output signals of the timers 38 to 40, and the output signals of the AND elements 29 to 31 become pulse 0. Therefore, the output signals of the OR elements 32 to 34 are pulse O, and the output signals of the flip-flops 41 to -9 are all not set, and all output signals are determined to be normal with pulse 0. Pulse ROM, Us, and Uc are all normal, and pulse is 0.
0'' is incremented by 4. At this time, the output signals of each of the non-descriptive detection links 10 to j2 are pulses of 0'', so the output signals of AND elements J6 to 18 are also pulses of 0. .Also, the timer 38-40(1) setting time is pulse 0.
Since it is set to be larger than the period of the state, all of its output signals are pulses 0, and therefore the output signals of AND elements 29 to 31 are also pulses of 0.Therefore, all output signals of flip-flops 41 to 4g are pulses of 0. It is determined that the pulse is normal when the pulse is 0. Now, the abnormality on the side has increased and the pulse ROM is determined to be a pulse of 1.
If the state remains, only the pulse ROM is in the pulse L state, and the pulse LJI.

そこで、次にこのような場合を考える。さ工、パルスロ
ムはパルス@1″で、パルスUs、Llcハバー諧 ルスOであるから、不−款検出−路7G。
Next, let us consider such a case. Now, the pulse ROM is pulse @1'', and the pulse Us and Llc hubber scale O, so the fault detection path 7G.

ド嵩子2jの出力信号がパルス1となる。又。The output signal of the pad 2j becomes pulse 1. or.

タイマーsg#)aS力信号は所足時間依パルスlとな
り、従って、アンド素子28、オア素子14の出力信号
はパルスlとなφ・それ故、フリップフロップ4#がセ
ットされて、その出力@1号はパルス@l”となる。即
ちパルスロムが^當と判断する。
The timer sg#) aS force signal becomes the required time-dependent pulse l, and therefore the output signals of the AND element 28 and the OR element 14 become the pulse l. Therefore, the flip-flop 4# is set and its output @ No. 1 becomes a pulse @l''. That is, the pulse ROM determines that this is the case.

久に、4−1らかの異常が発生して、パルスロムがパル
ス”0”駄急のままになったとすれば、パルス:jムが
パルスll0II状恣で、パルスUil、[JCカパル
ス′″1”状態である期間が必す生じる。そこで、この
ような場合を考える。
If some abnormality in 4-1 occurs for a long time and the pulse ROM remains at the pulse "0", the pulse: j is arbitrary like the pulse 110II, and the pulse Uil, [JC couple''' A period of 1” state will inevitably occur. Therefore, consider a case like this.

パルスU藤、UCは正常であるから、モノマルチ1#の
出力信号は正常でパルスlとなる・恢ってフリップフロ
ップ44〜46はセクトされる・このとき、パルスUB
、Llcは正常であるので、フリップフロップ45.4
1はすぐにリセットされるが、パルスロムはパルス0状
態の1 ままであるので、フリップフロップ44はリセットされ
ず、その出力信号はパルス“l”状態のままとなる。パ
ルスロムはパルス@OII状態のままであるので、タイ
マー38の出力信号は轡定時間後パルス1となり、疵っ
てアンド素子z9.オア嵩子S2の出力m号はパルス1
となって、フリップフロップ49がセットされてパルス
ロムが異常と判断する・ 以上説明した動作説明をタイムチャートで示したものが
#14園、JllI5−であり、第4−はパルスロムが
パルス1allK故障した場合であり、馬s#Aはパル
スロムがパルス0状謙に故障した場合である。又、II
際の装置では、必ず制御−差や一路嵩子のIIIIa−
差が存在するので、パルスロム、Us、Ucが全く同一
の信号になるとは限らない・本発與はそのような場合に
も全く問題なく適用できるものである@従って、上記タ
イムチャートでは、パルスロム、us、Llcがg差を
有している場合について紀@している。
Since pulses U and UC are normal, the output signal of monomulti 1# is normal and becomes pulse L.Flip-flops 44 to 46 are then sectored.At this time, pulse UB
, Llc is normal, so the flip-flop is 45.4
The 1 is immediately reset, but since the pulse ROM remains at the 1 in the pulse 0 state, the flip-flop 44 is not reset and its output signal remains in the pulse "1" state. Since the pulse ROM remains in the pulse @OII state, the output signal of the timer 38 becomes pulse 1 after a predetermined time, and the AND element z9. The output m of Orakako S2 is pulse 1
, the flip-flop 49 is set and the pulse ROM is judged to be abnormal. The above operation explanation is shown in the time chart for #14, JllI5-, and in the 4th-, the pulse ROM has failed in the pulse 1allK. In this case, s#A is a case where the pulse ROM fails in the pulse 0 state. Also, II
In actual equipment, control-difference and Ichiro's IIIa-
Since there are differences, the pulse ROM, Us, and Uc may not necessarily be exactly the same signal. This proposal can be applied to such cases without any problems. Therefore, in the above time chart, the pulse ROM, Us, and Uc The case where us and Llc have a g difference is described.

本弛−の他のIIJll、例についてa−する。Other IIJll examples of this course are discussed below.

前述のa−ではンAいUムがパい“1“―。In the a-a-mentioned above, the A-um is ``1''.

パルスO肯のいづれのIIKも故障■ることを想定した
場合であるが、装置の構成によっては、パルス111に
&障する場合、或いはパルスO″−に故障する場合が確
率的に無視できる程小さい場合がある。そのような場合
には、嫉視装置としては、パルス1IIllの故障又は
パルス”O″貴の故障のみを検出する装置としてもよし
・。
This is a case assuming that any IIK with a positive pulse O fails, but depending on the configuration of the device, the probability of a failure on pulse 111 & or a failure on pulse O''- is negligible. In such cases, the monitoring device may be a device that detects only the failure of pulse 1IIll or the failure of pulse "O".

又、甑碗装置としてマイクロコンピュータを使用してソ
フト錫塩で行なえることも明らかである。
It is also clear that the process can be carried out using a soft tin salt using a microcomputer as the hotpot device.

〔尭−の効果〕〔Effect of 孭〕

以上歇−したごとく、本発明によれば、多重化された装
置の出力信号の不一致を検出する機能と1紀出力信号が
所定時間状態変化を起さない状態を検出する機能、更に
果豹出力4N号によってセットされ、薊紀各々の装置の
・出力信号によってリセットされる記憶機能と前記出力
信号が所定時間変化を起さない状態を検出する機能とを
組み合せることKより、前記多重化された装置が、パル
ス@1″貴に故障した場合にもパルス10”貴に故障し
た場合にもJIj富を検出することができ、且つ、いづ
れのkIILが故障した場合にも的確に411111I
Tすることができ、ひいては多重化の麹米を象大脈に生
かしてシステム停止や拡大事故を未然に防止することが
できると云う着しい麹米を1する。
As described above, according to the present invention, there is a function of detecting a mismatch between output signals of multiplexed devices, a function of detecting a state in which the state of the first output signal does not change for a predetermined time, By combining the memory function set by No. 4N and reset by the output signal of each Akinori device and the function of detecting a state in which the output signal does not change for a predetermined period of time, the multiplexed It is possible to detect JIJ wealth both when the device fails at pulse @1'' and when it fails at pulse 10''.
This is a unique type of koji rice that can be used to prevent system outages and widespread accidents by making full use of multiplexed koji rice.

【図面の簡単な説明】[Brief explanation of drawings]

籐11m、亀2−は、多゛宜化された装置の構成−,1
113図は、本発明の一実1a例を不Tl1ai路図、
第4N、1lS−は、第3−のタイムチャートである・ J−11・・・装置、12〜14・・・オア素子。 15〜1r・・・アンド素子、18・・・オア素子、1
#・・・モノマルチ、34)〜12・・・不−紋検ai
―絡、21〜11・・・アンド素子、32〜J4・・・
オア素子、1s〜40・・・タイマー、41〜4J・・
・反転素子、44〜41・・・フリップフロックO出願
人代場人升量士鈴江武彦 第1wJ 第2図 第3図 第4図 第5図 C&−一−−−−−−−−−−−−−−−−−−−−−
−−−−−−−一一−−一−−5
Rattan 11m, Tortoise 2- is a configuration of a diversified device-, 1
Figure 113 shows an example 1a of the present invention as a non-Tl1ai path diagram,
4th N, 11S- is a time chart of 3rd- J-11...device, 12-14...OR element. 15-1r...AND element, 18...OR element, 1
#...Mono multi, 34) ~ 12...Fu-print inspection ai
- Connection, 21-11...AND element, 32-J4...
OR element, 1s~40... timer, 41~4J...
・Inversion elements, 44 to 41...Flip-flock O applicant representative person quantifier Takehiko Suzue 1st wJ Figure 2 Figure 3 Figure 4 Figure 5 C&-1---------------------- −−−−−−−−−−−
-----------11--1--5

Claims (1)

【特許請求の範囲】[Claims] 同−のII!舵を有する複数のパルス信号を入力信号と
し、その入力m号を一つの出力傷gに集約するfIkl
lmにおいて、前記w数の入力信号の2信号の不−1:
を検出して%mid入力伯号の内、いづれの入力信号が
異常であるかを杓期する累1F)1iIA能を令すると
ともに、更に前記入力信号の谷々について、それらの入
力信号が所定時間内に状I[を化を起さないJ11曾に
異常と判断する亀20機粍を有するとともに、lshの
機乾によって、#4常と′44J断された入力信号と、
論2の機能によってRNと411111rされた入力信
号か1款した場合にのみ当咳入男信号か異常と判断する
凧3のIIIA舵を壱することを特徴とする監視装置。
Same II! fIkl that takes multiple pulse signals with a rudder as input signals and aggregates the input m into one output flaw g
In lm, the difference between the two input signals of the w number is -1:
It detects which input signal is abnormal among the %mid input signals and determines which input signal is abnormal. In addition to having 20 mechanisms to judge that J11 is abnormal because the condition I [ does not occur within the time period, the input signal is disconnected from #4 and '44J due to the drying of lsh,
A monitoring device characterized in that the IIIA rudder of the kite 3 determines that the input signal is abnormal only when the input signal is RN and 411111r by the function of theory 2.
JP57017318A 1982-02-05 1982-02-05 Monitor device Pending JPS58134304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57017318A JPS58134304A (en) 1982-02-05 1982-02-05 Monitor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57017318A JPS58134304A (en) 1982-02-05 1982-02-05 Monitor device

Publications (1)

Publication Number Publication Date
JPS58134304A true JPS58134304A (en) 1983-08-10

Family

ID=11940666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57017318A Pending JPS58134304A (en) 1982-02-05 1982-02-05 Monitor device

Country Status (1)

Country Link
JP (1) JPS58134304A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6223397A (en) * 1985-07-19 1987-01-31 Fuji Electric Co Ltd Generator exciting system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5155643A (en) * 1974-11-11 1976-05-15 Omron Tateisi Electronics Co DENSHIKEI SANKISEIGYO HOSHIKI
JPS54112150A (en) * 1978-02-23 1979-09-01 Sanyo Electric Co Ltd Pulse interrupt detection circuit
JPS56110102A (en) * 1980-01-21 1981-09-01 Siemens Ag Method of and apparatus for selecting digital frequency

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5155643A (en) * 1974-11-11 1976-05-15 Omron Tateisi Electronics Co DENSHIKEI SANKISEIGYO HOSHIKI
JPS54112150A (en) * 1978-02-23 1979-09-01 Sanyo Electric Co Ltd Pulse interrupt detection circuit
JPS56110102A (en) * 1980-01-21 1981-09-01 Siemens Ag Method of and apparatus for selecting digital frequency

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6223397A (en) * 1985-07-19 1987-01-31 Fuji Electric Co Ltd Generator exciting system

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