JPS58132977A - Preparation of schotkky gate type gaas field effect transistor - Google Patents
Preparation of schotkky gate type gaas field effect transistorInfo
- Publication number
- JPS58132977A JPS58132977A JP1507382A JP1507382A JPS58132977A JP S58132977 A JPS58132977 A JP S58132977A JP 1507382 A JP1507382 A JP 1507382A JP 1507382 A JP1507382 A JP 1507382A JP S58132977 A JPS58132977 A JP S58132977A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- heat
- electrode
- mask
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000013078 crystal Substances 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 238000003746 solid phase reaction Methods 0.000 abstract description 2
- TVTJUIAKQFIXCE-HUKYDQBMSA-N 2-amino-9-[(2R,3S,4S,5R)-4-fluoro-3-hydroxy-5-(hydroxymethyl)oxolan-2-yl]-7-prop-2-ynyl-1H-purine-6,8-dione Chemical compound NC=1NC(C=2N(C(N(C=2N=1)[C@@H]1O[C@@H]([C@H]([C@H]1O)F)CO)=O)CC#C)=O TVTJUIAKQFIXCE-HUKYDQBMSA-N 0.000 abstract 1
- 229940125851 compound 27 Drugs 0.000 abstract 1
- 239000007769 metal material Substances 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 230000004913 activation Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- WWTBZEKOSBFBEM-SPWPXUSOSA-N (2s)-2-[[2-benzyl-3-[hydroxy-[(1r)-2-phenyl-1-(phenylmethoxycarbonylamino)ethyl]phosphoryl]propanoyl]amino]-3-(1h-indol-3-yl)propanoic acid Chemical compound N([C@@H](CC=1C2=CC=CC=C2NC=1)C(=O)O)C(=O)C(CP(O)(=O)[C@H](CC=1C=CC=CC=1)NC(=O)OCC=1C=CC=CC=1)CC1=CC=CC=C1 WWTBZEKOSBFBEM-SPWPXUSOSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 244000245420 ail Species 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229940126208 compound 22 Drugs 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 235000004611 garlic Nutrition 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はＧａＡｍを用いたショットキーゲート型電界効
米トランジスタ（以下ＭｌｉｉＳＦｇＴ ）の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a Schottky gate field effect transistor (hereinafter referred to as MliiSFgT) using GaAm.
ＧａＡｓＭＥ８ＦＥＴは高周波場ｍ器や発Ｊｉｉ器など
を構成する個別半纏体素子として広く使われている。ま
た、最近ではＧａＡｓ Ｉ Ｃの基本素子としても重要
な役割を来しつつある。このいずれの応用でもＧａＡｓ
ＦＥＴの性能を十分引き出すことが要求される。、Ｇ
ａＡａ ＰＥＴの制周波性能指数は良く知られているよ
うにＣｇｓ／ｇｍで記述される。ここでＣｇ、はゲート
・ソース間ｇ１でありｓ ｇｍはＦＥＴの相互コンダク
タンスである。GaAsME8FETs are widely used as individual semi-integrated elements constituting high frequency field devices, generators, etc. Moreover, recently, it is playing an important role as a basic element of GaAs IC. In both of these applications, GaAs
It is required to fully bring out the performance of the FET. ,G
As is well known, the frequency control figure of merit of aAa PET is expressed in Cgs/gm. Here, Cg is the gate-source distance g1, and sgm is the mutual conductance of the FET.
Ｃｇｓを減らしｂｇｒｎを大きくしてやることにより高
周波性能指数は改善される。The high frequency figure of merit is improved by reducing Cgs and increasing bgrn.
ｇｒｒｌに着目すると、ＦＥＴの実質的なｇｍはｇｍ。Focusing on grrl, the actual gm of the FET is gm.
ｇｍ＝ １＋蒜ｍ。Ｒ８−
となることが知られている。ｇｌｌｌｏはＦＥＴのチャ
ネル部の特性から決まる貞性相征コンダクタンスである
。これが引き出しうる竣大のｇｍであるが現実にはソー
ス・ｒ−）閾の直列抵抗Ｒｓがあり、上式のように実質
的なｇｍはｇｍｏより小さなものとなってしまう。従っ
て、このＲｓをいかにして小さくするかが大きい相互コ
ンダクタンスを得てＰＥＴの高鳴波特性を改＃するため
の鍵である。gm=1+garlic m. It is known that R8-. glllo is the chastity phase conductance determined by the characteristics of the channel portion of the FET. This is the final gm that can be extracted, but in reality there is a series resistance Rs of the source/r-) threshold, and as shown in the above equation, the actual gm is smaller than gmo. Therefore, how to reduce this Rs is the key to obtaining a large mutual conductance and improving the high frequency characteristics of PET.
ＭＢ２ ＦＥＴの直列抵抗Ｒ＠の低減化をはかる方？去
としてセルファライン（自己１ｂ）法が知られている。How to reduce the series resistance R@ of MB2 FET? The self-line (self-1b) method is known as an alternative method.
これにはいくっがの方法があるが。There are several ways to do this.
代表的なのは＃ＩＩ１図に示すようにｆ −トＸ極１３
をマスクとして茜嬢イイオン注入をし、篭子濃Ｂ−１
イか１０１ 以上のソース、ドレイン頭載１４゜１５を
ｆ−）電慟１３に近接させて形成Ｔる方法である、１１
は半絶縁性ＧａＡｓ結晶、１２はｒ古性噛、１６．１７
はそれぞれソース、ドレイン電極である。この方法で最
も雌しい技術は耐熱性ｒ−）電極金−の選択である。ｒ
−）電極なマスクとして高讃度イオン注入したソース。A typical example is f-to-X pole 13 as shown in Figure #II1.
This is a method of implanting Akane's ions using the mask as a mask, and forming the source and drain heads of 14°15 and 101 above f-) in close proximity to the electrode 13.
is a semi-insulating GaAs crystal, 12 is an ancient crystal, 16.17
are source and drain electrodes, respectively. The most suitable technique for this method is the selection of heat-resistant r-) electrodes. r
-) Highly ion-implanted source as an electrode mask.
ドレイン部を高電子１（−とするにはアニーリング工程
が必要であるが、通常ＧａＡｓへのドナーイオン注入層
のアニール温度は約８００ ｔにもなる。こうした高温
アニール工程を経たあともマスクとして使ったｒ−）電
極とＧ鳳入Ｓとが良好なショットキー障壁を有している
ことが２安である。こうした厳しい条件下でＧａＡｓと
良好なショットキー障壁を形成しうる金属は数少い。主
にＷ、Ｍｏ、Ｔａ、Ｔｒどの耐熱性金−その他Ｔ ｉ
／ Ｗなどの耐熱性金貞合金がその可能性を有している
。実際にＴｉ／ＷダートのセルファラインＧａＡｓ Ｍ
ＢＳ ＦＥＴの実験例が報道されている（例えば、Ｎ、
’ ＹＯＫＯＹＡＭＡ ｅｔａｌ、 １９８１１Ｓ８Ｃ
Ｃ）。しがし、こうした耐熱性ひ−は一般にＧａＡｓと
の機械的密晋性が悪く、再現性よく良好な接合を得るこ
とは嬉しい。An annealing process is required to make the drain region high electron 1 (-), but the annealing temperature for the donor ion implantation layer in GaAs is usually about 800 t. Even after such a high-temperature annealing process, it can still be used as a mask. It is important that the electrode and the G-type S have a good Schottky barrier. There are only a few metals that can form a good Schottky barrier with GaAs under such severe conditions. Mainly heat-resistant gold such as W, Mo, Ta, Tr - other Ti
Heat-resistant metal alloys such as /W have this possibility. Actually, Ti/W dirt self-line GaAs M
Experimental examples of BS FET have been reported (for example, N,
'YOKOYAMA etal, 19811S8C
C). However, such heat-resistant steel generally has poor mechanical adhesion to GaAs, so it is pleasing to be able to obtain good bonding with good reproducibility.
本発明はこうした従来の耐熱性金属に絣り、Ｐ（をｒ−
）電極金属として用い、これとＧａＡａとの固相反応を
利用して、耐熱性Ｖ−１！ットキー接合を再現性よく形
成し、それによりセルファライン型ＧａＡｓ ＭＥ８Ｆ
ＦｉＴを安定に作ることを可能にするものである。The present invention applies P(r-
) Used as an electrode metal and utilizing the solid phase reaction between this and GaAa, heat resistance V-1! The self-aligned GaAs ME8F
This makes it possible to stably produce FiT.
ＰｔとＧａＡｍとは容易１；反応し、ＰｔＡｓ！。 Pt and GaAm easily react 1; PtAs! .
ＰｔＧａ、などの金嬌間（ヒ合物が形成される。そして
、それら化合物の組成に依存してショットキー障壁の電
気的特性も変化する。第２図（ａｌ Ｉ （ｂ）はＧａ
Ａｓ ニＰｉを５００ Ａ ＩＬｔＩ！琢４し、温度を
変えて熱処理したときのショットキー障壁のＤ４１！！
篩さくφＢ）と障壁の良し厩しを示す餉（ｎｌを示した
ものである。５図中、破線は５ｉｎｈａらが１９７３年
に発表したデータであり、実線が今回本発明者らが測定
したデータである。・この図から見られるよう（＝約５
００℃以下ではＰｔとＧａＡｓとの間【二反応が生じて
も一気的特性は大きく変らないが、６００′Ｃ以Ｅとな
ると障壁特性が劣化−「る。従って、このままではＰｔ
をｙ−トとして用いるとソース、ト°レインｎ＋注入層
ノアニール（〜８００℃）の際にショットキー障壁が劣
化してしまうためセルファラインＭＥ８ＦＥＴはつくれ
ない。PtGa, etc. are formed.The electrical characteristics of the Schottky barrier also change depending on the composition of these compounds.
As Ni Pi 500 A ILtI! Schottky barrier D41 when finished and heat treated at different temperatures! !
The graph shows the sieve size φB) and the thickness of the barrier (nl). In Figure 5, the broken line is the data published by Inha et al. in 1973, and the solid line is the data measured by the inventors this time. This is the data.・As seen from this figure (= about 5
Below 00°C, even if two reactions occur between Pt and GaAs, the instantaneous properties do not change significantly, but at temperatures above 600°C, the barrier properties deteriorate.
If this is used as a y-t, a self-line ME8FET cannot be made because the Schottky barrier deteriorates during the source and train n+ injection layer no-annealing (up to 800° C.).
ところが、本発明者らの実験によれば、 ＰｔとＧａＡ
ａとを比較的低温（４００℃明後）で−間熱処理をする
と、その後８００℃まで昇温してもその電気的特性が変
らないということが明らかとなった。第３図および８４
図は実験結果の一例を示すものである。ｎ型ＧａＡｓ結
晶にＰｔを５０ＯＡ蒸着し、熱処理を行った。１つは第
３図の破＠にのような温度プログラム、丁なわち室温か
ら一気に８００℃まで昇温して１０分間保持するという
もの、もう１つは実線Ｂのように４００℃に昇温し、そ
こで６０分間保持したあと、８００℃に昇温して１０分
間保持するというものである。これらの試料の裏面にＡ
ｕＧｅのオーミック電極を形成してショットキーダイオ
ードとして電気的特性を調べた結果、第３図のＡ、Ｂに
それぞれ対応して粥４図のＡ、Ｂのようなものであった
、ｍＫｆロダラムＡの場合のショットキー特性は余りよ
くない。一方、Ｂの場合は良好なショットキー特性を示
した。However, according to the inventors' experiments, Pt and GaA
It has become clear that when a is heat-treated at a relatively low temperature (400°C after dawn), its electrical characteristics do not change even if the temperature is subsequently raised to 800°C. Figures 3 and 84
The figure shows an example of experimental results. 50OA of Pt was deposited on the n-type GaAs crystal and heat treated. One is the temperature program as shown in Figure 3, which is to raise the temperature from room temperature to 800°C all at once and hold it for 10 minutes, and the other is to raise the temperature to 400°C as shown in solid line B. After holding there for 60 minutes, the temperature was raised to 800°C and held for 10 minutes. A on the back side of these samples
As a result of forming an ohmic electrode of uGe and examining its electrical characteristics as a Schottky diode, it was found that mKf Rodalum A was similar to A and B in Figure 4, corresponding to A and B in Figure 3, respectively. The Schottky characteristics are not very good in the case of . On the other hand, in the case of B, good Schottky characteristics were exhibited.
本発明は以ｔの物理現映を利用したものである。すなわ
ち、ＰｔをＦＨＴのダート金輌とし。The present invention utilizes the following physical phenomena. In other words, Pt is FHT's dart gold tank.
被４ｆｌｋｌ＝それをマスクとしてセルファラインでソ
ース、Ｐレイン用のｎ イオン注入を行った後、まず４
００℃前後で熱処理してＰｉとＧａＡｍの化合物を形成
し、次いで８００℃自１優に昇温して熱処理をしてれ
注入１ｍの不純物の活性化をするというものである。第
１段階のＰｔとＧａＡｓの化合物を形成する熱処理は、
好ましくは４００〜５００℃、１０〜６０分である。ま
た活性化のための熱処理の好ましい温度範囲は７５０〜
８５０℃である。4flkl = After performing n ion implantation for the source and P-rain using self-line as a mask, first 4flkl is used as a mask.
Heat-treat at around 00℃ to form a compound of Pi and GaAm, then heat-treat by raising the temperature to well above 800℃.
This involves activating impurities implanted for 1 meter. The first stage of heat treatment to form a compound of Pt and GaAs is
Preferably it is 400-500 degreeC and 10-60 minutes. The preferred temperature range for heat treatment for activation is 750~
The temperature is 850°C.
本発明は従来４１１ＧされているＴｉ／Ｗなどを用いた
セルファライン型ＧａＡｓＭＥＳＦＥＴの製造方法に比
ベシヨットキーダート金−とＧａＡｍの密着性に優れ、
また電気的特性（１４壁の高さなど）の再現性、安定性
などの点で優れており、Ｇａ１ｎ ＩＧやＬＳＩの有効
な製造方法となりつる、。The present invention has excellent adhesion between gold and GaAm compared to the conventional manufacturing method of self-line type GaAs MESFET using Ti/W etc.
Furthermore, it is excellent in terms of reproducibility and stability of electrical characteristics (14 wall height, etc.), making it an effective manufacturing method for Ga1n IGs and LSIs.
以下で具体的実施例にもとずいてセルファライン型Ｇａ
Ａｓ ＭＢＳＦＥＴの製造方法について述べる。第５図
は製造工程の一例である。半絶縁性Ｇａｐｓ結晶基板２
１にＳｉ イオＹをマスク２２１ｔ −！
を用いて１００ＫＶで４Ｘ１０ （ＪＫ 注入し、８
５０℃で１５分間アニールすること（二より活性１−２
３を選択的（＝形成する（ａ）。つづいてデート金属と
してのＰｔを５０ＯＡ蒸着してダート電極２４を形成し
くｂ）、これをマスクとして再びＳｉ イオンを１５
０ ＫＶで３Ｘ１０ ｍ 注入してｆ−）電極２４に
セルファラインされたイオン注入層２５．２６を形成す
る（Ｃ）。この試料を４００℃で６０分間熱処理すると
ｐｔｙ−トａ極２４とＧ ａ Ａ ｓとが反応して化合
物２２が形成される（ｄ）。この６０分の熱処理では蒸
着したＰｔは□ばゾ丁べて反応する。このあと８００ｔ
ｌ：昇温して１５分間熱処理して高−反イオン注入層ｒ
ｉ 、 ｚ ｓの不純物活性化を行い、ソース領域２５
１１ ドレイン領域２６’を形成し、その後ＡｕＧｅ
かうなるソース、ドレイン電極ｊ ８ 、２９を形成す
るｔｅｌ。Below, based on specific examples, Selfaline type Ga
A method for manufacturing As MBSFET will be described. FIG. 5 shows an example of the manufacturing process. Semi-insulating Gaps crystal substrate 2
1 with Si io Y mask 221t -! 4X10 (JK injection, 8
Anneal at 50°C for 15 minutes (more active than 1-2).
3 is selectively formed (=forming (a). Next, 50 OA of Pt as a date metal is evaporated to form the dirt electrode 24 (b), and using this as a mask, Si ions are again deposited at 15 OA.
Implant 3×10 m at 0 KV to form f-) ion implantation layers 25 and 26 self-aligned to the electrode 24 (C). When this sample is heat-treated at 400° C. for 60 minutes, the pty-a electrode 24 and GaAs react to form a compound 22 (d). During this 60 minute heat treatment, the deposited Pt reacts across the squares. 800t after this
l: Heat treated for 15 minutes at elevated temperature to form a high-anti-ion implantation layer r
Impurity activation of i, zs is performed, and the source region 25
11 Form the drain region 26', then AuGe
tel forming such source and drain electrodes j 8 and 29.
こうして、直列抵抗の小さなセルファライン型０１ム農
ＭＥ Ｓ Ｆ ＥＴがつくれる。このＭＢ２ ＦＥＴは
従来のようなソース、ドレイン部１ニセルファラインで
ｎ＋層がつくられていないＦＩＴ ｉ＝比べ相がコンダ
クタンスが約２倍以上であり、妬速スイッチングが可能
であった。またショットキーｌ”−）電橋の密着性がよ
く、再現性、安定性に′−優れた特性が得られた。In this way, a self-aligned MESFET with low series resistance can be created. This MB2 FET had a conductance more than twice as high as that of the conventional FIT (FIT i) in which no n+ layer was formed in the source and drain portions with one self-aligned line, and was capable of high-speed switching. In addition, the adhesion of the Schottky bridge was good, and excellent reproducibility and stability were obtained.
＠１図はｒ−ト金−をマスクとしてソース。
ドレイン部にｆｊ１３１１１ｆ不純物層を形成するセル
ファライン型ＭＥ ８ Ｆ ＥＴの基本構造を示す図、
粥２図ｆ１） 、 （ｂｌはＰｔとＧａＡｓのショット
キー障壁特性の熱処理諷ず依存性を示す図、第３図およ
び嘱４図は熱処理温度プログラムとその違いによるＰｔ
−ＧｍＡｓ ；ｙ ：１ツトキー障壁の′を流−電圧
特性あ１いを示す図、＠Ｓ図（ａ）〜（ｅ）は、本発明
の一実施例のＧａＡａ ＭＢＳＦＥＴの製造工程を示す
図である。
２１・・・半絶縁性ＧａＡｓ結晶基板、２３・・・活性
層、２４・・・ｒ−ト電極（Ｐｔ）、 ２ｓ 、 ｘｉ
−＠濃闇イオン注入１−１２１・・・化合物、２５′・
・・ソース領域、２６１・・・ドレイン領域、２８・・
・ソース電極、２９・・・ドレイン電極。
出願人代理人 弁理士 鈴 江 武 彌第 １図
１１Ｗ２ｖ？Ｊ
（ａ） （ｂ）慣４閲@Figure 1 shows the source using gold as a mask. A diagram showing the basic structure of a self-line type ME 8 FET in which an fj13111f impurity layer is formed in the drain part,
Figure 2 f1), (bl is a diagram showing the direct dependence of the Schottky barrier properties of Pt and GaAs on heat treatment, Figures 3 and 4 are the heat treatment temperature programs and their differences in Pt
-GmAs ; y : 1 A diagram showing the current-voltage characteristics of the key barrier, @S diagrams (a) to (e) are diagrams showing the manufacturing process of a GaAa MBSFET according to an embodiment of the present invention. be. 21... Semi-insulating GaAs crystal substrate, 23... Active layer, 24... r-to electrode (Pt), 2s, xi
-@Dark ion implantation 1-121... Compound, 25'.
...Source region, 261...Drain region, 28...
- Source electrode, 29... drain electrode. Applicant's agent Patent attorney Takeshi Suzue Figure 1 11W2v? J (a) (b) Practice 4 review
Claims (1)
形成し、このｒ−）電極をマスクとしてソース。 ドレイン部にドナー不純物を高濃度にイオン注入した後
、比較的低温で熱処理してｐｔとＧａＡｍの化合物を形
成し、続いて昇温熱処理来トランジスタの製造方法。 ＋２） ＰｔとＧａＡｓの化合物を形成Ｔる熱処理は
４００〜５００℃で１０〜６０分行ない、不純物を活性
化させる熱処理は７５０〜８５０ノスタの製造方法。[Claims] il) GaAs substrate (forming a dart electrode made of two Pt, and using this r-) electrode as a mask for source. A method for manufacturing a transistor in which a donor impurity is ion-implanted into the drain region at a high concentration, and then heat-treated at a relatively low temperature to form a compound of pt and GaAm, followed by temperature-rising heat treatment. +2) The heat treatment to form a compound of Pt and GaAs is performed at 400 to 500°C for 10 to 60 minutes, and the heat treatment to activate impurities is a manufacturing method of 750 to 850 degrees.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1507382A JPS58132977A (en) | 1982-02-02 | 1982-02-02 | Preparation of schotkky gate type gaas field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1507382A JPS58132977A (en) | 1982-02-02 | 1982-02-02 | Preparation of schotkky gate type gaas field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58132977A true JPS58132977A (en) | 1983-08-08 |
| JPS6312391B2 JPS6312391B2 (en) | 1988-03-18 |
Family
ID=11878674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1507382A Granted JPS58132977A (en) | 1982-02-02 | 1982-02-02 | Preparation of schotkky gate type gaas field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58132977A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5012985A (en) * | 1973-06-01 | 1975-02-10 | ||
| JPS53125777A (en) * | 1977-04-08 | 1978-11-02 | Nec Corp | Manufacture for field effect transistor |
| JPS56133872A (en) * | 1980-03-21 | 1981-10-20 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor device |
-
1982
- 1982-02-02 JP JP1507382A patent/JPS58132977A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5012985A (en) * | 1973-06-01 | 1975-02-10 | ||
| JPS53125777A (en) * | 1977-04-08 | 1978-11-02 | Nec Corp | Manufacture for field effect transistor |
| JPS56133872A (en) * | 1980-03-21 | 1981-10-20 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6312391B2 (en) | 1988-03-18 |
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