JPS58131808A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS58131808A
JPS58131808A JP1354982A JP1354982A JPS58131808A JP S58131808 A JPS58131808 A JP S58131808A JP 1354982 A JP1354982 A JP 1354982A JP 1354982 A JP1354982 A JP 1354982A JP S58131808 A JPS58131808 A JP S58131808A
Authority
JP
Japan
Prior art keywords
substrate
plate
piezoelectric
piezoelectric resonator
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1354982A
Other languages
Japanese (ja)
Inventor
Yukisato Atomachi
後町 幸里
Yoshikatsu Kishi
岸 善勝
Takashi Hasegawa
孝 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toko Inc
Original Assignee
Toko Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toko Inc filed Critical Toko Inc
Priority to JP1354982A priority Critical patent/JPS58131808A/en
Publication of JPS58131808A publication Critical patent/JPS58131808A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/125Driving means, e.g. electrodes, coils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Abstract

PURPOSE:To fix a piezoelectric resonator on a board at a position other than the vicinity of electrodes, by surrounding the vicinity of the electrodes on front and rear sides of the piezoelectric resonator with an elastic member and soldering leads of the electrodes on one side to the winding pattern on the board. CONSTITUTION:Elastic members 18, 23 are coated on the front side 9 and the rear side 12 of the piezoelectric plate 8 by printing, for example, to a prescribed thickness. Cream solder is applied to metallic patterns 29, 30 of the board and metallic patterns 21, 22 of the rear side 12 of the piezoelectric plate. Further, the plate 8 is mounted on the board 36 and an upper plate 24 is on the rear side 12 of the plate 8 sequentially. The cream solder is melted through heating for soldering. Then, the lead terminal 20 and the wiring patter 31 are conected with a conductive paste 34.

Description

【発明の詳細な説明】 本発明はエネルギ閉じ込め型圧電共振子を用いたフィル
タが一体に形成されているハイブリッドで示すように集
積回路の基板1の表面に凹部2を設け、圧電板3の裏面
の電極4をその凹部2内に位置させると共に表面の電極
5をセラミックや合成樹脂のキャップ6で被った状態で
圧電板3を基板1に接着剤により固着し、全体をフェノ
ール樹脂等の外装材37で樹脂封止することにより圧電
共振子が集積回路に取付けられていた。そして表面と裏
面の電極近傍に凹部2、キャップ6により空隙が形成さ
れて圧電板3はエネルギ閉じ込め型の振動を行い得るよ
うにしである。なお7は基板10表面に設けられている
配線パターンである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a recess 2 on the surface of a substrate 1 of an integrated circuit, as shown in a hybrid in which a filter using an energy trap type piezoelectric resonator is integrally formed. The piezoelectric plate 3 is fixed to the substrate 1 with an adhesive, with the electrode 4 located in the recess 2 and the electrode 5 on the surface covered with a cap 6 made of ceramic or synthetic resin, and the whole is covered with an exterior material such as phenol resin. The piezoelectric resonator was attached to the integrated circuit by sealing with resin at 37. A gap is formed by the recess 2 and the cap 6 near the electrodes on the front and back surfaces, so that the piezoelectric plate 3 can perform energy-confined vibration. Note that 7 is a wiring pattern provided on the surface of the substrate 10.

ところがこのような従来の構造では四部2、圧電板6の
電極、キャップ6を精度良く位置合せする必要があり、
又基板1に凹部2を設けなければなら々いので製造工程
が複雑になる。
However, in such a conventional structure, it is necessary to precisely align the four parts 2, the electrodes of the piezoelectric plate 6, and the cap 6.
Furthermore, since the recess 2 must be provided in the substrate 1, the manufacturing process becomes complicated.

本発明の目的は電極近傍の空隙を形成するための位置合
せが容易で、しかも基板に凹部を設ける必要のないエネ
ルギ閉じ込め型圧電共撮子のハイブリッド集積回路への
取付は構造の提供にある本発明はエネルギ閉じ込め型圧
電共撮子が組み込まれたハイブリッド集積回路において
、圧電共振子の表裏両面の電極近傍を弾性材により囲み
、少くとも片面の電極のリード端子を基板上の配線パタ
ーンに半田付けすることにより圧電共振子を電極近傍以
外の位置で基板上に固着し、残りの面を電極近傍以外の
位置で基板とは別の上板に固着してなることを特徴とす
る。
An object of the present invention is to provide a structure for attaching an energy trapping type piezoelectric co-photograph to a hybrid integrated circuit, which is easy to align to form a gap near the electrode, and does not require the provision of a recess in the substrate. The invention relates to a hybrid integrated circuit incorporating an energy trapping type piezoelectric resonator, in which the vicinity of the electrodes on both the front and back sides of the piezoelectric resonator is surrounded by an elastic material, and the lead terminal of the electrode on at least one side is soldered to the wiring pattern on the substrate. By doing so, the piezoelectric resonator is fixed on the substrate at a position other than the vicinity of the electrode, and the remaining surface is fixed on an upper plate separate from the substrate at a position other than the vicinity of the electrode.

以下本発明の実施例を示す第2図、第3図を参照しなが
ら説明する。第2図は圧電共振子を取付けである部分の
ハイブリッド集積回路を分解した時の平面図であり、(
a)は上板、(b)、(○)は圧電共振子の夫々裏面と
表面、(勾は基板を示しており、第3図は圧電共振子を
取付けである部分のハイブリッド集積回路の断面図が理
解を容易にするために(3) やや誇張して示しである。
Embodiments of the present invention will be described below with reference to FIGS. 2 and 3, which show embodiments of the present invention. Figure 2 is an exploded plan view of the hybrid integrated circuit where the piezoelectric resonator is attached.
a) is the upper plate, (b) and (○) are the back and front surfaces of the piezoelectric resonator, respectively (the slope indicates the substrate, and Figure 3 is the cross section of the hybrid integrated circuit where the piezoelectric resonator is attached). The figure (3) is slightly exaggerated to make it easier to understand.

第2図、第3図において、圧電共振子を構成する四角形
の圧電板80表[9には1対の入力電極10と出力電極
11が銀を焼付けて形成されており、又裏面12には入
力電極10と出力電極11に対向する位置にアース電極
16が形成されている。表面9の対向する2辺に沿って
入力電極10と出力電極11のリード端子14.15が
部分的に形成されており、残りの対向する2辺の全部に
沿ってU字状の金属パターン16.17がvL極10゜
11、リード端子14.15とは別に形成されている。
In FIGS. 2 and 3, a pair of input electrodes 10 and an output electrode 11 are formed by baking silver on the front surface [9] of a rectangular piezoelectric plate 80 constituting a piezoelectric resonator, and on the back surface 12. A ground electrode 16 is formed at a position facing the input electrode 10 and the output electrode 11. Lead terminals 14 and 15 of the input electrode 10 and the output electrode 11 are partially formed along two opposing sides of the surface 9, and a U-shaped metal pattern 16 is formed along the entire remaining two opposing sides. .17 is formed separately from the vL pole 10°11 and the lead terminals 14 and 15.

そして弾性材18がi動の生ずる電極10.11の近傍
を囲み円状に位置している。弾性材18としては例えば
シリコン接庸剤である[トーレシリコン811j−17
00J(商品名)を用いるとよい。
The elastic material 18 is positioned in a circle surrounding the vicinity of the electrode 10.11 where the i-motion occurs. The elastic material 18 is, for example, a silicone adhesive [Toray Silicone 811j-17
It is recommended to use 00J (product name).

又裏面12には表面の金属パターン16.17にほぼ対
向する位置にアース電極13のリード端子19.20が
広く形成されている。別の対向する2辺に沿って部・公
的に金属パターン21.22(4) が電極13、リード端子19.20とは別に形成されて
いる。さらに弾性材18に対向して弾性材23が電極1
3の近傍を囲み位置している。
Further, lead terminals 19 and 20 of the ground electrode 13 are widely formed on the back surface 12 at positions substantially opposite to the metal patterns 16 and 17 on the front surface. Along two other opposing sides, metal patterns 21, 22 (4) are formed separately from the electrodes 13 and lead terminals 19, 20. Furthermore, an elastic material 23 is placed on the electrode 1 opposite to the elastic material 18.
It is located surrounding the vicinity of 3.

圧電板8と同じ大きさであり、セラ2ツク又は合成樹脂
から々る上板24の片面には、対向する2辺に沿って部
分的に金属パターン25.26が形成されているが、こ
の金属パターン25.26は圧電板の裏面の金属パター
ン21.22に夫々対hi して位置する。
On one side of the upper plate 24, which is the same size as the piezoelectric plate 8 and is made of ceramic or synthetic resin, metal patterns 25 and 26 are partially formed along two opposing sides. The metal patterns 25 and 26 are located opposite to the metal patterns 21 and 22 on the back side of the piezoelectric plate, respectively.

集積回路の基板36の表面には圧電板の表面のリード端
子14.15に夫々対応する配線パターン27.28と
、金属パターン16.17に夫々対応する金属パターン
29.30が形成しである361は圧電板の裏面のリー
ド端子19.20の片側が接続される配線パターンであ
り、32.36は集積回路の外部接続用の端子である。
On the surface of the integrated circuit substrate 36 are formed wiring patterns 27 and 28 corresponding to the lead terminals 14 and 15 on the surface of the piezoelectric plate, and metal patterns 29 and 30 corresponding to the metal patterns 16 and 17, respectively. is a wiring pattern to which one side of lead terminals 19 and 20 on the back surface of the piezoelectric plate are connected, and 32 and 36 are terminals for external connection of the integrated circuit.

このように形成した基板36に圧電板8が取付けられて
いるが、リード端子14.15を夫々配線パターン27
.28に半田付け1−1金11i パターン16.17
を夫々金属パターン29.30に半田付けすることによ
り圧電板8はその表面9を下側にして基板36に固着さ
れている。又圧電板8゜の金属パターン21.22には
夫々金属パターン25.26を半田付けすることにより
、上板24が圧電板8の裏面12に固着されている。圧
電板の裏面12のリード端子20は導電ペースト34に
より配線パターン51に接続される。第3図は基板36
に圧電板8が取付けられた状態における上板24のA−
A’m面に沿った断面図であり、35は半田を示してい
る。上板24、圧電板8はさらに全体を外装材により樹
脂封止されるが第3図では省略されており示されていな
い。又上板24と圧電板8の接続部分も第3図では餞示
されていない。
The piezoelectric plate 8 is attached to the substrate 36 formed in this way, and the lead terminals 14 and 15 are connected to the wiring pattern 27, respectively.
.. Solder to 28 1-1 gold 11i pattern 16.17
The piezoelectric plate 8 is fixed to the substrate 36 with its surface 9 facing downward by soldering to the metal patterns 29 and 30, respectively. Further, the upper plate 24 is fixed to the back surface 12 of the piezoelectric plate 8 by soldering metal patterns 25 and 26 to the metal patterns 21 and 22 of the piezoelectric plate 8, respectively. Lead terminals 20 on the back surface 12 of the piezoelectric plate are connected to wiring patterns 51 by conductive paste 34. FIG. 3 shows the board 36
A- of the upper plate 24 with the piezoelectric plate 8 attached to the
It is a sectional view taken along the A'm plane, and 35 indicates solder. The upper plate 24 and the piezoelectric plate 8 are further entirely sealed with resin using an exterior material, but are omitted and not shown in FIG. 3. Also, the connecting portion between the upper plate 24 and the piezoelectric plate 8 is not shown in FIG.

このように構成された本発明の取付は構造では、金属パ
ターンはいずれも基板36、圧電板8、上板24を相互
に半田付けして固着すると共に圧電板8の周辺を固定し
不要振動を抑圧する役割を有してお抄、又弾性材18.
23は外装材が振動の生ずる電極近傍に入らないように
して空隙を形成すると共に不要振動を吸収しさらに半田
付は時に半田が空隙に流れとむことを防ぐ役割を有して
いる。弾性材18.23の平面形状は円状にしであるが
、四角形状であった沙、部分的に周囲が欠けていたりし
ていてもよい。又基板36と上板24に完全に接触して
いてもよいし、又わずかに透間があってもよい。要する
に前記した役割を達し得る状態にあればよい。さらに上
板24は電極近傍に上側から外装材が入ることを防止す
る役割を有しており、圧電板8と必ずしも同じ大きさに
ある必要はない。
In the mounting structure of the present invention configured as described above, all of the metal patterns are fixed by soldering the substrate 36, piezoelectric plate 8, and upper plate 24 to each other, and fix the periphery of the piezoelectric plate 8 to prevent unnecessary vibrations. 18. It has a suppressing role and is also an elastic material.
23 serves to prevent the exterior material from entering the vicinity of the electrode where vibrations occur, thereby forming a gap and absorbing unnecessary vibrations, and also serves to prevent solder from flowing into the gap during soldering. Although the planar shape of the elastic members 18 and 23 is circular, it may be rectangular or may have a partially chipped periphery. Further, the substrate 36 and the upper plate 24 may be in complete contact with each other, or there may be a slight gap. In short, it suffices if it is in a state that can fulfill the role described above. Furthermore, the upper plate 24 has the role of preventing exterior material from entering the vicinity of the electrodes from above, and does not necessarily have to be the same size as the piezoelectric plate 8.

圧電板8の取付は方法はまずその表面9、裏面12に夫
々弾性材18.21t−例えばプリントにより一定の厚
さに塗付する。次に基板の金属パターン29、?)0お
よび圧電板の裏面12の金属パターン21.22にクリ
ーム半田を塗付する。そして圧電板8を基板36上に、
又圧電板の裏面12上に上板24を順次載置する。次に
加熱することによりクリーム半田を溶解して半田付けす
る。その後リード端子20と配線パターン31とを導電
ペースト34によや接続する。
The method for attaching the piezoelectric plate 8 is to first apply an elastic material 18.21t to the front surface 9 and back surface 12 of the piezoelectric plate 8 to a certain thickness by, for example, printing. Next, the metal pattern 29 on the board, ? ) Apply cream solder to the metal patterns 21 and 22 on the back surface 12 of the piezoelectric plate. Then, the piezoelectric plate 8 is placed on the substrate 36,
Further, the upper plate 24 is sequentially placed on the back surface 12 of the piezoelectric plate. Next, the cream solder is melted by heating and soldering is performed. Thereafter, the lead terminal 20 and the wiring pattern 31 are connected to the conductive paste 34.

ところで第4図の平面図には基板36に圧′1板8を載
置した時の基板36に重ねて、圧電板8の表面の電極1
0.11と半田付けされる部分、すなわち金属パターン
16.17、リード端子1415が破線で示しである。
By the way, in the plan view of FIG. 4, the electrode 1 on the surface of the piezoelectric plate 8 is shown superimposed on the substrate 36 when the piezoelectric plate 8 is placed on the substrate 36.
0.11 and the parts to be soldered, that is, the metal patterns 16 and 17 and the lead terminals 1415 are shown by broken lines.

第4図は圧電板の表面9の半田付けされる部分が基板3
60半田付けされる部分と一致していないでずれている
状帽を示しているが、このような状襟でもクリーム半田
がf!解するとその狭面張力により圧電板8が矢印方向
にすべるように移動し、圧電板8と基板66の半田けけ
される部分の位置を完全に一致させた状態で半田付けが
≠能になる。このことは圧電板8と上板24のIA係に
おいても同様である。なお圧電板8、上板24を順次基
板66に載置した時、弾1生材1B、23が鳩板!16
と上板24に例え接触しても接着されない厚みにあるこ
とは熱論必要な条件である。
FIG. 4 shows that the part of the surface 9 of the piezoelectric plate to be soldered is the substrate 3.
60 shows a misaligned cap that does not match the part to be soldered, but even with this kind of collar, cream solder is f! When understood, the piezoelectric plate 8 slides in the direction of the arrow due to the narrow surface tension, and soldering becomes possible with the piezoelectric plate 8 and the parts of the board 66 to be soldered completely aligned. This also applies to the IA section of the piezoelectric plate 8 and the upper plate 24. Furthermore, when piezoelectric plate 8 and upper plate 24 are placed on substrate 66 in sequence, bullet 1 raw materials 1B and 23 are dove plates! 16
It is a thermally necessary condition that the thickness is such that it will not be bonded even if it comes into contact with the upper plate 24.

かくして本発明の・・イブリッド集積回路では、圧電共
振子を基板36に取付ける場合に凹部2を設ける必要も
々い。そして弾性材、電極、リード端子等はいずれもr
ji嘆技術を用いて容易に形成できる。又基板36、圧
電板8、上板24の位置合せについても、半田付けされ
る部分を互に一致させて載置するだけでよく、多少互い
の位置がずれていてもクリーム半田を用いればその溶解
、寺に自動的に修正されるから精度の高い位置合せは必
要としない。従って従来の圧電共振子の取付は構造に比
較して夷造工橿がきわめて簡単になり例えば基板36の
配線パターンに1m接続されるチップ状の他の回路素子
と同時に半田付けすることも可能になるので能率的であ
る。
Thus, in the hybrid integrated circuit of the present invention, it is often necessary to provide the recess 2 when attaching the piezoelectric resonator to the substrate 36. Elastic materials, electrodes, lead terminals, etc.
It can be easily formed using the jigging technique. Also, regarding the alignment of the substrate 36, piezoelectric plate 8, and upper plate 24, it is only necessary to place the parts to be soldered so that they match each other, and even if their positions are slightly shifted, it can be fixed using cream solder. High precision alignment is not required as the melting and temple alignment is automatically corrected. Therefore, compared to the structure of conventional piezoelectric resonator installation, the construction process is extremely simple, and for example, it is possible to solder the piezoelectric resonator at the same time as other chip-shaped circuit elements that are connected to the wiring pattern of the board 36 for 1 m. Therefore, it is efficient.

なお本発明は実施例に限定されることなく広い応用範囲
を有する。実施例における圧電板8の金gハI’−/1
6.17や基板66の金属パターン29.30はリード
端子14,15、配線パターン27.33の面積を大き
くしてこの部分だけで半田付けを強固にできるように設
計すれば除くことも可能である。ス王[1の金属パター
ン21.22、上板24の金属パターン25.26はり
一ド端子19.20に対応する上板24の位置に金属)
(ターンを形改して半田付けできるようにすれば除くこ
ともできる。熱論上板24と圧電板8の間から導電ペー
ストにより基板36の配線パター   愉ン31にリー
ド端子19.20を接続することは可能である。さらに
又基板36、圧電板8、上板24はすべて半田付けによ
り固着されているが、基板36の配線パターンと圧電板
8のリード端子との半田付けの必要な部分以外は接着剤
により固着することも可能である。この場合位置合せの
精度を半田による実施例の場合よりも多少曳くする必要
がある。なお実施例では1素子の圧電共振子について説
明し九が、2素子以上の圧電共振子に本発明を用い得る
ことは言うまでもない。
Note that the present invention is not limited to the embodiments and has a wide range of application. Gold g of piezoelectric plate 8 in the example I'-/1
6.17 and the metal patterns 29.30 on the board 66 can be removed by increasing the area of the lead terminals 14, 15 and the wiring patterns 27.33 and designing so that the soldering can be made strong with just these parts. be. [Metal patterns 21, 22 of 1, metal patterns 25, 26 of the top plate 24, and metal positions on the top plate 24 corresponding to the lead terminals 19, 20]
(This can be removed by changing the shape of the turn so that it can be soldered. Connect the lead terminals 19 and 20 to the wiring pattern 31 of the board 36 using conductive paste from between the thermal plate 24 and the piezoelectric plate 8. Furthermore, the substrate 36, piezoelectric plate 8, and upper plate 24 are all fixed by soldering, except for the parts that require soldering between the wiring pattern of the substrate 36 and the lead terminals of the piezoelectric plate 8. It is also possible to fix with adhesive. In this case, it is necessary to improve the accuracy of positioning slightly more than in the case of the embodiment using solder. Note that in the embodiment, a single element piezoelectric resonator will be explained. It goes without saying that the present invention can be applied to piezoelectric resonators having two or more elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のハイブリッド集積回路の断面図であり、
′42図は本発明のハイブリッド集積回路の圧電共振子
の取付けである部分を分解した時の平面図であり、第3
図は圧電共振子の取付けである部分の本発明の集積回路
の断面図であり、第4図は圧電共振子を集積回路の基板
に裁置した時の平面図である。 1.56:基板、 2:凹部、  3,8:圧電板、 
 4,5:電極、 6:キヤツジ。 9:表面、  10:入力電極、  11:出力電極、
 12;裏面、 13:アース1燻。 14.15,19.20: リード端子。 16.17.2L 22,25,26,29,30  
:金属パターン、  1B、23:弾性材、 24:上
板7.27.2B、31 :配線パターン。 64二導゛亀ペースl−,55:半田。 67:外装材 特許用1娘人 東光株式会社 (ロ)
FIG. 1 is a cross-sectional view of a conventional hybrid integrated circuit.
Figure '42 is an exploded plan view of the mounting portion of the piezoelectric resonator of the hybrid integrated circuit of the present invention;
The figure is a sectional view of the integrated circuit of the present invention of the part where the piezoelectric resonator is attached, and FIG. 4 is a plan view when the piezoelectric resonator is placed on the substrate of the integrated circuit. 1.56: Substrate, 2: Recess, 3, 8: Piezoelectric plate,
4, 5: electrode, 6: cage. 9: Surface, 10: Input electrode, 11: Output electrode,
12; Back side, 13: Earth 1 smoke. 14.15, 19.20: Lead terminal. 16.17.2L 22, 25, 26, 29, 30
: Metal pattern, 1B, 23: Elastic material, 24: Top plate 7.27.2B, 31: Wiring pattern. 64 second lead turtle pace l-, 55: solder. 67: Exterior material patent use 1 daughter Toko Co., Ltd. (Ro)

Claims (3)

【特許請求の範囲】[Claims] (1)  エネルギ閉じ込め型圧電共振子が組み込まれ
たハイブリッド集積回路において、圧電共振子の表裏両
面の電極近傍を弾性材により囲み、少くとも片面の電極
のリード端子を基板上の配線パターンに半田付けするこ
とにより圧電共振子を電極近傍以外の位1tで基板上に
固着し、残りの面を電極近傍以外の位置で基板とは別の
上板に固着してなることを特徴とするノ・イブリッド集
積回路。
(1) In a hybrid integrated circuit incorporating an energy-trapped piezoelectric resonator, the vicinity of the electrodes on both the front and back sides of the piezoelectric resonator is surrounded by an elastic material, and the lead terminal of the electrode on at least one side is soldered to the wiring pattern on the board. By doing so, the piezoelectric resonator is fixed on the substrate at a position other than the vicinity of the electrode at 1t, and the remaining surface is fixed to an upper plate other than the substrate at a position other than the vicinity of the electrode. integrated circuit.
(2)圧電共振子の表裏両面、基板、上板には相互に対
応した位置に圧電共振子を固着するための金属パターン
が設けてあり、圧電共振子は該金属パターンの部分で半
田付けされることにより基板および上板に固着されてい
る特許請求の範囲第1項記載の、ハイブリッド集積同格
、。
(2) Metal patterns for fixing the piezoelectric resonator are provided at mutually corresponding positions on both the front and back surfaces of the piezoelectric resonator, the substrate, and the top plate, and the piezoelectric resonator is soldered at the metal pattern portions. A hybrid integrated apposition according to claim 1, wherein the hybrid integrated apposition is secured to the substrate and the top plate by.
(3)圧電共振子が接着剤を併用して基板および上板に
固着されている特許請求の範囲第1項記載のハイブリッ
ド集積回路。
(3) The hybrid integrated circuit according to claim 1, wherein the piezoelectric resonator is fixed to the substrate and the upper plate using an adhesive.
JP1354982A 1982-01-29 1982-01-29 Hybrid integrated circuit Pending JPS58131808A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1354982A JPS58131808A (en) 1982-01-29 1982-01-29 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1354982A JPS58131808A (en) 1982-01-29 1982-01-29 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS58131808A true JPS58131808A (en) 1983-08-05

Family

ID=11836237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1354982A Pending JPS58131808A (en) 1982-01-29 1982-01-29 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS58131808A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04116428U (en) * 1991-03-29 1992-10-19 京セラ株式会社 Chip type piezoelectric resonator
JPH06132772A (en) * 1992-10-19 1994-05-13 Murata Mfg Co Ltd Chip type piezoelectric resonator and production thereof
JP2004513740A (en) * 2000-11-20 2004-05-13 ボストン サイエンティフィック リミテッド Polypectomy snare instrument
US8287535B2 (en) 2005-05-11 2012-10-16 Mayo Foundation For Medical Education And Research Apparatus and methods for internal surgical procedures

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5433714A (en) * 1977-08-19 1979-03-12 Mitsubishi Electric Corp Automatic playing envelope generating system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5433714A (en) * 1977-08-19 1979-03-12 Mitsubishi Electric Corp Automatic playing envelope generating system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04116428U (en) * 1991-03-29 1992-10-19 京セラ株式会社 Chip type piezoelectric resonator
JPH06132772A (en) * 1992-10-19 1994-05-13 Murata Mfg Co Ltd Chip type piezoelectric resonator and production thereof
JP2004513740A (en) * 2000-11-20 2004-05-13 ボストン サイエンティフィック リミテッド Polypectomy snare instrument
US8287535B2 (en) 2005-05-11 2012-10-16 Mayo Foundation For Medical Education And Research Apparatus and methods for internal surgical procedures
US8747403B2 (en) 2005-05-11 2014-06-10 Mayo Foundation For Medical Education And Research Apparatus and methods for internal surgical procedures
US9839440B2 (en) 2005-05-11 2017-12-12 Mayo Foundation For Medical Education And Research Apparatus and methods for internal surgical procedures

Similar Documents

Publication Publication Date Title
US5623236A (en) Chip-type piezoelectric-resonator and method of manufacturing the same
JPS6351547B2 (en)
CN110706925B (en) Electronic component
JPS5985123A (en) Air-tight base for piezoelectric oscillator
JP5918454B1 (en) Piezoelectric parts
JPH11150153A (en) Electronic component
JPH054339Y2 (en)
JPS58131808A (en) Hybrid integrated circuit
JPH11251186A (en) Stacked ceramic capacitor
JP2018191170A (en) Coupling structure of resonator and resonator stack
JP2536627B2 (en) Chip-shaped piezoelectric component
JPS63161710A (en) Piezoelectric resonator and its manufacture
JP2005033450A (en) Electronic component and its manufacturing method
JP2563964Y2 (en) Surface mount type resonator
JPS6340909Y2 (en)
JPH0741212Y2 (en) Piezoelectric vibrator
JPH06169030A (en) Electronic component package, electronic component package board and manufacture of electronic component package board
JP2000353829A (en) Thermoelectric module and manufacture of the same
JP3157975B2 (en) Ladder type filter
JPH08191181A (en) Manufacture of electronic component and electronic component
JP3986023B2 (en) Electronic component module, non-reciprocal circuit device and manufacturing method thereof
JPH03258107A (en) Chip type electronic component, element and mount method
JP4070131B2 (en) Electronic component module, non-reciprocal circuit device and manufacturing method thereof
JPH01231384A (en) Manufacture of piezoelectric part
JPH08274569A (en) Piezo-resonator