JPS58129551A - Microprogram controlling circuit for digital processor - Google Patents

Abstract

PURPOSE:To execute an operation of the whole process at a high speed, by reading out an ROM independently, dividing it into modules of 2N-th power pieces, shifting them by 1 clock cycle in order, executing the read-out operation in parallel, and operating a controlling circuit by N-th power of 2. CONSTITUTION:A microprogram counter 11 of a microprogram controlling circuit 1 is increased by ''1'' by a clock 7, and an output 1102 except LSB2 bits of its output is provided to address registers 111-114 corrected in parallel. Also, an LSB 2 bit output 1103 is provided to gate circuits 141-144 to which the clock 7 is inputted, through a decoder 14, and by the timing shifted by 1 cycle each, which is outputted by said circuits 141-144, data of the registers 111-114 are updated. By outputs of these registers 111-114, corresponding ROMs 121- 124 are operated independently, and outputs 1211-1241 of each ROM are provided to a multiplexer 131. In this way, the controlling circuit 1 is operated by N-th power of 2, and the operation of the whole process is executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control circuit for controlling the operation of a digital processor.

As shown in FIG. 1, the digital processor that performs microprogram control includes a microprogram control circuit 1.
．． Microprogram decoding circuit 2. Arithmetic circuit 3 and a clock having a constant period.

It is composed of a black circuit 4, which generates a

The microprogram control circuit 1 which receives the clock signal 7 from the clock circuit 4 reads out the microprogram 5, decodes it in the microprogram decode circuit 2, and controls the arithmetic circuit 3 by its output 6. Conventionally, in this type of microphone, the program control circuit l has a read-only memory 12 storing a microprogram for performing arithmetic control, and a read-only memory 12 for storing a microprogram for performing arithmetic control. The micro program counter 11 outputs the address of the read-only memory 12 by incrementing the value by +1 every time the output 1 of the micro program counter 11 increases.
Read-only memory 12 with 101 as memory address
It consisted of four microphone programs 1201t read out from the microprogram register 13 held every clock cycle. The operation will be explained below with reference to the operation diagram shown in FIG.

The micro program counter 11 has a constant period of 0. 7), increases the value by +1, and its output is 11
01 is ni, ni+1. The read-only memory is read as consecutive addresses such as +2. The read-only memory output 1201 is a read period (output irregular period)
Microprogram 1203 determined after 1202
becomes. (In Figure 3, the program stored at address +1 is MPX, and the program 9 stored at address +1 is MPIK.
+1 grade.

) The microprogram 1203 determined in the output 1201 of the read-only memory 12 is held in the microprogram register 13 at the beginning of the next cycle, and becomes the output 5, which is 1 cycle. A constant 1x4 program (Mpx, MPK+1) during the cycle
etc.). In this way, the microprogram control circuit 1 supplies microprograms such as MPt and MPt+xMPic to the microprogram decoding circuit 2 every clock cycle.

As mentioned above, in the conventional microphone program control circuit,
When reading from the read-only memory of one module that stores a microprogram,
Since each clock cycle always includes a read-only memory read period 1202, in order to speed up the clock cycle that determines the calculation speed of the entire digital processor, read-only memory elements with a short read period 1202 are used. The disadvantage was that it had to be used.

The present invention divides the conventional single module memory into 2ON modules (N is a positive integer) that can be read independently, and reads each memory module sequentially. The read operation is performed in parallel with a shift of one clock cycle, and the nine parallel 2N microprograms read out with a shift of one clock cycle at a time are reorganized into columns on the time axis by a multiplexer. And by adopting a circuit configuration that performs a read operation every 2 N cycles for one memory module,
A microprogram control circuit for digital processors that eliminates the above drawbacks and enables full operation in clock cycles that are 2N times faster than conventional ones even when using read-only memory elements that have the same read time as conventional ones. It provides:

Microprogram 2 for digital processor according to the present invention
The system control circuit consists of a microprogram counter whose value increases by +1 each time the circuit is turned on, and a 2ON circuit connected in parallel with the counter output excluding the L8B@N bit as input.
2ON address registers, 2ON read-only memories that can be read independently using the outputs of each address register as address inputs, and L8B of a microprogram counter that takes the outputs of 2ON address registers as inputs, respectively. A multiplexer that performs switching control based on the N bit and g outputs, a microprogram register that holds the output of the multiplexer for each cycle and the output of the microprogram control circuit, and a microprogram. Counter L 88gN
Use the bit output to create multiple pulses for holding the output of the microprogram counter in the 2N address registers at different timings.
It is characterized by a configuration consisting of a timing circuit. For 2ON read-only memories, read operations are performed sequentially, cyclically, sequentially, and in parallel, and the programs read in parallel are reorganized in a line on the time axis using a multiplexer. As a result, the read operation for each glue-only memory can be performed once every 2 to the power clock cycle.

Therefore, even when a read-only memory element having the same read time as the conventional one is used, the microprogram 2 can be controlled to operate at q cycles faster than the conventional one. Although the conventional circuit had the disadvantage that it was difficult to increase the clock cycle speed, the present invention solved this disadvantage and, as a result, achieved an increase in the calculation speed of the digital processor.

Next, embodiments of the present invention will be described with reference to the drawings.

Figure 4 shows a microlog 2m control circuit according to the present invention.
FIG. 2 is a block diagram of an example of a circuit configuration when =2. This embodiment includes a micro program counter (binary counter) 11 whose value increases by +1 with a clock 7 having a constant cycle, and a microphone connected to L8 of the program counter 11 to an output 1102 excluding 2 bits on the 3 side. address register Al11. Address register B11
2. Address register C113. Address register D1
14 and these address registers A, kl, C, D
There are four gate-only memories Al21 . Read only memory B122
.

Read-only memory C123. Read-only memory D124 and these read-only memories A and H0C.

Each output of D 1211.1221.1231.124
1 as input, L8B of micro program counter 11
@2-bit output 1103 selects the output! Lunaplexer 131, microprogram register 13 which holds V multiplexer output 1311 every clock cycle and outputs a constant microprogram 5 for one clock cycle, and L813 side of microprogram counter 11. A decoding circuit 14 decodes the 2-bit output 1103, and a microprogram 2m counter output 1102 is decoded from the decoding circuit and the clock 7.
Gate/circuit 141-14 that generates rounding timing pulses held in three address registers A, B, C, and D
It consists of 4.

Next, the operation will be explained with reference to FIG. 5, which shows the operation timing for the embodiment shown in FIG. 4.

Micro program counter output 1101 a, rip
Increase the value by +1 at the start-up timing of Tsuku 7,
ni -1, ni, ni +1. takes a value such as +2 (K is a positive integer). Output 1102 excluding L8B@2 bit of output 1101 is m-1%-1-1 every 4 clock cycles, assuming K=4N (M is a positive integer).
It takes a value like . Also, LSB side 2 upper 2 of output 1101
Bit output 11034 clock cycles KO. 1.
04 address registers A, H that return the value of 2.3
, C, D (111-114) Mori, the gate circuit output (latch timing pulse) produced by the decoding circuit 14 that received the microphone four-gram counter output 1103 and the gate circuits 141 to 144 that received the ptsu 7 )1411.
1421.1431.1441], the microprogram counter output 1l102 (assumed) is held at the timing of 1421.1431.
l, N+2, etc.) 04 read-only memories A, B, C
, D (121-124) are four independent address registers A and B.

C. Since the four groups operate in pairs with D (111 to 114) and perform similar operations at timings shifted by one clock cycle, the operation of group A will be explained below.

Read-only memory Al21 is address register A1
Reading is performed using the output 1 1 1 1 (denoted as M) of 1l as a memory address, and the output 1211 is the microprogram 1213 (denoted as AM) that is determined after the read period 1212. AM is read-only memory A.
C) program stored at address M). Then, in the next clock cycle after the reading is completed, the output 11 of the address register A is again sent to the read-only reader.
Reading is started with memory address 11 (assumed as Ilil+1), and the finalized microprogram is output (assumed as AM+1. Aia+t is the same as above).
program stored at address ii+1). Similarly, read-only memory A is read out every four clock cycles, and programs 2 are read out in the order of addresses.

Due to the above operations, read-only memories A, B,
C, D output 1211.1221.1231.1241
are each determined to be 9 micrograms and 4 grams 1213.1223
．． 1233 and 1243 are included every four clock cycles, and are input to the multiplexer 131 at timings shifted by one clock cycle from each other. Multiplexer 13
1 is! The rounding and multiplexer output 1311a, the fifth
1 read only memory A, B, C, D as shown in the figure
The microprograms created from the above are arranged in order for each clock cycle (AM, HM, C
M.DM.

AM+1, BM+1, 0M+1, DM+1, etc.). The micro program register 13 outputs the multiplexer output 131 at the rising edge of clock 7.
1 and outputs a constant microprogram 5 for one clock cycle.

Therefore, in the microprogram control circuit according to this embodiment, since the read operation for each read-only memory is every four clock cycles, it is recommended that the microprograms conventionally stored in one read-only memory are shown below. The data is classified into addresses that are an integer multiple of , and divided and stored in four single-only memories.

Read-only memory A: Conventional program at 4M address (N is a positive integer) Read-only memory B: Conventional program at address 4M+1 Read-only memory C; Conventional program read-only memory at address 4M+2 D: Conventional program at 4M\3 Programming the address As a result, the microprogram control circuit of this embodiment can operate at a clock cycle four times faster than the conventional IT using a read-only memory element having the same read time as the conventional one. .

The above is an example in which the read-only memory is divided into four (divided to the N power of 2) using the LaB side 2-bit (N=2) output of the microprogram counter. Even when N=3, etc., the microprogram control circuit operates similarly to the above.◎ According to the present invention, tt using a read-only memory element with a conventional read time, 2 to the N power of the conventional This has the effect of making the microprogram control circuit operable with a clock speed of . As a result, it becomes possible to increase the calculation speed of the digital processor as a whole.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the general configuration of a digital processor, Fig. 2 is a block diagram showing a conventional microprogram control circuit, Fig. 3 is a timing diagram of the signals of each part, and Fig. 4 is a block diagram showing the conventional microprogram control circuit. A block diagram showing one embodiment, and FIG. 5 is a timing chart of signals of each part thereof. l...Microprogram control circuit, 2...
...Microprogram decoding circuit, 3...
・Arithmetic circuit, 4... Clock circuit, 5...
...Micro program, 6...Arithmetic control signal, 7...Clock, 11...Micro program counter, 12...Read only memory% 13... ...Micro program register, 14...Decode circuit, 111-114...
...Address register A, B, C, D%121~1
24... Read only memory A, B, C, D,
131...Multiplexer, 141-144.
...Gate circuit, 1101...Micro program counter output, 1102...Output except for the LSB side 2 bits of the micro program counter,
1103... L of micro program counter
8B side 2-bit output, 1201...read-only memory output, 1202...read-only memory read period, 1203...read-only memory confirmed microprogram output, 1111, 11
21, 1131.1141... Each output of address registers A, B, C, D, 1211, 1221゜12
31.1241 ... Read only memory A,
B.C. Each output of D, 1212, 1222, 1232.1242
...Reading period % for each of read-only memories A, B, C, and D 1213, 1223, 1233.
1243... Read only memory person, B, C,
Each confirmed microprogram output of D, 1311...
...Multiplex output, 1411.1421,143
1.1441...Gate circuit 141.142,
Each output of 143 and 144.

Claims (1)

[Claims] The value increases by 1 for black and riyoshi! Microprogram counter and L 8 B@N of the output of this counter
2N address registers connected in parallel with inputs excluding bits and g, 2N glue-only memories that can read each output of these address registers independently as address inputs, and these 2N glue-only memories. A multiplexer that receives the outputs of the dual-only memory and whose switching is controlled by the L8B@N bit of the counter output, and a microprogram register that holds the output of this multiplexer every clock cycle and takes out the output. and for holding the output of the counter in the 2N address registers at different timings using the L8B@N bit output.
1. A microprogram control circuit for a digital processor, comprising: a latch tie construction circuit for generating chip pulses.