JPS58129521A - Microcomputer device - Google Patents

Abstract

PURPOSE:To reduce malfunctions, and to stabilize an operation, by controlling a switching element provided on a read and write line of a CPU, by an output signal of a reset signal generating circuit for generating a signal which releases reset of the CPU. CONSTITUTION:On an electric power supply controlling circuit 12 for controlling electric power supply to a CPU1, a reset signal generating circuit 12-13 operated by an output of an NOR gate 12-4 for outputting an on-and-off control signal of an electric power supply line of the CPU is provided. The circuit 12-13 is constituted of a monostable multivibrator 12-131 and a gate circuit 12-132, and an output from the circuit 12-132 is inputted to a reset terminal of the CPU1, and the gate of a switching element Q12 provided on a read and write R/W line of the CPU1. Whe an electric power supply is turned on to the CPU1, and it has become a stable state, and reset state is released by an output signal of the circuit 12-13, and the R/W line is made to conduct by the Q12, therefore, malfunctions of read and write are reduced, and the operation is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION 2., -7 The object of the present invention is to provide a power-saving type microcomputer device.

Generally, the time a microcomputer device spends performing a required task is extremely short compared to the time it spends waiting for instructions for that task. For example, if we now consider the case of inputting data using a keyboard, the ratio of the time interval during which a person presses a key to input predetermined data and the time it takes for a microcomputer to process it is several hundred times greater. In other words, the time the microcomputer device actually performs the work is a very short time, several hundred times longer than the time it takes to wait for instructions for the work.

By the way, all microcomputer devices that have been used in the past are constantly energized, not only when they are performing the required work, but also when they are waiting for instructions for that work, so considering their power consumption, This means that a large amount of power is wasted during the time spent waiting for the instruction.

The present invention eliminates the above-mentioned drawbacks of the conventional technology.The present invention applies the required power to the central processing unit only when the microcomputer device performs the required work, and when the microcomputer device is in the 3-page state waiting for an instruction, the power is applied to the central processing unit. The present invention provides a microcomputer device that cuts off the power supply and has extremely low power consumption as a whole.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A microcomputer device according to the present invention will be described below with reference to drawings of an embodiment.

FIG. 1 is a block diagram of an embodiment of a microcomputer device according to the present invention. In FIG. 1, 1 is a microprocessor including a central processing unit (hereinafter referred to as CPU), 2 is an address decoding/chip select signal generation circuit, 3 is a system RAM, 4 is a system ROM, and 5-1
is a display RAM, 5-2 is a display driver, 6-3 is a display, 6-1 is a keyboard scanning gate circuit, 6-2 is a keyboard, 6-3 is a keyboard output buffer 7-17 is a clock pulse generation circuit , 8 is a power supply, and 9 is a power supply circuit, and these components constitute a conventionally known microcomputer device.

10 is a timer circuit, 11 is a reduced voltage detection circuit,
12 is a power supply control circuit, 13 is a switch circuit, and 14 is a peripheral device such as a printer or an expansion memory. In this embodiment, the power supply control circuit 12. A major feature is the addition of the switch circuit 13.

Note that the power supply control circuit 12 has an input terminal that receives the address data of the CPU 1, a control line, and a timer circuit 10. It is connected to the keyboard scanning gate circuit 6-1 and the address decoding/chip select signal generation circuit 2, and the output terminal is connected to the reset interrupt of the CPU 1 and the read/output terminal via the switch circuit 13.
Connected to the write terminal.

FIG. 2 is a block diagram showing the main parts of the above-mentioned embodiment in more detail, and will be explained in more detail below using this figure together with FIG. 1.

(1) Structure and operation of the keyboard portion The keyboard scanning gate circuit 6-1 uses each of the address lines φ to 7 of CjPUl as one input.

The chip select signal C5XX of the address decode/step select signal generation circuit 2 is commonly input to the other circuit 8.
It is composed of OR gate circuits 6-11 to 6-18. And these OR gate circuits -11 to 6-
All 18 inputs are connected to the VDDO power supply via resistors 6 and pulled up. The outputs of the OR gate circuits -11 to 6-18 are applied to each keyboard 6-2 as a scanning signal for the keyboard 6-2. As is well known, the keyboard 6-2 has a scanning example (
The configuration has contact points S at the intersections of the matrices on the X-axis) and the output side (Y-axis), respectively. keyboard 6-2
The output ends (8 in this embodiment) of the output buffer 7-6-
It is connected to each input terminal of tri-state buffer 1-6-31 in 3 and each input terminal of OR gate 6-32.

In this case, all input terminals of the OR gate 6-32 are grounded and pulled down via resistors. The control input terminals of the tri-state buffers 6-31 all have address data/chip in common.

Chip select signal csx of preselect signal generation circuit 2
o is applied. And tristate buffer 6
-31 output terminals are data bus D of CPU1, respectively. −
When the chip select signal csKx connected to D7 is at the no level, that is, when CP'[TI is not scanning the keyboard 6-2, the keyboard scanning gate circuit 6-1 The output of each OR gate 6-11 to θ-18 is at high level. - The input examples of the blade output buffers 7-6-3 are all at low level because they are pulled down, and the output of the OR gate 6-32 which receives these inputs is at low level. If any key on the keyboard 6-2 is pressed in this state, the corresponding contact S is turned on, so that the corresponding OR gates 6-11 to 6-18 in the keyboard scanning gate b path 6-1 are pressed. The output is transmitted to the input side of the output buffer 1-6-31 through the upper and lower turned-on contacts, and therefore the output back, 7-
The output side of the OR gate 6-32 in 6-3 changes from low level to high level, and a so-called key suppression signal is output.

The output terminal of the OR gate 6-32 in the output buffer 6-3 is connected to the power supply control circuit 12, and this OR gate)
When the output terminal of 6-32 becomes high level, the power supply control circuit 12 is driven by this.

Operate cptz as described below. Therefore, on the 7th page, I learned that CPU1 operated the key in this state,
Keyboard 6-2 for knowing which key was operated
will start scanning. Now, the operation of the CPU1 is started, the address signal section φ is at high level, the other address signals M1 to M7 are at low level, and the chip select) signal (8K
When I becomes low level, the OR in the keyboard scanning gate circuit 6-1 to which the address signal section φ is input is
Only the output of the gate 6-11 is at high level, and the others are at halo level. Therefore, in this state, if any of the keys on the scanning line corresponding to the OR gate to which the address signal section φ is input is suppressed, the signal is transmitted to the OR gate (6-11) via the contact S corresponding to that key. The output of is applied to the output buffer corresponding to the contact S, tristate buffer 1-6-31 in -6-3, and the input side of the tristate buffer 7-6-31 becomes high level. . Therefore, in this state, the chip select signal csx
o to low level and data bus DoND.

By reading this information, you can know which □ key is being pressed. If none of the keys of the scanning line corresponding to 6-11 (to which the address signal part is applied) is pressed, the output buffer 7
The outputs of the tri-state buffer 6-31 in -6-3 are all at low level, and the CPU 1 moves on to the next scanning procedure.

That is, the address signal section is set to low level, address signal section 1 is set to high level, and address signal sections 2 to 7 are set to low level, and the pressed key is searched using the same procedure.

(2) Configuration and operation of power supply control circuit (MU) Power on/off control using key press signals.

Keyboard output back, -6-3 OR game)6-3
The key press signal appearing from 2 is output from 2 in the power supply control circuit 12.
It is applied to the above-mentioned MND gate 12-1 as one input of the human cam Nl) gate 12-1. Above mund gate 1
The output of the keyboard/display on/off memory 12-8 is applied to the other input terminal of the keyboard/display on/off memory 12-8. MND game) 12
The output terminal of -1 is connected to one input terminal of 3-person power OR game) 12-2, and the other input terminal of 3-person power OR game) 12-2 is connected to the borrow from timer circuit 1o. Signal, reduced voltage detection circuit 1
1 is applied. The output terminal of the three-manpower OR system 12-2 is connected to the input terminal of the interrupt signal memory 12-3. Therefore, when the output terminal of the OR gate 12-2 changes six levels from the low level, the interrupt signal memory 12-3
The output changes from low level to high level and acts to maintain this state. Meanwhile, the above interrupt signal memo'
)-12-3 is connected to the output terminal C81 of the address decode/chip select signal generation circuit 2, and is configured to be reset by the select signal 081 applied thereto. That is, when the address decoding/chip select signal generation circuit 2 applies the select signal OS 175E10/.-- to the reset input terminal of the memo')-12-3, this causes the interrupt signal memory 12-3 to be applied.
3 is reset and its output terminal changes from high level to low level. Interrupt signal memo above! The output terminal of J-12-3 is connected to one input terminal of a four-person NOR gate 12-4. The other input terminal of 4-person NOR game) 12-4 has the first. Second power on/off memory 12-5
, 12-9 and an interrupt signal IEXT INT from the peripheral device 14 or the like are applied.

Further, the output of the interrupt signal memo T)-12-3 is applied to one input end of the two-person cam ND game) 12-7 via an inverter 12-6.

The output of the four-man powered NOR game 12-4 is applied to the switch circuit 13 and the reset signal generation circuit 12-13. The input terminal of the reset signal generation circuit 12-13 is
When the level changes from high to low, the specified time width (
For example, a monostable multi-byte 11-page printer 12-131, as shown in FIG. ! :NOR gate 12-132
It consists of a circuit consisting of: The output terminals of the reset signal generation circuits 12-13 are directly connected to the reset terminal FIIE81CT of the cptz and also connected to the base of a protection NPN transistor Q12 connected to the read/write signal line via a resistor RO. . On the other hand, the interrupt signal EXT2NT from the peripheral device is applied to the other input terminal of the MND game 12-7. The output terminal of this MND gate 12-7 is connected to the interrupt signal input terminal 2NT of 0PU1.

Here, the protection NPN) transistor Q12 is CP
When the power supply of U1 is switched, the read/write signal is always set to high level even if the CPU1 is in an unstable state.

Keep the entire system in read state, including system RAM 3 and peripheral devices 1.
This is to prevent unstable data writing to 4. Therefore.

This transistor Q12 has an emitter and a rear connected to the read/write signal terminal R/W of cptz, a collector connected to the VDDO power supply via a resistor, and the collector further connected to various parts as a read/write signal.

When the output of the reset signal generation circuit 12-13 is low level, that is, when the reset signal is applied to 0PU1, the transistor Q+2 is off, and the read/write signal PI/W appearing on the collector side of the transistor Q+2 is Always at high level and on the read side.

When the output of the reset signal generating circuit 12-13 becomes high level, this is applied to the CPU 1, so that the CPU 1 is released from reset and starts operating. In this state, the transistor Q12 is turned on, and the read/write signal R/W from CPJ appears directly at the collector via the transistors Q and 2.

The switch circuit 13 is a well-known (PNP) transistor QC.
s, resistor R1S r R+4 s speedor, and capacitor OI5 can be easily constructed into 13 pages. When the output of the four-power NOR gate 12-4 becomes low level, the transistor QCs turns on and the power supply V
DDO is applied to the power supply terminal VDD of cptz.

The first power on/off memory 12-6 is constituted by a D7 lip-flop circuit, and its D input terminal receives data from cptz, such as Do, and its strobe input terminal receives address decode/step select signal generation circuit 2. Chip select signal line AS2 from
is applied.

Therefore, when cptz specifies a predetermined address and outputs data, when that specific address is decoded by the address decode/chip select signal generation circuit 2 and generates the select signal 082, the memory 1
2-5 to write the above-mentioned predetermined data.

And keyboard display, on-off memory-12-8
Similarly to the memory 12-6, the memory has 14 pages, and in this case, the chip select signal O8g from the address decode/chip select signal generation circuit 2 is applied to the strobe input terminal.

Now, the operation of operating the CPU 1 by pressing any key on the keyboard 6-2 will be described.

Figure 3 is a waveform diagram of each part drawn to make these operations easier to understand.

This will be explained using FIG.

In Fig. 3, MU shows the output waveform of 6-32, which occurs when any key is pressed, and time! It shows that the key was pressed at , and the +- key was released at τ2 for one hour. The output of OR gate 6-32 is output to ND gate 12.
-1°OR) Interrupt signal memo IJ via 12-2
-12-3, and changes the output of the interrupt signal memory 12-3 from low level to high level as shown in FIG. 3B. When the output of the interrupt signal memory 12-3 changes from low level page 16 to high level, the output of NOR gate 12-4 changes from high level to low level, so transistor Ch5 of switch circuit 13 is turned on, and the power supply terminal of CPtT1 is turned on. A predetermined power supply voltage vD is applied to VDD as shown in FIG. 3C.
DO is applied.

The output of the NOR gate 12-4 is simultaneously applied to the monostable multivibrator 1 of the reset signal generation circuit 12-13.
2-131. Therefore, the monostable multivibrator 12-131 is kicked by the output of the NOR game 12-4, and generates at its output end a required pulse having a shorter time width than the output of the NOR game 12-4. Therefore, the following stage is powered by two people) 10R gate 12
At the output terminal of -132, the required output appears during the period when the output from the NOR gate 12-4 continues to appear after the above-mentioned pulse disappears. In other words, NOR game) 1j71
32) i0R gate 12-4 output and monostable multi
The output of vibrator 12-131 is used as input,
The device is configured to output a required high level output only when both of these outputs become low level.

Therefore, during the period when the monostable multipipe rake 12-131 is kicked by the low level output from the NOR gate 12-4 and the high level output appears from the monostable multivibrator 12-131, the NOR gate 1
When no output appears from the NOR gate 12-132 and the output of the monostable multivibrator 12-131 becomes low level, the required high level output from the NOR gate 12-132 appears.

Therefore, the output of the switch circuits 12-13 eventually becomes high level for a period of time T6 from time T5 as shown in the third diagram. And this output is the reset terminal RE of 0PTJ1
SET,) applied to the base of transistor (h2.C
When a high level output is applied to the reset terminal REMIT of PU1, 0PU1 releases its reset state for 17 pages and starts operating.

On the other hand, the output of the 1 interrupt signal memory 12-3 is applied to the interrupt signal input terminal 1NT of 0PU1 via the inverter 12-16 and the ND gate 12-7. Therefore 0
A signal of polarity exactly opposite to that of FIG. 3B is applied to the interrupt signal input terminal INT of PU1. When the CPU 1 is released from reset and completes the initial routine processing, the input terminal 1
The interrupt signal applied to NT is accepted. C.P.
When U1 accepts the above interrupt signal, the keyboard 6
-2 address to read data, i.e. select signal csxo
to occur. Therefore, the tristate buffer 7-6-31 in the output puff 7-6-3 becomes operational,
Data on the keyboard 6-2 is read. In this case, since any one of the 8 bits of data lines n, , n, is always at a high level, the cpt
It can be seen that an interrupt always occurs when z is turned on. Then turn on the first power.

Since the select signal C82 and the signal from the data line Do are applied to the 18 base off memory 12-5, power-on data is written to the power-on/off memory 12-6.

In other words, the select signal C82 is as shown in FIG. As shown in FIG.
6 is written. Then, after that, select signal 08+
occurs at time T5, and the interrupt signal memory 12-
Reset 3. Next, the keyboard is scanned as described above to detect the pressed key and perform a predetermined task.

When this work is completed, the select signal 082 is generated again at time t6, and power-off data is written into the power-on/off memory 12-6. However, 9
All the inputs of the NOR gates 12-14 become low level, and the outputs of the fOR gates 12-14 return to high level.

As a result, the switch circuit 13 is turned off, and power supply to the CPυ119 page is stopped.

As described above, according to the above embodiment, the key suppression start time T1
Therefore, the CPU 1 can be energized for a time period T1 to T6, which is significantly shorter than the time period up to the key press release time T2, and power consumption can be significantly reduced.

@) Power ON/OFF control of CPH by timer circuit The timer circuit 10 receives the output of the clock pulse generation circuit 7 and divides it into channels as shown in FIG. 5.
1 and the seconds counted down in response to the output of this branch unit 10-1.

Respective presettable counter 10-2 for minute 9:00
．． 10-3.10-4 and these counters 10-2
, 10-3, and 10-4 to the data bus D of the CPU1. ~D.

It is composed of buffers 1Q-5, 10-8° and 10-7. Presettable counter 10-2.
The preset input terminals of 10-3 and 10-4 are each connected to CP.
It is connected in parallel to the data bus of t71, and the output C from the address decode/chip select signal generation circuit 2
3TSW, C1C19T, and C3THW are configured so that data specified by each cptz via the data bus can be preset in each counter 10-2.10-3.10-4. For example, if 03:61:29 is now preset and toshi, the pulses at 1 second intervals of the divider 10-1 will be sequentially subtracted, and after 3 hours, 61 minutes and 29 seconds, a borrow signal will be output from the top counter 10-4. This causes the output of the interrupt signal memory 12-3 to go high via the OR signal 12-2.

As a result, the CPU 1 is energized in the same way as when the key is depressed. In FIG. 3, the state at time T7 shows the state in which the timer 10 generates a borrow signal. Even in this state, the output of the interrupt signal memory 12-3 and the power supply of aptrl are as shown in FIG. 3B as in the case of key suppression.

As shown in the third diagram, the signal rises at time t7, and the page set signal S21 rises after a predetermined time delay, as shown in the third diagram. Therefore, the CPU 1 is released from reset at this point and starts its operation.

After that, the power-on data is written in the power-on/off memory 12-5 in the same way as when the key is pressed, and then the side-in signal memory 12-3 is reset. It is possible to write data to the power on/off memory 12-5 and turn off the power to the CPU 1.

In this case, it is also possible to use the interrupt signal memo IJ-12-3 as a power on/off memory.

That is, in this case, the CPU 1 can be easily turned off by resetting new data to the timer circuit 10 at time t8 after completing a predetermined task, and then resetting the interrupt signal memory 12-3 at time t9. can do.

(C) Power on/off control by peripheral devices The interrupt signal KXT 1NT from the peripheral device is applied to the interrupt signal input terminal of the CPU 1 via the 22-page ND game) 12-7, and the NOR gate) 12-4. It is also applied to the switch circuit 13 via the switch circuit 13. Therefore, even if the interrupt signal ΣXTINT is generated from the peripheral device 1, the switch circuit 13 is turned on in the same way as when a key is pressed.
After power is applied to 0PU1, similar operations will be performed.

Oka: Controlled by a reduced voltage detection circuit The reduced voltage detection circuit 11 includes a voltage detector 11-1 such as a Schmitt circuit that detects the voltage value of the power supply 8, a memory 11-2 that stores its output, and an address decode/chip select for the output. The select signal C8V from the signal generation circuit 2 connects the data bus of the CPU 1 to, for example, D7.
It is comprised of a buffer 11-3 for enabling the PU 1 to read the voltage value stored in the memory 11-2. The output of the memory 11-2 is also applied to the input terminal of the voltage control circuit 12-2.

When the voltage of the power supply 8 drops below a certain value, the voltage detector 11-
1 changes, and this is transmitted to and stored in the memory 11-2. Then, the contents stored in the memo IJ-11-2 are directly applied as an input to the memo IJ-12-2, so that the CPU 1 enters the operating state in the same manner as when the key is pressed. When the CPU 1 becomes operational, the contents stored in the memory 11-2 are transferred to cptz via the buffer 11-3.
Detects when the power supply voltage drops below a certain value. Therefore, by this detection, for example, the display 5
It is possible to display a warning such as "-31C'POWKRTRABIJ" and control the system so that it will not accept any subsequent work.

The memory 11-2 is configured such that the contents stored therein are read out by the select signal C8v from the address record/chip select signal generation circuit 2, and the stored contents are read out by the select signal C8v. is configured to be reset immediately after it is read.

(4) Keyboard/display on/off operation keyboard 6-
When any key of 2 is pressed, the CPU 1 starts operating as described above, so if the key is pressed carelessly, there is a risk that the 0PU1 will operate intermittently and waste a large amount of power. To prevent this, keyboard/display on/off memory 12-8, second power on/off memory 12-9° inverter 12-10, 12-11, on/off switch in keyboard 6-2 are installed. 6-21 and a power supply control circuit 12-12 for the display device.

The keyboard/display on/off memory 12-8 is constituted by a D-type FRI, PFL, and P circuit, and its D input terminal is connected to the data line Do of the CPU 1, and its strobe input terminal is connected to the address decoding/chip select signal generation circuit 2. A select signal line OB3 from 26 pages is connected. Therefore, 0PU1 is the memory 1
On or off data will be written to 2-8.

The output of the keyboard/display on/off memory 12-8 is used as the input of the iD game 12-1 and the input of the open-drain inverter 12-10, that is, the gate input of the N-channel transistor. The output terminal of the inverter 12-10 is connected to the input terminal of the inverter 12-11 and is grounded via the on/off switch 6-21 in the keyboard 6-2, and further controls the display power control circuit 12-12. Connected to the input end.

The output end of the inverter 12-11 is connected to the input end of the second power on/off memory 12-9, and when the output of the inverter 12-11 changes from low level to high level, the memory 12- 9 is configured to change its output from low level to high level and hold it. And memory 12-e26 page;! Reset input and address decode/chi.

A select signal OBa from the preselect signal generation circuit 2 is applied, and the circuit is configured to be reset by this select signal O8a.

Assume that OFF data is written into the keyboard/display on/off memory 12-8 by the CPU 1 via the select signal O8s line from the address decode/chip select signal generation circuit 2 and the data line Do. In this case, the output of the memo jj-12-8 becomes low level, and the input to the memory module 12-1 becomes low level, so press any key on the keyboard 6-2 to change the keyboard output buffer. Even if the output of the OR gate 6-32 in 6-3 is changed from a low level to a high level, the output of the 12-1 does not change, and the power supply voltage is still not applied to the CPU 1. In this state, when the on/off switch low 21 in the keyboard 6-2 is turned on, the input of the inverter 12-11 changes from high level to low level, and its output changes from low level to high level. Therefore the second power on-off memory 1
2-9a The output changes from low level to high level and maintains this state. Then, since the output voltage is applied to the switch circuit 13jC via the 101 game) 12-4, power is applied to 0PU1, and tl and cPUl start operating. When the CPU 1 starts operating, the select signal (58g) of the data line DD will write ON data into the memory 12-8, and its output will change from low level to high level. If the key is pressed in this state, the output of the MUND game 12-1 can be set to a high level, and the CPU 1 can be operated.

In this way, the keyboard/display on/off memory 12-
If OFF data is written in 8, the CPU 1 cannot be operated even if the key is pressed, but when the on/off switch low 21 in the keyboard 6-2 is turned on, the above memo U-12-8 The data can be rewritten to on data, and the CPU 1 can be operated by pressing the key thereafter.

Further, the output terminal of the keyboard/display on/off memory 12-8 is connected to the keyboard 6-2 via an inverter 12-10.
On/off switch 6-21. Since it is connected to the control input terminal of the display device power control circuit 12-12, when the on/off switch 6-21 is turned on or when ON data is written to the memory 12-8, the display device power control circuit is activated. 12-12 can be driven to operate one display 6-3.

FIG. 6 shows a more detailed example of the display power supply control circuit 12-12. The control input terminal is connected to PI via resistor R1.
P) The above transistor is connected to the transistor q1 base. The collector on page 129 is connected to the base of an NPN transistor Q2 and is grounded via a resistor R4. The base emitters of the transistors Q1 are each connected to the VDDO power supply via resistors R2+R5. The resistors R, , R2 also serve as pull-up resistors for the inverter 12-10. The emitter of transistor Q2 is directly grounded, and its collector is connected to the collector of series transistor Q5 constituting constant voltage circuit 12-121.

The emitter of the transistor Q3 is connected to the display driver 6-2.

If either the on/off switch 6-21 in the keyboard 6-2 or the transistors constituting the inverter 12-10 is turned on, the transistor Q1. Q2 is turned on, and a desired voltage is applied to the display angle driver 6-2 to drive it. Therefore, the display 6-3 is driven by this. In addition, as shown in FIG. If they are configured to be connected to each other, the number of pins can be reduced by one when these are integrated into a circuit, which is advantageous.

As is clear from the above embodiments, the microcomputer device of the present invention controls on/off the power supply line of the CPH.

The configuration is such that power is applied to 0PTJ only when performing the required work, and power is not supplied to the CPH while waiting for instructions, so there is no unnecessary power consumption, resulting in a microcomputer device with extremely low power consumption as a whole. be able to. According to the present invention, a reset signal generation circuit is separately provided, and the output thereof is applied to the reset terminal of the CPH and the control terminal of the switching element inserted in the read/write signal line.
After the power is turned on, the reset is released when its operation is stable, and before the reset is released, even if a write signal is input to the read/write signal line, it will be rejected by the switching element. As a whole, an extremely stable microcomputer device with fewer malfunctions can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the microcomputer device of the present invention, FIG. 2 is a block diagram showing a more specific configuration of the same essential parts, and FIG. 3 is a diagram for explaining the operation of the same essential parts. Figure 4 is a concrete block diagram of the interrupt signal memory that makes up the device, Figure 5 is a concrete block diagram of the timer circuit, and Figure 6 is a concrete diagram of the display power supply control circuit. This is a block diagram. 1...Central processing unit (cpv), 2...
・Address decoding/chip select signal generation circuit, 3
...System RAM, 4...System 110M, 6-1...Display RAM, 5-2
...Display driver, 5-3...
Display device, 6-1...Keyboard scanning gate circuit, 6-11 to 6-18...OR game), 6-2
...Keyboard, 6-21...On
Off switch, 6-3...Keyboard out cover,
Fur, 6-31... Tri-state buff 7
−． 6-32...OR gate, 7...
Clock pulse generation circuit, 8... Power supply, 9...
...Power supply circuit. 10...Timer 0 circuit, 10-1...
Frequency divider, 10-2 to 10-4... Presettable counter. 10-5 to 1o-7...Buffer, 11...
...Reduced voltage detection circuit, 11-1...Voltage detector, 11-2...Memory, 11-3...
...Buffer, 12...Power control circuit, 1
2-1...MND gate, 12-2...
・OR gate, 12-3...Interrupt signal memory, 12-4...NOR gate, 12-6...
...Power on/off memory, 12-6...
・Inverter, 12-7...mND game), 1
2-8... Keyboard display on/off memory, 12-9... Power on/off memory, 12
-10゜12-11... Inverter, 12-1
2...Display power supply control circuit, 12-13...
...Reset signal generation circuit, 12-131...
・・Monostable multivibrator, 12-132・・・・
...NOR gate, 13...Switch circuit, 1
4... Peripheral circuit. Figure 13 Figure 4 Figure 5 1θ IRG diagram

Claims (1)

[Claims] A reset signal generation circuit is constituted by a monostable multivibrator that receives a signal for controlling the power supply line of the central processing unit on and off, and a gate circuit that receives the above signal and the output of the monostable multivibrator as input. , applying the output of the reset signal generation circuit to a reset terminal of the central processing unit, and releasing the reset state of the central processing unit by the output of the reset signal generation circuit when power is applied to the central processing unit; The output of the reset signal generation circuit is simultaneously applied to a switching element provided on the read/write signal line of the central processing unit, so that the write signal can be transmitted to the read/write signal line only when the reset state is released. A microcomputer device characterized in that it is configured as follows.