JPH0283678A - Data processing system developing method - Google Patents

Abstract

PURPOSE:To flexibly and easily respond to the change of the operating specification and the function of a data processing system by writing required data on a nonvolatile storage element included in a logic function block corresponding to a function requested to the system. CONSTITUTION:A single chip microcomputer 1 is constituted of a processor 5, a programmable logic array 6, and an input/output port 7, and respective block is connected with a common bus 8. In the case of necessitating the change of the operating specification or the function of the system on the middle way of a developing process when the data processing system is comprised by setting a semiconductor integrated circuit for data processing including an electrically loadable logic function block or a nonvolatile memory block as a key component, information with respect to the hardware-oriented logic function of the logic function block and the nonvolatile memory block are programmed electrically on the nonvolatile storage element corresponding to their change. In such a way, it is possible to respond to the change of the operating specification or the function of the system.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of configuring a data processing system and furthermore a microcomputer system, and is useful, for example, in responding to modifications to software programs or changes in system functions during system development. It relates to techniques that can be applied and are effective.

[Prior art]

A microcomputer application system constructed on a wiring board has a single-chip microcomputer as a key component consisting of a central processing unit (CPU) and necessary peripheral circuits formed on a single semiconductor substrate, and its control purpose is Depending on the data storage and data visibility.

Furthermore, in order to realize hardware for motor drive and display control, dedicated LSI and even PAL
It is equipped with programmable devices such as (programmable array logic) and PLD (programmable logic device), and TTL circuits.

By the way, when developing such a microcomputer application system, when changing a software program or fixing a bug, it is necessary to modify the memory that holds the program. For single-chip microcomputers that have a built-in memory that is subject to modification or modification of such software programs, it is often necessary to convert the memory into an EPROM and write to it in a manner that can be controlled based on external signal control. 1986
It is disclosed in Japanese Patent No.-198667.

[Problem to be solved by the invention]

By the way, when configuring a microcomputer application system that uses external logic such as PAL, PLD, or TTL circuits as hardware outside the single-chip microcomputer that has the program memory in the form of EPROM, the development If it becomes necessary to modify the hardware due to changes in the operating specifications or functions of the system, we will modify the program of the programmable device as external logic, or
For hardware composed of gate arrays, it is necessary to rebuild the LSI by changing the mask pattern, and also to change the wiring pattern on the wiring board. and response to functional changes will be delayed.

On the other hand, as today's microcomputer application systems become more multifunctional and more compact, the application of data processing LSIs to these systems, such as single-chip microcomputers that incorporate various peripheral functions on-chip, tends to expand. Accordingly, single-chip microcomputers are equipped with various peripheral functions that can be configured as external memory or external logic, such as interface circuits, timers/counters, input/output control circuits, ROM that stores control programs, and even subprocessors. It has come to be built-in. Under these circumstances, when configuring a microcomputer application system in which such a single-chip microcomputer is the key component 1, if it becomes necessary to partially change the operating specifications or functions of the system during the development process, single-chip microcomputers may be used as key components. If the peripheral functions built into a chip microcomputer, especially the hardware-like logic functions, are fixed, the characteristics of a single-chip microcomputer, in which various functional blocks are formed on a single semiconductor substrate, are required to satisfy these requirements. Moreover, it would be necessary to change the entire configuration and mask patterns for manufacturing, making it impossible to quickly and easily respond to changes in system operation specifications and functions during the development of microcomputer application systems. The inventor of the present invention has revealed that there is a problem in that it also inhibits multifunctionalization of single-chip microcomputers.

An object of the present invention is to provide a method for developing a data processing system that can flexibly and easily respond to changes in the operating specifications and functions of the data processing system.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a semiconductor integrated circuit for data processing is formed on a single semiconductor substrate with a logic function block and a CPU block that can realize a required logic function depending on the write state of an electrically writable non-volatile memory element. When constructing a data processing system using circuits, required data is written into the nonvolatile memory elements included in the logic circuit block according to the functions required of the system. At this time, there is a step of rewriting the non-volatile memory element included in the logic function block in accordance with the operational specifications and function changes of the data processing system, or writing a new one with the same structure in which the changed function is reflected in the storage information of the logic circuit block. a step of replacing the semiconductor integrated circuit with a data processing semiconductor integrated circuit; a step of writing a software program in accordance with the functions required of the data processing system into the nonvolatile memory block including an electrically writable nonvolatile memory element; A step of rewriting the non-volatile memory element included in the non-volatile memory block in accordance with a change in the function of the processing system, or a new semiconductor integrated circuit for data processing with the same structure in which the changed function is reflected in the storage information of the non-volatile memory block. A step may be included to replace the circuit.

[For production]

According to the above means, when configuring a data processing system using a data processing semiconductor integrated circuit including an electrically writable logic function block, a non-volatile memory block, etc. as a key component, the operating specifications of the system can be adjusted during the development process. When a change in functionality becomes necessary, such a request can be handled by electrically programming the hardware logical function of the logical function block and the information in the non-volatile memory block into the non-volatile storage element according to the change. A quick and easy response can be taken, and as a result,
The objective is to achieve a data processing system development method that can flexibly and easily respond to changes in system operation specifications and functions.

〔Example〕

FIG. 1 shows a schematic block diagram of a printer controller system which is an embodiment to which the data processing system development method according to the present invention is applied.

Printer controller system shown in the figure]-00
0 controls the mechanical parts of the printer while interfacing with the host computer, and uses a single-chip microcomputer 1 to control, for example, the dots in the printer head 1 to drive the dots according to print data. A driver 10o1, a carriage return motor driver 1002 for moving the printer head in the printing direction, a line feed motor driver 1003 for moving a medium such as paper to be printed, etc. are mounted on one board. The single-chip microcomputer 1 receives print data from a host computer via a Centronics interface or a serial interface, controls the head 1 driver 1001 according to this print data, and prints on a medium.

During printing, the carriage return motor driver 1002 and line feed motor driver 1003 receive outputs from timers included in the single-chip microcomputer 1, position detection signals detected by mechanical parts of the printer, and inputs from panel switches. The drive is controlled based on the information, and the display of required information on the printer panel is controlled as necessary. The print data given to the head driver 1001 is sent to an LSI such as an interface adapter based on the data and address output from the single-chip microcomputer 1.
Alternatively, external position detection signals, panel switch inputs, and even panel display control outputs can be exchanged via an LSI such as an interface adapter. The printer controller system 1000 can also be provided with an expansion RAM that can be accessed by the single-chip microcomputer 1.

Figure 2 shows the single-chip microcomputer 1 mentioned above.
An example is shown. A single-chip microcomputer 1 shown in the figure has a CPU (central processing unit) 2. RAM (random access memory) 3, and ROM (read memory)
(only memory) 4; and a PLA (programmable logic array) 6, which is an example of a logic function block with a variable logic structure. and an input/output port (also simply referred to as Ilo) 7, and each block is connected by a common bus 8. Further, the PLA 6 is directly coupled to l107 and the CPU 2 via signal lines 9 and 10.

The above ROM4 is a single chip microcomputer 1
The PLA 6 is a logical function block for programmably realizing a part of the hardware of the single-chip microcomputer 1.
6 includes an electrically writable non-volatile memory element.

FIG. 3 shows a detailed example of the single-chip microcomputer shown in FIG. 2, centering on the configuration of the PLA 6 described above.

The above PLA6 is an AND (logical product) surface 20. It is composed of circuits such as an OR (logical sum) plane 21, an output latch 22, an input latch 23, and a selector 24, and wiring for connecting the respective circuits. The connection between the processor 5 and the PLA 6 is made by a control signal NIA8a for inputting a signal generated by the processor 5 to the input latch 23 of the PLA6, an address bus 8b, and a data bus 8c. The single-chip microcomputer 1 is interfaced with the outside by an output port door a, an input/output port door b, and an input port door C, which are connected to the data bus 8C. P.L.
The input to the input latch 23 of A6 is the control signal line 8a.
, address bus 8b, data bus 8c, input port c
output cuff 0c and output 9c of the output selector 24, and the output of this input latch 23 is supplied to the AND plane 20.

The output of the AND plane 20 is one input on the OR plane, and one output on the OR plane is given to the output latch 22. The output 22a of the output latch 22 is given to the selector 24, and a part of the signal 22b is input to the AND plane 20. Outputs 9a and 9b of the selector 24 are input to the output port a and the input/output port door b, respectively, and the output 9C is coupled to the data bus 8C.

FIG. 4 shows an example of the AND surface 20.

This AND plane 20 may include non-volatile storage elements for EPROM (Electrically Programmable Read Only Memory) configurations such as, but not limited to, ultraviolet erasable electrically programmable channel injection structures. configured. This AND surface 20 is made by 4 people.
I3) with four independent AND outputs (A, -A3)
). On this AND surface 2o, the nonvolatile memory elements M (0, O) to M (7, 3
) is arranged in a matrix. Here, since the configuration of the nonvolatile memory element itself for the electrically writable EPROM configuration is already known, a detailed explanation thereof will be omitted, but the threshold voltage of the nonvolatile memory element is 1 [V A state at a relatively low level of about 5 [V] is defined as an erase state, and a state at a relatively high level of about 5 [V] is defined as a write state.

Writing to the nonvolatile memory element is performed row by row, 4 bits at a time. That is, the write data is written to the write terminals 00~
D, given one selection line S. -83 is set to a selection level such as high level, the write signal WE is set to high level, and a write voltage (for example, 12.5 [V]) is applied to the write terminal Vp. At this time, crab was added. ~
■Whether to write positive logic or negative logic is determined by the state of 3.

For example, input ■. For example, input ■. When the word line W is set to high level. P is selected and crab enters again. When the word line W is set to low level. n is selected. A resistor Rj (
j=. A write voltage is applied via 7). Write terminals D0 to D.

Voltage converting circuits W, -W3 which receive write data on the data lines d generate drain voltages necessary for writing when the write data level is high level, respectively. −
d. As a result, the nonvolatile memory element whose initial state is the erased state is put into the write state when a word line is selected and high-level write data is applied, and the other nonvolatile memory elements maintain the erased state.

Through such a write operation, the nonvolatile memory elements M (0, O) to M (7,
The program 3) is carried out.

When the programmed AND plane 20 is to perform a logical operation, the power supply voltage (or ground voltage) of the circuit is applied to the write terminal Vp, the write signal WE is set to low level, and the signals 81 to S are applied.

are all at a high level. This allows you to enter the crab.

A word line is selected according to the levels of ~■, and the data line d has a data level corresponding to the programmed state of the nonvolatile memory element whose gate electrode is coupled to the selected word line.

As a result, the sense amplifier 5Ao-'SA outputs an AND output A. -Aj is obtained.

FIG. 5 shows an example of the OR plane 21 included in FIG. 3. This OR surface 21 is a logical product output A. .

OR circuit ORI with two-man power for A1, AND output A2.
OR circuit OR2, OR circuit OR4, where A is powered by two people,
It is composed of an OR circuit OR3 which outputs the output of R2 by two people, an output selection circuit 50 which selects the output of the OR circuit ORI and the OR circuit R3.

When the input signal 51 of the selection circuit 50 is set to high level, the transistor r1 is turned on and the transistor T2 is turned off, and the OR plane 1 is outputted by the logical sum output O8, ○ is obtained.

○、=Ao+A O engineering=A2+A.

Further, when the input signal 51 of the selection circuit 50 is set to a low level, the transistor T1 is turned off and the transistor T2 is turned on, and the OR plane 21 outputs a logical sum of 0 as shown by the following logical formula.゜, O□ is obtained.

Oo ” A o + A x + A x + A
30,=A2+A.

The single-chip microcomputer 1 shown in FIG. 3 can operate in the manner shown in FIG. 6, for example, by switching and controlling the input latch 23 and the selector 24.

The aspect shown in FIG. 6(A) is the input name 2 of FIG.
By selecting the information on the buses 8a to 8c as the inputs of the processor 3 and giving the output of the selector 24 to the ports 7a and 7b, the output of the processor 5 is converted by the PLA 6 and sent to the outside of the single-chip microcomputer 1. This is what is output.

In the embodiment shown in FIG. 6(B), the outputs of the boats 7b and 7c are selected as inputs to the input latch 23, and the selector 24
By selecting the output 9c as the output of the single-chip microcomputer 1, a signal applied from the outside of the single-chip microcomputer 1 is converted by the PLA 6 and is applied to the processor 5.

In the embodiment shown in FIG. 6(C), information on buses 88 to 8c is selected as input to the input latch 23.

By supplying the output of the selector 24 to the bus 8c, the output of the processor 5 is converted by the PLA 6 and returned to the processor 5 again.

In the embodiment shown in FIG. 6(D), the outputs of ports h7b and 7c are selected as inputs of the input latch 23, and the selector 24
By selecting outputs 9a and 9b as the outputs of PLA,
6, the data is converted and output again to the outside of the single-chip microcomputer 1.

Note that the embodiments shown in FIGS. 6(A) to 6(D) above are
It is also possible to combine two or more. For example, in the combination of the embodiments shown in FIGS. 6(A) and (B) above, PLA6
divides the input of the
C), the other is external human power (7b, 7c), and PL
The output of A6 is also divided, and one side is connected to the input of processor 5 (8
c).

The other can also be output to the outside (7a, 7b).

When configuring the printer controller system 1000 using the single-chip microcomputer 1 described above, the printer controller system 100o will be The logical configuration, ie, the program state for the nonvolatile memory element, is determined depending on the required function. By enclosing the single-chip microcomputer 1 in a package with a window, erasing the stored information by irradiating ultraviolet rays through the window, and then electrically rewriting new logic information, the hardware in the single-chip microcomputer 1 can be changed. P plays a part
It becomes possible to change the logic of L A 6 and correct errors on the single-chip microcomputer 1, and the single-chip microcomputer 1 can flexibly respond to changes in the operational specifications and functions of the printer controller system 1000. It becomes like this. Furthermore, the single-chip microcomputer 1 can be used repeatedly for such changes. If the microcomputer is not packaged in a windowed package, it can be replaced with a new single-chip microcomputer with the same structure but with the necessary logical information.

The non-volatile memory element of PLA6 is an electrically programmable and erasable MNOS (Metal Nyride Oxide Semiconductor) or a floating gate type E.
EI) A non-volatile memory element P for ROM (Electrically Erasable and Programmable Read Only Memory) configuration can also be used.

Next, a single-chip microcomputer constructed by adding a programmable logic circuit having a processor structure, that is, a subprocessor, as a logic function block with a variable logic structure will be described. As shown in FIG. 7, this single-chip microcomputer 1 is constructed by adding a sub-processor 100 connected to the common bus 8, PLA 6, and 1107 to the configuration shown in FIG.

FIG. 8 shows an example of the configuration of the sub-processor 100 and the sub-processor 100. The connection relationship between the PLA 6, l107, and common bus 8 is shown.

The sub-processor 100 is a ROM for storing instructions.
101, a control circuit 1.02 for generating a control signal based on the information stored in this ROM 101, ROM 10
Address latch 103.L holding the next address for accessing L. ALU (
arithmetic logic unit) 107, register file 10
8. PSG (Programmable Sequential Generator) 109, ST controlled by this PSG 109
R (Status Register) 110. The above sub-processor]-〇〇 is constituted by a BIF (bus interface circuit) 111 for connecting the common bus 8.

The PLA 6 is connected to the common bus 8 by a wiring 112a and to the common bus 1107 by a wiring 112b, and is connected to a control signal 102a generated by the control circuit 102 of the sub-processor 100 by a wiring 112c to a wiring 112d.
The signal 107a is input to the output 110a of the status register 110 and from l107 to the ALU 107.
are connected to each.

The PSGLO9, ROM10I, and PLA6 are constructed of electrically writable nonvolatile memory elements as described above. Therefore, even in the single-chip microcomputer 1 shown in FIG.
The nonvolatile memory elements included in G109, ROM 101, and PLA6 are part of printer controller system 100.
Its logical configuration is determined according to the functions required for the 0.

Then, after erasing the stored information by irradiating ultraviolet rays through the window formed in the package of the single-chip microcomputer 1, new logic information is electrically rewritten, and the hardware and logic in the single-chip microcomputer 1 are erased. PLA6, which plays a part of the function.
It becomes possible to change the logic and correct errors in the PSG 109° ROM 101, etc., and the single-chip microcomputer 1 can flexibly respond to changes in the specifications and functions of the printer controller system 100o.

FIG. 9 shows an example of a single-chip microcomputer 1 in which the ROM 4 for storing a software program inside the chip is converted into an EPROM.

In Figure 9, single-chip microcomputer 1
is a CPU 2, a ROM 4 (hereinafter simply referred to as this ROM) such as an EPROM as an electrically writable non-volatile memory block for storing software programs.
M4 is also referred to as a nonvolatile memory block 4), a control signal generation circuit 500, and a programmable logic circuit 900 that constitutes the sub-processor, PLA, etc., and other functional modules. The CPU 2, nonvolatile memory block 4, programmable logic circuit 900, etc. are connected to an address bus 41 and a data bus 42.

In particular, a switch element 61 is interposed between the address bus 41 and the CPU 2, a switch element 62 is interposed between the data bus 42 and the CPU 2, and a switch element 63 is interposed between the nonvolatile memory block 4 and the data bus 42. , and a switch element 63 is interposed between the programmable logic circuit 900 and the data bus 42. address bus 4
1 is connected to the single-chip microcomputer 1 by a signal line 519 via a 3-state driver 72 that functions as an output sofa, an inverter 82 and a 3-state inverter 65 that function as an input sofa.
It is possible to interface with the outside world. Similarly, the data bus 42 is interfaced with the outside of the single-chip microcomputer 1 by a signal 5518 via the 3-stage 1 to driver 71 that function as output buffers, and the inverter 81 and 3-state inverter 64 that function as input buffers. is made possible.

The control signal generation circuit 500 is supplied with control signals 5101 to 5104 for data transfer control from the CPU 2, and control signals 5111 and 5104 for instructing the operation mode of the single-chip microcomputer 1.
121, 513, and 5122 are given from outside the single-chip microcomputer 1. The control signal generation circuit 500 to which such various signals are applied is connected to the CPU 2°, the nonvolatile memory block 4. Programmable logic circuit 9
Control signals 520 to 528 are generated to control data transfer timing between 00 and data bus 42, address bus 41°, and signal lines 518 and 519. Note that the signal 5 output from the control signal generation circuit 5°O to the outside
], 4,515 are signals indicating external read cycles and write cycles, and the nonvolatile memory block 4 and programmable logic circuit 900 have high voltage signals necessary for writing to the nonvolatile memory elements included therein. Signal line 516 for commonly applying voltage etc. from the outside
are combined.

In the single-chip microcomputer 1 shown in FIG.
The nonvolatile memory block 4 and the programmable logic circuit 900, which are commonly connected to each other, are arranged in the same address space. Therefore, no special processing or circuit configuration is required to switch the address space when writing to the nonvolatile memory block 4 and the programmable logic circuit 900, and by specifying the addresses assigned to each, the same control can be achieved. Alternatively, write and verify processing can be easily performed on required nonvolatile memory elements included therein using the same sequence. As a result, a common writing device can be used, and even when using the built-in CPU 2, writing and verify processing can be performed in the same sequence.

FIG. 10 shows a control signal generation circuit 500 shown in FIG.
An example is shown. Although this control signal generation circuit 500 is not particularly limited, the AND plane 51 and the ORRb2O are nitrated. This AND1 eyebrow 51 has six vertical signal lines each serving as an AND output signal line, and a horizontal signal corresponding to the intersection point indicated by a circle among the horizontal signal lines that intersect with the vertical signal line. The result of performing logical product on the line inputs is the corresponding logical product output. For example, if all the inputs on the horizontal signal lines marked with a circle that intersect with the vertical logical product output signal line are at high level. In a certain case, the output of the corresponding vertical AND output signal line is set to high level. 6 on the AND side
The logical product output signal line of this book is set as the ORRb2O input, and the horizontal logical sum output signal line that intersects with the six vertical input signal lines.

The result of ORing the inputs of the vertical input signal lines corresponding to the intersections indicated by ○ marks is the OR output.1For example, it is indicated by the O mark that intersects with the horizontal OR output signal lines. If even one input to the vertical input signal line is at high level, the output from the corresponding horizontal OR output signal line is set to high level.

When the control signal 513 applied from the outside is at a low level, the AND output signal lines 5291.5292.5293.5296 which receive the inverted signal 5131 at the intersection of the O marks are connected to the control signals 5101 to 5104 output from the CPU 2.
A logical AND output is obtained that makes the level of . In this state, control signals 5101 (TRI), 5104 (E
xtM) is at a high level, the AND output signal line 529
1 becomes high level and external device read mode is set. In this operating mode, the control signal 514 (TR3) indicating an external read cycle is asserted to a high level, and the control signals 520 .
527.528 are also asserted high. The high-level control signal 520 controls the switch element 61 to be in the ON state, and the high-level control signal 528 controls the 3-state driver 72 to enable output operation.
The address signal output from PU2 is the address bus 41.
and is output to the outside via a signal line 519.

Data output by an external accessed module (not shown) in response to the address signal and control signal 514 is externally applied to the signal line 518 and is also supplied from the three-state inverter 64 turned on by the high-level control signal 527. It is applied to the data bus 42 and read into the CPU 2.

In this external device read mode, the control signal 52
4 is set to low level, the data fetched from the outside to the data bus 42 is transferred to the nonvolatile memory block 4.
and the operation of the programmable logic circuit 900.

When the control signal 513 is at a low level, the control signal 51
When 02 (TWO,) and 5104 (ExtM) are set to high level, the output signal l1t5292 becomes high level and external device write mode is set. In this operation mode, the control signal 515 (TW3), which means a write cycle to the outside, is asserted to high level and the control signals 520, 521 .
526.528 is also asserted high. As a result, the address signal output from the CPU 2 is outputted to the outside via the switch element 61 which is turned on in the same manner as described above, the 3-state driver 72 which is controlled to enable output operation, and the signal line 519, and is also output from the CPU 2 to the outside. The hot weather data output from the switch element 62, which is turned on by the high-level control signal 521, and the data bus 42.
It is applied to the outside via the 3-state driver 71 controlled to be able to output by a high-level control signal 526 and the signal line 518, thereby writing to an external accessed module.

When the control signal 513 is low level, the control signal 510
1 (TRI) and 5103 (IntM) are at high level, the output signal line 5293 becomes high level and the internal device read mode is set. In this operating mode, the control signals 520.522 (TR,),
524 is asserted high. This allows C.P.
The address signal output from U2 is applied to the address bus 41 via the switch element 61, and is used as the address signal 426 of the nonvolatile memory block 4 or the address signal 5172 of the programmable logic circuit 900. At the same time, the control signal 522 instructs the nonvolatile memory block 4 and the programmable logic circuit 900 to perform a read operation. At this time, since the nonvolatile memory block 4 and the programmable logic circuit 900 are arranged in the same linear address space, even if an address signal is given to both, only one of them reads data according to that address signal. The output data is applied to the data bus 42 via either switch element 63 or 66. The CPU 2 reads the data outputted to the data bus 42 in this way from the signal line 423.

When the control signal 513 is low level, the control signal 510
2 (TWl,) and 5103 (Int, M) are at high level, the output signal line 5296 is at high level, and the internal device write mode is set. In this operating mode, the control signals 520, 521, 523
(TW4) is asserted to high level. As a result, the address signal output from the CPU 2 is applied to the address bus 41 via the switch element 6], and the write data output from the CPU 2 is applied to the data bus 42 via the switch element p62. Further, programmable logic circuit 900 is instructed to perform a write operation. As a result, data is loaded into the required address of the programmable logic circuit 900 specified by the address signal.

On the other hand, when the control signal 513 is at a high level, the AND output signal 152 receives its inverted signal 5131 at the intersection of the circles.
91.5292.5293.5296 are negated to low level regardless of the levels of control signals 5101 to 5104 output from the CPU 2, so that the control signals 520 and 521 are always controlled to low level, and the CPU
2 to output data and addresses to the data bus 42 and address bus 41 is substantially disabled. That is, the CPU 2 is disconnected from the address bus 41 and data bus 42. In this state, the control signal 5121 (TR
2) is set to high level, the AND output signal line 529
4 becomes high level, and a read mode based on external access is set. This operating mode is EPROM
It is used for desl-reading for verification after writing by a writer or the like. In this operating mode, control signals 522 (TR4), 524, 525
．． 526 is set to high level and asserted to 1. As a result, the address signal supplied from the outside to the signal line 519 is
The address signal is applied to the address bus 41 via the 3-state inverter 65 controlled to be operable by the control signal 525, and this address signal is sent to the nonvolatile memory block 4 from the address bus 41 via signal lines 426 and 5172.
and to programmable logic circuit 900. Nonvolatile memory block 4 and programmable logic circuit 90
0, the read operation is instructed by the control signal 522, and the nonvolatile memory block 4 is read by the control signal 524.
and a data output terminal of programmable logic circuit 900 are connected to data bus 41. Therefore, when either the nonvolatile memory block 4 or the programmable logic circuit 900 performs a read operation in response to an address signal supplied from the outside, the required data to be read is provided to the data bus 42. The read data given to the data bus 42 is transmitted to the 3-state driver 71 which is controlled to be able to output by a high-level control signal 526.
The signal is applied to the signal line 518 via the signal line 518 and read out to the outside.

When the control signal 513 is at high level, the control signal 5122
(TW2) is set to high level, the output signal line 52
95 becomes high level, and a write mode based on external access is set.

This operating mode is used when writing by an EPROM writer. In this operating mode, control signals 525 and 527 are asserted to a high level. As a result, the address signal supplied from the outside to the signal line 519 is supplied to the address bus 41 via the 3-state inverter 65 which is controlled to be operable by the control signal 525, and this address signal is supplied from the address bus 41 to the address bus 41. It is applied to the nonvolatile memory block 4 and the programmable logic circuit 900 via signal lines 426 and 5171.

Further, data supplied from the outside to the signal line 518 is supplied to the data bus 42 via the 3-state inverter 64 controlled to be operable by the control signal 527, and this data is transferred from the data bus 42 to the signal line 424. and 5
171 to nonvolatile memory block 4 and programmable logic circuit 900. When a high voltage for writing is applied from the external terminal to the signal line 516 in this state, the write data is written to the nonvolatile memory element at a predetermined address of the nonvolatile memory block 4 or programmable logic circuit 900 specified by the address signal. written. The write high voltage is set to be a voltage sufficient for a write operation of about 10 to 25 [V] corresponding to a single memory LSI such as an EPROM.

In addition, when the nonvolatile memory block 4 and the programmable logic circuit 900 are configured with an electrically writable and erasable nonvolatile memory element for EEPROM configuration,
Erasing and writing voltages may be applied via the signal line 516, or the writing voltage and erasing voltage may be generated by an internal booster circuit.

In the single-chip microcomputer 1 shown in FIG. 9 as well, the nonvolatile memory block 4 and the nonvolatile memory elements of the programmable logic circuit 900 included therein are adjusted according to the operational specifications and functions required of the printer control system 1000. A logical configuration is determined. After erasing the stored information by irradiating ultraviolet rays through the window formed in the package of the single-chip microcomputer 1, a part of the hardware in the single-chip microcomputer 1 can be erased by electrically rewriting new logic information. Programmable logic circuit 90
It is now possible to change the logic of 0, correct errors, change the program stored in the non-volatile memory block 4, and correct bugs. You will be able to respond flexibly. If the microcomputer is not enclosed in a windowed package, it can be replaced with a new single-chip microcomputer with the necessary logical information written in it.

A detailed example of the programmable logic circuit 900 is illustrated in FIG. 1-1.

In FIG. 11, 91 is a NOR array including nonvolatile memory elements, 961 to 963 are logic modules, and 94
61 to 9463 are selectors, 9433 is a sense amplifier,
9434 is a write circuit, 9431.9432 is an address decoder, 941 is a data register, 942 is an at 1
Nos register 9435 is a multiplexer.

''The second logic module 961 includes a NOR gate 922, a flip-flop 921, selectors 923 and 924, an output driver 925. It is composed of AND gates 926 and 927. The NOR array 91 has a logical configuration according to write program states for a plurality of nonvolatile memory elements included therein.

You can take it. The logic modules 961 to 963 are
The logic of the signal output according to the logic configuration of the NOR array 91 is further changed programmably according to the selection operating conditions of the selectors 923 and 924 and the state of the flip-flop 921.
1 constitutes a variable structure logic. logic module 96
1 to 963 can be indirectly interfaced with the data bus 42 and address bus 41 via signal lines 5171 to 5173, and can also interface with the outside of the single chip microcomputer 1 via terminals 991 to 993. can be input and output. When the control signal 513 is at a low level, the data input/output target is the flip-flop 921 inside the logic modules 961 to 963, and when the control signal 513 is at a high level, the NOR logic of the NOR array 91 is input/outputted. It is possible to write to and read from the nonvolatile memory elements that constitute the .

When the control signal 513 is set to low level and the internal device read mode is set, the address signal output from CI) U2 is transferred from the address bus 111 to the signal line 5.
172. After this address signal is set in the 71-less register 942, it is supplied to the address decoder 9432 via AND gates 1 to 951, and is decoded by the address decoder 9432. This address decoder 9432 forms a selection signal for selecting one of the logic modules 961 to 963 in response to a manual address signal. Note that the selection level is set to high level. Output selection signal 5 of address decoder 9432
310 is provided to an AND gate 926 of the logic module. The A and ND gates 926 are also supplied with the control signal 522 at a high level in the relevant operation mode. From this AND gate 926, the selector 92
3. Flip-flop 92 via output driver 925
1 data is output, and this output data is sent to the signal line 531.
1, is read out from the signal line 5173 to the data bus 42 through the selector 9435.

When the control signal 513 is set to low level and the internal device write mode is set, the address signal output from the CPU 2 is sent to the signal line 5172, and the data is sent to the signal line 5171! I can get it. This results in
Data is provided to the logic module AN1 gates 1-927 via AN1) gates 95;3. This AND gate 927 is supplied with the control signal 523 at a high level in the relevant operation mode, and is also supplied with a selection signal from the address decoder 9432 in accordance with the decoding result of the address signal. Therefore, the flip-flop 9 specified by that address signal
The output data of the CPU 2 can be written into the memory 21.

When the control signal 513 is set to a high level and a write mode based on external access is set, the output of the address register 942 is sent to the address decoder 943 via the gate 952. 9431 performs NOR according to the input address signal.
One of word lines 986-989 of array 91 is selected. The data given to the signal line 5171 from the CPU 2 is set in the data register 941, and the data is input to the AND gate +-.
954 to the write circuit 9434. Write data is applied to selectors 9461 to 9463 in synchronization with the timing at which a write high voltage is applied from the outside. The selector selection signal 5312 of the address decoder 9431 is applied to the bit line 981 according to the input address signal.
985 is selected, write data is applied to the selected bit line, and thereby writing to the nonvolatile memory element is performed. At this time, the selector 924 inside the logic module has its output controlled to a high impedance state by the signal 513, thereby causing the word IV! This prevents undesired signals from being mixed into 986-989.

When the control signal 513 is set to a high level to set a read mode based on external access, the bit line data of the NOR array 91 specified by the address decoder 9431 is transferred to the selector 94, similarly to the write mode.
61 to 9463 to the sense amplifier 9433, and the signal 41A51.73 is supplied to the sense amplifier 9433 via the selector 9435.
is read out.

As described above, when the control signal 5]3 applied from the outside is at a low level, data is input/output to and from the flip-flops 921 inside the logic modules 961 to 963.
Furthermore, when the control signal 513 is at a high level, writing and reading are performed based on external access to the NOR array 91 made up of nonvolatile storage elements. If a nonvolatile memory element that can be electrically written to and erased is used in the NOR array 91, an erasing operation can also be performed with the same circuit configuration as writing by adding an erasing circuit.

Note that even if the configuration of the programmable logic circuit 900 changes, for example, if there are multiple NOR arrays 91, if the internal logic structure of the logic modules 961 to 963 differs, if the number of flip-flops 921 differs, or if the logic module Signal line 9 from 961 to 963 to external terminal
Even in the case where 91 to 993 do not exist, a configuration similar to this embodiment can be adopted to enable access from the CPU 2 of the single-chip microcomputer and external terminals.

According to the above explanation, the programmable logic circuit 90 of the single-chip microcomputer 1 shown in FIG.
0 includes PLA6 in FIG. 4 and subprocessor 1 in FIG.
00, and the circuit shown in FIG. 11 can be included as a logic function block as a variable logic structure, but this programmable logic circuit 900 and nonvolatile memory block 4 may be linearly arranged in the same address space, although this is not particularly limited. can be placed in

FIG. 12 shows an example of an address mapping state between the programmable logic circuit 900 and the nonvolatile memory block 4 in the same address space. According to FIG. 12, the nonvolatile memory block 4 contains 0OOOH to 3
Addresses up to F F F H are assigned, and the programmable logic circuit 90o has addresses from 4000H to 7FFFH.
*(7) 7 dresses are assigned. By arranging the programmable logic circuit 900 and the nonvolatile memory block 4 in the same address space in this way, writing and test reading can be performed by giving different addresses to both from outside the single-chip microcomputer 1. It can be carried out.

In addition, by making the addresses, data, control signals, timing, etc. necessary for writing and test reading for verification almost the same as standard single EPROMs, in other words, single EPROMs and EE PROMs
By adapting to the general specifications of a writing device such as an EPROM writer for programming, it becomes possible to perform writing and verify processing using the general-purpose writing device as is. and.

When the control signal 513 is set to high level to set the write/read mode by external access,
Address bus 41 and data bus 42 to which programmable logic circuit 900 and nonvolatile memory block 4 are commonly connected are separated from CPU 2 by gates such as switch elements 61 and 62. In the operating mode, the single-chip microcomputer 1
is functionally a non-volatile memory L like a single EPROM.
Looks similar to SI. In other words, 1”:PROM
The writer will now see an external terminal that can interface with this.

FIG. 13 shows a timing chart necessary for data writing and test reading for verification.

A general-purpose EPROM writer for writing and test reading to an electrically writable non-volatile semiconductor memory device such as an EPROM is equipped with a power supply voltage Vcc, an address signal, and an output I-- which instructs data input/output direction, although it is not particularly limited. It outputs an enable signal OE, a write high voltage Vpp, and a chip enable signal CE for instructing chip selection/non-selection, and also inputs read data and outputs write data. Such E
In the PROM writer, during write operation, the error 1
The chip enable signal OE is at high level, the chip enable signal CE is at low level, and the write voltage VP
The output terminal of P is set to a high voltage such as 12.5 [V]. On the other hand, during test read for verification, the output enable signal OE is at low level, the chip enable signal CE is at low level, and the write voltage V
The output terminal of PP is set to a voltage of about 5 [V] corresponding to the power supply voltage Vcc.

Such an EPROM writer and the single-chip microcomputer 1 as shown in FIG. electrically coupled.

For example, with this adapter, the chip enable signal CE
The inverted signal of output enable signal OE is given as the control signal 513 shown in FIG. 9, the write voltage Vpp or the power supply voltage Vcc is selectively supplied to the signal line 516 of FIG. Control signal 51 in the figure
As 21, this output enable signal ○E
is given as control signal 5122 in FIG. 9, and an address signal is given to signal line 519 in FIG. And EP
The data input/output terminal of the ROM writer is the signal line 51 in Figure 9.
Furthermore, the electric voltage Vcc is applied to a power supply terminal (not shown) of the single-chip microcomputer 1. Furthermore, if the control signal generation circuit 500 is configured such that the control signal 5121 is converted into an inverted level signal of the control signal 5122 by an inverter (not shown) and only the control signal 5122 is directly applied from an external terminal, the external terminal The output enable signal OE can be directly applied to the output enable signal OE. Alternatively, the power supply voltage Vcc on the adapter is applied as a high-level control signal 513, and the result of performing NOR logic on the adapter on the output enable signal OE and the chip enable signal CE is set as the control signal 5121, and the output enable signal 5121 is set as the control signal 5121. It is also possible to apply NOR logic on the adapter to the inverted level of the signal OE and the chip enable signal CE, and provide the result to the single-chip microcomputer as the control signal 5122, and the other connection relationships can be the same as described above.

In this way, the single-chip microcomputer 1 can be
When a power supply voltage Vcc of about 5V is applied to the single-chip microcomputer 1 while connected to a PROM writer, the single-chip microcomputer 1 becomes operational.

After that, the address information of the address to be written to the nonvolatile memory block 4 or the programmable logic circuit 900 is output from the EPROM writer, and the output enable signal OE remains negated at a high level and the voltage of about 12 [V] is output. Write high voltage VPP is output, and chip enable signal CE is asserted to low level. As a result, writing of data to the required nonvolatile memory element selected by the address information is started. The period during which the chip enable signal CE is asserted to a low level is determined by the characteristics of the nonvolatile memory element for the EPROM configuration, and is, for example, about 1 m5ec. When the chip enable signal CE is negated to a high level, the write voltage VPP supplied to the signal line 516 of the single-chip microcomputer 1 decreases.
The write mode is ended by returning the voltage to the power supply voltage vcc.

When the output enable signal ○E is asserted to low level and the chip enable signal CE is asserted to low level while the address signal used for writing is output, the data in the nonvolatile memory element selected by the address signal is It is output from the single-chip microcomputer 1. By determining whether the read data matches the write data, a verify process is performed to determine whether data has been correctly written by the write operation.

When the necessary data is written and verified in this way, the single-chip microcomputer 1 becomes able to execute data processing depending on the logic achieved by the written state.

Figure 14 shows a CPU that uses microprogram control.
An example of a single-chip microcomputer including 2 is shown.

In the single-chip microcomputer shown in FIG.
A single semiconductor substrate includes an OM (also referred to as OM) 600 and an EPROM 624 for storing an operation program consisting of a plurality of macro instructions.

The micro EPROM600 included in CPU 2 is
A signal line 653 is connected to the address bus 41 and the data bus 42,
Signal lines 651 and 650 are connected to the write circuit 601 connected to address bus 41 and data bus 42 by 652.
and the instruction fetch circuit 602 connected to the data bus 42, and furthermore, during the instruction control operation, the micro E
It is connected to a read circuit 604 for reading microinstructions of the F R0M 600. Readout circuit (504
The microinstructions outputted from the control circuit 607 are supplied to the control circuit 607 and decoded, and the control signals generated thereby control the operations of the arithmetic circuit 605, the instruction fetch circuit 602, the address generation circuit 606, and the like. The address generation circuit 606 supplies the address of the macro instruction to the address bus 41 via a signal line 648. This CPU
2 is operated in synchronization with the tarlock signal φ.

The non-volatile memory blocks 4 each have an address bus 41,
It is composed of a read circuit 621 connected to the data bus 42, a write circuit 622, a test read circuit 623, and an E I ROM 624 connected thereto.

Further, the readout circuit 621 is also connected to the control circuit 607 of the processor 2 . 71 to response bus 4] and data bus 42 are connected to i! by the tarlock signal φ. The address bus 41 is connected to a bus precharge circuit 671 which is controlled by signal lines 654 and 655, and is further interfaced with the outside of the single-chip microcomputer via a signal line 612, an input circuit 608, and a signal line 611.

Further, the data bus 42 includes signal lines G-1-4, input/output circuits 609. It is also possible to interface with the outside of the single-chip microcomputer via a signal line 61;3.

Outputs 630 to 639 of the control signal generation circuit 500 connected to the external control signal line 61.0 are used for command control operation, micro EPROM 600, EPROM
In order to control writing to 624 and test operations, it is connected to each of the above circuits.

Writing to the micro EPROM 600 is set by applying a write mode signal to the control signal input line 6]0, and in this state, the control signal generation circuit 500
Of the outputs 630 to 639, only the control signal 636 of the write circuit 601, the control signal 638 of the input circuit 608, and the control signal 639 of the input/output circuit 609 are enabled, and the other signals are controlled to a negated state. That is, C
P1. Output from J 2, nonvolatile memory block 4, and bus precharge circuit 671 to data bus 42 and address bus 41 is prohibited, and each of the above buses 41.42
micro IEP RO via the input circuit 601
Used only for writing to M600. Input circuit 60
Micro E P ROM600 is connected to the external connection line 611 of 8.
The external connection line 613 of the input/output circuit 609, which is controlled in the input direction, is provided with address information for selecting a desired element from a group of nonvolatile memory elements constituting the memory element. Write data is applied to the control input line 610, and a write signal is applied to the control input line 610. As a result, required microinstruction information is written to the predetermined address of the micro EPROM 600 specified by the external address signal.

For test 1, whether or not the write operation was performed correctly.

This is performed by applying a mode signal for reading from the micro EPROM 600 to the control input line 610. When the operation mode is set, the outputs of the control signal generation circuit 500 (330 to (); among 39, the control signal 11 of the test readout circuit 603 635, the control signal 638 of the input circuit 608, and the control signal 638 of the input/output circuit 609) Control signal 639 becomes valid.

As a result, an address signal is applied to the external input line 611, and the micro IEP r<0 is applied to the control input line 6]-〇.
When a mode signal for reading the test of M600 is given, the input/output circuit 609 is controlled in the output direction,
The read data of the selected micro EPROM 600 is output to the external connection line 613 via the test read circuit 603, connection line 650, data bus 42, connection line 614° input/output circuit 609. This allows verification externally.

Nonvolatile memory element group 624 of nonvolatile memory block 4
Similarly to the writing and test reading of the micro EPROM 600, the writing circuit 622, the test reading circuit 623, and the input circuit 6 are controlled by the control signal from the control signal generation circuit 500.
08 and the input/output circuit 609.

The operation of the semiconductor integrated circuit in the normal mode, that is, during instruction control operation, is performed in synchronization with the clock φ, for example, as follows. When the address information generated by the address generation circuit 606 of the CPU 2 is sent to the read circuit 621 of the nonvolatile memory block 4 via the address bus 41, the C
A predetermined macro instruction is read from the nonvolatile memory element group 624 based on a signal on the read signal line 671 from the control circuit 607 of the PU 2, and is fetched into the instruction fetch circuit 602 via the data bus 42. Instruction fetch circuit 6
The information held in 02 is micro EPROM600
micro EPROM60 based on that information.
0 is addressed and the microinstruction is read into read circuit 604 accordingly.

This read information is used as control information inside the CPU 2, etc. The microinstruction read out by the readout circuit 604 is input to the control circuit 607 and decoded, and based on this, the arithmetic circuit 605, address generation circuit 606, instruction fetch circuit 602, memory readout circuit 621, etc. are controlled. In addition, in such an instruction control operation, the data bus 42 and address bus 41 are precharged by a bus precharge circuit 671 that operates in synchronization with the clock signal φ, and a series of operations of the single-chip microcomputer is supplied to the CPU 2. It is synchronized with the clock signal φ. Test readout circuit 603 of the CPU2
The number of parallel output bits of the readout circuit 604 and the test readout circuit 604 do not need to be equal.
The number of parallel output bits from the data bus 42 is equal to the number of pins on the data bus 42.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, the configuration of a logic function block that can realize a required logic function depending on the write state of an electrically writable nonvolatile memory element, the configuration of a nonvolatile memory block for storing a software program, and the configuration of a nonvolatile memory block that is included therein. The configuration of the electrically writable nonvolatile memory element and the processing details for writing data thereto are not limited to the above embodiments and can be modified as appropriate.

Furthermore, the semiconductor integrated circuit for data processing, such as the single-chip microcomputer that includes an electrically writable nonvolatile memory element for the EPROM configuration applied to the above embodiment, is not necessarily packaged in a windowed package that can erase information with ultraviolet light. The information is not limited to those enclosed in a ``book'', and may be of a format that allows writing only once. In this case, if you use a single-chip microcomputer with the exact same structure, write new information into it, and install it in the system, a single-chip microcomputer with the same structure will be able to handle changes in operating specifications and functions during system development. can be dealt with.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the development of a printer controller system, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, and can be applied to the development of various data processing systems such as microcomputer application systems.

The present invention can be applied to conditions in which a data processing semiconductor integrated circuit having at least an electrically writable logic function block and a nonvolatile memory block is used.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, a logic function block that can realize a required logic function depending on the writing state of an electrically writable nonvolatile memory element, a nonvolatile memory block that includes an electrically writable nonvolatile memory element, and a CPU.
When configuring a data processing system using a semiconductor integrated circuit for data processing in which blocks are formed on a single semiconductor substrate, the required functions of the logic circuit block are By performing the steps of writing data to the non-volatile memory block or writing the required software programs to the non-volatile memory block, changes to the operating specifications or functionality of the data processing system may become necessary during the development of the data processing system. This has the advantage of being able to respond quickly and easily to requests, as well as being able to respond flexibly.

Nowadays, there is a tendency for various peripheral functions to be integrated into on-chip semiconductor integrated circuits for data processing, which are considered to be the key components of data processing systems, and the operating specifications and functions of data processing systems are subject to change. It is expected that more and more circuit parts will be included in the data processing semiconductor integrated circuit. Under such circumstances, if the step of writing to the logic circuit block, which is a programmable logic structure built into the data processing semiconductor integrated circuit, is executed to deal with changes in the operating specifications and functions of the system, key components and There are relatively few changes to be made to the LSI and circuits provided outside the data processing semiconductor integrated circuit, which can greatly contribute to shortening the development time and cost of data processing systems. effective.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a printer controller system that is an example of applying the data processing system development method according to the present invention, and FIG. 2 is a block diagram showing an example of a single-chip microcomputer included in the printer controller system. , FIG. 3 is a block diagram of another single-chip microcomputer centered on the configuration of PI and A, which are examples of logical function blocks. FIG. 4 is a circuit diagram showing an example of the AND surface in the PLA of FIG. 3, FIG. 5 is a circuit diagram showing an example of the OR surface of the PLA of FIG. 3, and FIGS. D) is an explanatory diagram of the operation mode when focusing on PLA and Ilo in the single-chip microcomputer shown in FIG. 3, and FIG. 7 is a block diagram of a single-chip microcomputer equipped with a sub-processor, which is an example of a logical function block. . FIG. 8 is a block diagram showing an example of the subprocessor shown in FIG. 7, and FIG. 9 is a block diagram showing an example of the subprocessor shown in FIG.
A block diagram of a single-chip microcomputer equipped with an M program memory, FIG. 10 is a logic diagram showing an example of a control signal generation circuit included in the single-chip microcomputer shown in FIG. 9, and FIG. 11 shows logic functions. FIG. 12 is an explanatory diagram showing an example of the address mapping state of the logical function block and non-volatile memory block; FIG. 13 is a block diagram showing another example of the block; FIG. 5 is a timing chart showing an example of the timing required for writing data to the included logical function blocks and nonvolatile memory blocks and reading data to the test I for verification. FIG. 14 is a block diagram showing an example of a single-chip microcomputer that employs microprogram control. 1... Single-chip microcomputer, 2...
CPU, 4...Nonvolatile memory block, 5...Processor, 6-PLA, 7 (7a, 7b, 7c)-I
/ O120・A N D plane, 2], -OR plane, 4
]...Address bus, 42...Data bus, 91.N
OR array, 500... Control signal generation logic, 900, Programmable logic circuit, 1000... Printer controller 1~
〇-La System, 1001.../\Rad Driver, 10
02... Carriage return motor driver 1003...
...Line feed motor driver. Figure Figure AOA+ 2A3 Figure Figure (C) (D) Figure Figure 41 Atrusno ＼・Z Figure Figure O Figure 2111-11111 52θr

Claims (1)

[Claims] 1. A logic function block that can realize a required logic function depending on the state of writing to an electrically writable nonvolatile memory element, and a logic that uses this logic function block to execute a logic operation. A data processing system is developed using a data processing semiconductor integrated circuit formed by forming an operation control block on one semiconductor substrate, and one or more controlled circuit blocks controlled by the data processing semiconductor integrated circuit. A method for developing a data processing system, comprising writing required data into a nonvolatile memory element included in the logical function block according to a function required of the system. 2. Development of the data processing system according to claim 1, further comprising the step of erasing information in the nonvolatile memory element before writing data corresponding to a change in the function of the data processing system to the nonvolatile memory element included in the logical function block. Method. 3. Replacing the data processing semiconductor integrated circuit in accordance with the functional change of the data processing system with a new data processing semiconductor integrated circuit in which data corresponding to the functional change is written into the nonvolatile memory element of the logical function block. The method for developing a data processing system according to claim 1, comprising: 4. The data processing semiconductor integrated circuit includes a nonvolatile memory block including an electrically writable nonvolatile memory element, and the nonvolatile memory block is provided with the above logic operation control according to the functions required of the data processing system. A method for developing a data processing system according to any one of claims 1 to 3, comprising the step of writing a software program for the block. 5. The data processing system according to claim 4, further comprising the step of erasing information in the nonvolatile memory element before writing information corresponding to a functional change of the data processing system into the nonvolatile memory element included in the nonvolatile memory block. development method. 6. In response to a change in the functionality of the data processing system, the data processing semiconductor integrated circuit is replaced with a new data processing semiconductor integrated circuit in which a software program corresponding to the function change is written into the nonvolatile storage element of the nonvolatile memory block. 4. The method for developing a data processing system according to claim 3, further comprising the step of: