JPH0283676A - Semiconductor integrated circuit for data processing - Google Patents

Abstract

PURPOSE:To easily respond to the change of operating specification and a function by attaching the operating specification which sets the loadable state of the nonvolatile storage element of a logic function block from the outside by a writer for an electrically loadable nonvolatile semiconductor memory device. CONSTITUTION:A single chip microcomputer 1 is constituted of a processor 5 consisting of CPU 2 as a logical operation control block, a RAM 3, and a ROM 4, a programmable logic array 6, and an input/output port 7 on a semiconductor substrate, and respective block is connected with a common bus 8. The microcomputer is provided with the operating function which sets the loadable state of the nonvolatile storage element of the logic function block or a nonvolatile memory block from the outside by the writer such as a universal EPROM writer. Thereby, it is possible to dispense with the use of a specific dedicated writer at the time of setting or changing the function of the operating specification for a semiconductor integrated circuit for processing.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit for data processing, and relates to a technique that is effective when applied to, for example, adaptation to changes in the operating specifications and functions of a single-chip microcomputer. [Prior art] CPU (central processing unit)
In a single-chip microcomputer in which a main component and necessary peripheral circuits are formed on a single semiconductor substrate, when changing a software program or fixing a bug, it is necessary to modify the memory that holds the program. For single-chip microcomputers with built-in memory that is subject to software program modification/change, the memory must be EPR
A configuration is disclosed in Jikai Publication No. 198667/1988 that converts the data into OM and makes it possible to control writing based on signal control from the outside. [Problems to be Solved by the Invention] Nowadays, as microcomputer application systems become more multifunctional and more compact, data processing LSIs such as single-chip microcomputers with various peripheral functions on-chip are becoming increasingly popular. Applications to these systems tend to be expanded more and more, and single-chip microcomputers are increasingly being used for interface circuits, timers/counters, input/output control circuits, ROMs that store control programs, and even sub-processors.
It has come to include various peripheral functions that can be configured as external memory or external logic. However, the peripheral functions, especially the hardware logical functions, built into such single-chip microcomputers have traditionally been fixed, so although it is possible to change the software program using EPROM program memory, the hardware In order to change the hardware logic function, it is necessary to change the design of the entire single-chip microcomputer and the mask pattern for manufacturing. The problem is that they are unable to set or change the required operating specifications and functions by themselves, and furthermore, they are unable to flexibly respond to changes in system operating specifications and functions during the development of microcomputer application systems. The present inventor has clarified something. Therefore, the inventor of the present invention proposed that a data processing semiconductor integrated circuit such as a single-chip microcomputer include a logic function block that can realize a required logic function depending on the write state of an electrically writable non-volatile memory element. was proposed earlier, but it is also necessary to adopt a specification that can improve usability for the user in terms of setting the logical function for the logical function block, that is, writing processing to the nonvolatile memory element included in it. I found out. An object of the present invention is to provide a data processing semiconductor integrated circuit that can easily cope with changes in operating specifications and functions, and more specifically, a logic function block including a nonvolatile memory element. It is an object of the present invention to provide a data processing semiconductor integrated circuit incorporating a logic function block and a non-volatile memory block, which can improve usability in terms of write processing to the non-volatile memory elements. . The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, it is configured to include a logic function block that can realize a required logical function depending on the state of writing to an electrically writable nonvolatile memory element, or a nonvolatile memory element that can electrically write a software program. A writing device such as a general-purpose EPROM writer is applied to a semiconductor integrated circuit for data processing, which consists of a nonvolatile memory block and a logical operation control block such as a CPU whose operation is controlled by its software program, formed on a single semiconductor substrate. It has operational specifications that enable writing to the nonvolatile memory elements of the logic function block and the nonvolatile memory block. For example, an operation specification that may be refused is a specification in which a data processing semiconductor integrated circuit is functionally similar to a non-volatile memory such as an EP ROM based on a mode signal, that is, a general-purpose EPROM.
Specifications can be made such that external terminals that can be interfaced with a writing device such as a ROM writer are visible. By adopting such operating specifications, it is possible to connect both data processing semiconductor integrated circuits and general-purpose writing devices by using an adapter such as a socket adapter with an hourglass configuration that exclusively changes the number and arrangement of external terminals of the data processing semiconductor integrated circuit and the general-purpose writing device. can be interfaced. At this time, the logic function block and the nonvolatile memory block are commonly connected to the internal address bus and the internal data bus, or the access terminals for data and addresses that are interfaced with the writing device are connected between the logic function block and the nonvolatile memory block. By making them common and arranging them both in the same address space, there is no need for special processing or circuitry for switching the 71-res space when writing logic function blocks or non-volatile memory blocks from the outside with a writing device. is not required, and information can be written to both the logic function block and the nonvolatile memory block using a common write device by simply changing the address signal. [Operation] According to the means described in 1., the operational specifications that enable writing to the nonvolatile memory elements of the logic function block and nonvolatile memory block from the outside with a writing device such as a general-purpose EPROM writer are as follows: When setting and changing the operating specifications and functions of semiconductor integrated circuits for data processing, there is no need to use a special dedicated writing device, and a general-purpose 1F writing device such as an EPROM writer for a single non-volatile memory such as an EPROM and by this,
During the mass production of data processing semiconductor integrated circuits, as well as during debugging or development of systems that apply this, data processing This improves the usability of semiconductor integrated circuits. [Embodiment] FIG. 4 shows a single-chip microcomputer 1 which is an embodiment of the data processing semiconductor integrated circuit according to the present invention.
is shown. The single-chip microcomputer 1 shown in the figure is a single semiconductor substrate such as silicon.
CPU (Central Processing Unit) 2, RAM (Random Access Memory) 3, and ROM (Li-1 only) as logical operation control blocks.
memory) 4, and a variable logic t19!
LA (programmable logic array) 6 and input/output capo-1 to
(!Ii is also written as Ilo) 7, and each block is connected by a common bus 8. In addition, the above P L
A6 is connected to l107 and CPU by signal line 9.10.
2. - [1 ROM 41 single chip microcontroller. As user's rough 1 he wear! It is for storing operating programs, ]22) 1. , A
6 is a logic function block for programmably realizing a part of the hardware of a single-chip microcomputer, and this PLA 6 includes an electrically writable nonvolatile memory element. FIG. 5 shows a detailed example of the single-chip microcomputer shown in FIG. 4, centering on the configuration of the PLA 6. The PLA 6 has an AND (logical product) surface 20, an R (logical sum) surface 21, an output latch 22, an input latch 23. and the selector 24, and wiring for connecting the respective circuits. The processor 5 and the PLA 6 are connected through a control signal line 8a, an address bus 8b, and a data bus 8C for inputting signals generated by the processor 5 to the input latch 23 of the PLA 6. The single-chip microcomputer 1 is interfaced with the outside by an output port a, an input/output port door b, and an input port 1-70 connected to the data bus 8c. P.L.A.
The inputs to the input latch 23 of 6 are the control signal lines 8a,
Address bus 8b, data bus 8c, input capo-1 to 7C
The output cuff 0c is the output 9C of the output selector 24, and the output of the input latch 23 is ANDed and supplied to the two sides. The output of the AND plane 20 is input to the OR plane 21, and the output of the OR plane 1 is given to the output latch 22. The output 22a of the output latch 22 is given to the selector 24, and
A part of the signal 22b is input to the AND screen 20. Outputs 9a and 9b of the selector 24 are input to the output port a and the input/output port door b, respectively, and the output 9c is coupled to the data bus 8c. FIG. 6 shows an example of the AND surface 20. This AND plane 20 may include non-volatile storage elements for EPROM (Electrically Programmable Read Only Memory) configurations such as, but not limited to, ultraviolet erasable electrically programmable channel injection structures. configured. This AND side 2o is made by 4 people (Io ~
I,) for four independent AND outputs (Ao-A3
). On this AND surface 20, nonvolatile memory elements M (0, O) to M (7,
3) is arranged in a matrix. Here, since the configuration of the nonvolatile memory element itself for the electrically writable EPROM configuration is already known, a detailed explanation thereof will be omitted, but the threshold voltage of the nonvolatile memory element is 1 [V A state at a relatively low level of about 5 [V] is defined as an erased state, and a state at a relatively high level of about 5 [V] is defined as a written state. Writing to the nonvolatile memory element is performed in units of rows by 4 bits. That is, the write data is sent to the write terminal DQ.
-Give to D3, selection line S. -81 to a selection level such as high level, and the write signal WE
is set to high level and the write voltage (
For example, give 12.5 [V]). At this time, human power ■. Whether to write positive logic or negative logic is determined by the state of ~■. For example, human power I. For example, when the input 1° is set to high level, the word line W. p is selected, and human power ■. When the word line W is set to low level. n is selected. A resistor R is connected to the gate l-'lIi electrode of the nonvolatile memory element whose gate electrode is coupled to the selected word line.
The pleasure voltage tj is obtained via j (j=a~7). Voltage conversion circuits W0 to W3, which receive write data at write terminals D0 to D3, generate drain voltages necessary for writing when the write data level is at a high level, and apply the drain voltages to the respective data lines d. −d. This results in
A nonvolatile memory element whose initial state is an erased state is put into a written state when a word line is selected and high-level write data is applied, and otherwise maintains an erased state. Through such a write operation, the nonvolatile memory elements M (0, O) to M (7,
The program 3) is carried out. When the programmed AND plane 20 is to perform a logical operation, the power supply voltage (or ground voltage) of the circuit is increased by 4 to the write terminal Vp, the write signal WE is set to low level, and the signal S is set. -83 are all set to high level. As a result, a word line is selected according to the levels of the inputs 1° to 3, and the data level corresponding to the program state of the nonvolatile memory element whose gate electrode is coupled to the selected word line is set to the data line d. -d, through the sense amplifier 5A
o-8A3, and as a result, the sense amplifier 5Ao-3A outputs an AND output A. -A is obtained. FIG. 7 shows an example of the OR surface 21 included in FIG. This OR surface 21 is a logical product output A. . A, OR circuit ORI with two-man power, AND output A2.
OR circuit ○R2 where A is powered by two people, OR circuit ORI,
The output of OR2 is cleared by an OR circuit R3 powered by two people, an output selection circuit 50 which selects the output of the OR circuit ORI and the OR circuit OR3. When the input signal 51 of the selection circuit 50 is set to high level, the transistor T1 is turned on and the transistor T2 is turned off, and the OR plane 21 outputs a logical sum ◯ as shown by the following logical formula. , 0□ is obtained. ○, =A, +A. 0, =A2+A3 Furthermore, when the input signal 51 of the selection circuit 50 is set to low level, the transistor T1 is turned off and the transistor '2 is turned on. Obtains the logical sum output ○.,○, shown as 0, =A, +A, +A2+A3 0, =A2+A. The single-chip microcomputer shown in FIG. 5 switches and controls the input latch 23 and selector 24. This makes it possible to operate, for example, in the manner shown in FIG. 8.The manner shown in FIG.
By selecting the information on the buses 8a to 8c as inputs of the processor 3 and giving the output of the selector 24 to the ports 7a and 7b, the output of the processor 5 is converted by the PLA 6 and sent to the outside of the single-chip microcomputer 1. This is what is output to. In the embodiment shown in FIG. 8(B), the outputs of the boats 7b and 7c are selected as inputs to the input latch 23, and the selector 24
By selecting the output 9o as the output of the single-chip microcomputer 1, a signal given from the outside of the single-chip microcomputer 1 is converted by the PLA 6 and given to the processor 5. In the embodiment shown in FIG. 8(C), the information on buses 88 to 8c is selected as input to the input latch 23, and the output of the selector 24 is also given to the bus 8c, so that the output of the processor 5 is transmitted to the PLA 6. The data is converted and returned to the processor 5 again. In the embodiment shown in FIG. 8(D), the outputs of ports t"7b and 7c are selected as inputs of the input latch 23, and the selector 2
By selecting outputs 9a and 9b as outputs of 4,
Regardless of the processor 5, a signal applied from outside the single-chip microcomputer 1 is converted by the PLA 6 and outputted to the outside of the single-chip microcomputer 1 again. Note that the embodiments shown in FIGS. 8(A) to 8(D) above are
It is also possible to combine two or more. For example, in the combination of the embodiments shown in FIGS. 8(A) and (B) above, PLΔ6
divides the input of the
c), the other is external input (7b, 7c), and PL
The output of A6 is also divided, and one side is connected to the input of processor 5 (8
C), the other can also be output to the outside (7a, 7b). In the single-chip microcomputer 1 described above, the two and eight six including the ultraviolet erasable electrically writable non-volatile memory element are required for the single-chip microcomputer 1 itself or its application system. (The logic configuration, that is, the program state of the non-volatile memory element is determined according to the function.The single-chip microcomputer 1 is enclosed in a package with a window, and the stored information is erased by irradiating ultraviolet rays through the window. By electrically rewriting new logic information, it becomes possible to change the logic and correct errors in the PLA 6, which plays a part of the hardware in the single-chip microcomputer 1, on the single-chip microcomputer 1. The computer 1 can flexibly respond to changes in operating specifications and functions during the development of the application system.Furthermore, the single-chip microcomputer 1 can be used repeatedly in response to such changes. The non-volatile memory element of PLA6 is electrically programmable and erasable MNOS (metal nitride 1-oxide semiconductor) or floating gate type E.
Non-volatile storage elements for EPROM (Electrically Erasable and Programmable Read Only Memory) configurations may also be utilized. Next, a single-chip microcomputer constructed by adding a programmable logic circuit having a processor structure, that is, a subprocessor, as a logic function block with a variable logic structure will be described. As shown in FIG. 9, this single-chip microcomputer 1 has a common bus 8, PLA 6, and 110
7 and a sub-processor 100 connected to it. FIG. 1-0 shows an example of the configuration of sub-processor 1, LOO, and sub-processor 100. PLA6. 1107 and the common bus 8 are shown. The sub-processor 100 has a ROM1 for storing instructions.
01, (7) ROMIOI (7) Control circuit 102 for generating control signals based on stored information, ROM10
Address latch 103.I holding the next address to access I. ALU (arithmetic logic unit) 107, register file 108, P
SG (Programmable Sequential Generator)
109, an STR (status register) 110 controlled by the PSG 109, and a BIF (bus interface circuit) 111 for connecting the sub-processor 100 and the common bus 8. The PLA 6 is connected to the common bus 8 by a wiring 112a, and to the bus 107 by a wiring 112b, and is connected to a control signal 102a generated by the control circuit 102 of the sub-processor 100 by a wiring 112d.
The signal 107a is input to the output 110a of the status register 110 and from l107 to the ALU 107.
are connected to each. The above PSG109, ROM101. , and PLA6 are constructed of electrically writable nonvolatile memory elements as described above. Therefore, even in the single-chip microcomputer 1 shown in FIG.
The logical configuration of the nonvolatile memory elements included in the SG 109, ROM iol, and PLA 6 is determined according to the operational specifications and functions required of the single-chip microcomputer 1. Then, after erasing the stored information by irradiating ultraviolet rays through the window formed in the package of the single-chip microcomputer 1, new logic information is electrically rewritten, and the hardware and logic in the single-chip microcomputer 1 are erased. PLA6, which plays a part of the function. It becomes possible to change the logic of PS0109, ROM101, etc. and correct errors. FIG. 11 shows an example of a single-chip microcomputer 1 in which the ROM 4 for storing a software program inside the chip is converted into an EPROM. In FIG. 11, a single-chip microcomputer 1 includes a CPU 2, a ROM 4 (hereinafter simply referred to as an EPROM) as an electrically writable non-volatile memory block for storing software programs.
(OM4 is also referred to as non-volatile memory block 4), a control signal generation circuit 500, and a programmable logic circuit 900 that constitutes the sub-processor, PLA, etc., and other functional modules. The above CPU2. - The nonvolatile memory block 4, the programmable logic circuit 900, etc. are connected to the address bus 41 and the data bus 42, and in particular, a switch element 61 is interposed between the address bus 41 and CI) U2, and the data bus 42 and A switch element 62 is interposed between the CPU 2, a switch element 63 between the nonvolatile memory block 4 and the data bus 42, and a switch element 63 between the programmable logic circuit 900 and the data bus 42. There is. The address bus 41 is interfaced with the outside of the single-chip microcomputer 1 by a signal line 519 via a 3-stay I-driver 72 that functions as an output buffer, an inverter 82 and a 3-state inverter 65 that function as an input buffer. is made possible. Similarly, the data bus 42 can be interfaced with the outside of the single-chip microcomputer 1 via a signal line 518 via a 3-state driver 71 that functions as an output buffer sofa, an inverter 81 that functions as an input buffer, and a 3-state inverter 64. It is being done. The control signal generation circuit 500 is supplied with control signals 5101 to 5104 for data transfer control from the CPU 2, and control signals 5111.5 for instructing the operation mode of the single-chip microcomputer 1.
121, 513, and 5122 are given from outside the single-chip microcomputer 1. The control signal generation circuit 500 to which such various signals are applied is connected to the CPU 2°, the nonvolatile memory block 4. Programmable logic circuit 9
Control signals 520 to 528 are generated for controlling data transfer timing between 00 and data bus 42, address bus 41, and signal lines 518 and 519. Note that the signal 5 output from the control signal generation circuit 5°O to the outside
14.5], 5 is a signal indicating a read cycle or a write cycle to the outside, and the nonvolatile memory block 4 and programmable logic circuit 900 have signals necessary for writing to the nonvolatile memory elements included therein. Signal line 516 for commonly applying high voltage etc. from the outside
are combined. In the single-chip microcomputer 1 shown in FIG. 11, a data bus 42 and an address bus 41
The nonvolatile memory block 4 and the programmable logic circuit 900, which are commonly connected to each other, are arranged in the same address space. Therefore, no special processing or circuit configuration is required to switch the address space when writing to the nonvolatile memory block 4 and the programmable logic circuit 900, and by specifying the addresses assigned to each, the same control can be achieved. Alternatively, write and verify processing can be easily performed on required nonvolatile memory elements included therein using the same sequence. As a result, a common writing device can be used, and even when using the built-in CPU 2, writing and verify processing can be performed in the same sequence. FIG. 12 shows the control signal generation circuit 50 shown in FIG.
An example of 0 is shown. This control signal generation circuit 500 is
Although not particularly limited, it is composed of the 1R surface 52 on the AND surface 5 surface. Each of the six vertical signal lines on the fifth AND surface is used as an AND output signal line, and the horizontal direction corresponding to the intersection indicated by a circle among the horizontal signal lines that intersect with the vertical signal lines The result of performing logical product on the inputs of the signal lines is the corresponding logical product output. For example, when the inputs of the horizontal signal lines indicated by circles that intersect with the vertical AND output signal lines are all at high level, the output of the corresponding vertical AND output signal line is set to high level. . The six AND output signal lines on the AND plane are input to the OR plane 52,
The horizontal logical sum output signal line that intersects with the six vertical human input signal lines corresponds to the intersection indicated by a circle. The result of performing a logical sum on the inputs of the vertical input signal lines is used as a logical sum output. For example, if the input of the vertical input signal line indicated by the O mark that intersects the horizontal OR output signal line is 1
If both are at high level, the output of the corresponding horizontal OR output signal line is set to high level. When the control signal 513 applied from the outside is at a low level, the AND output signal lines 5291.5292.5293.5296 which receive the inverted signal 5131 at the intersection of the circles are connected to the control signals 5101 to 5104 output from the CPU 2.
A logical AND output is obtained that makes the level of . In this state, control signals 5101 (TRI), 5104
When (Ex tM) is at a high level, the AND output signal line 5291 is at a high level and the external device read mode is set. In this operating mode, the control signal 51.1 indicating a read cycle to the outside is
(TR3) is asserted to a high level, and control signals 520.527.528 are also asserted to a high level. The high level control signal 520 is applied to the switch element 6
1 to the on state, and a high level control signal 52
8 controls the 3-state driver 72 to enable output operation, so that the address signal output from the CPU 2 is output to the outside via the address bus 41 and the signal line 519. Data output from an external accessed module (not shown) in response to the 7 trace signal and the control signal 514 is externally applied to the signal line 518, and the 3-state inverter 64 is turned on by the high-level control signal 527. is applied to the data bus 42 and read into the CPU 2. In this external device read mode, the control signal 52
4 is set to low level, the data fetched from the outside to the data bus 42 is transferred to the nonvolatile memory block 4.
and the operation of the programmable logic circuit 900. "- When the control signal 513 is at low level, the control signal 5
When 102 (TWI) and 5104 (ExtM) are set to high level, the output signal line 5292 becomes high level and external device write 1-mote is set. In the operating mode, the control signal 515 (TW3), which means a write cycle for the program section, is asserted to a high level, and the control signals 520 and 521 are asserted to a high level.
．． 526 and 528 are also asserted to high level. As a result, the address signal output from the CPU 2 is transmitted to the switch element 61 which is turned on in the same manner as described above, the 3-state driver 72 which is controlled to be capable of output operation, and the signal line 511.
] is output to the outside via (', F' L
The write data output from J2 is turned on by a high-level control signal 521, a switch element 62,
Data bus 42. The 23 stays I to 1-live buffer 1 are controlled to enable output operation by a high-level control signal 526, and are externally supplied via the signal line 518, thereby allowing writing to the external accessed module. It will be done. When the control signal 513 is low level, the control signal 510
1 (TRI) and 5103 (IntM) are at high level, the output signal line 5293 becomes high level and the internal device read mode is set. In the operation mode I-, the control signal 520.522 (TR4)
, 524 are asserted high. This allows C
The address signal output from PU2 is sent to switch element 61.
The address signal 1126 of the nonvolatile memory block 4 or the address signal 5172 of the programmable logic circuit 900 is applied to the address bus 41 via the address bus 41 . At the same time, the control signal 522 instructs the nonvolatile memory block 4 and the programmable logic circuit 900 to perform a read operation. At this time, since the nonvolatile memory block 4 and the programmable logic circuit 900 are arranged in the same linear address space, even if the A (heres signal) is given to both, only one of them reads data according to that address signal. , the read data is sent to the switch element 6
3 or 66 to the data bus 42. The CPU 2 reads the data outputted to the data bus 42 in this way from the signal line 423. When the L control signal 513 is at low level, the control signal 510
2 (TW, L), 5103 (Int, M) are at a high level, the output signal line 5296 becomes a high level and internal device write mode 1~ is set. In this operating mode, the control signals 520, 521, 52
3 ('T"W,,) is asserted to a high level. As a result, the address signal output from the CPU 2 is applied to the address bus 41 via the switch element 61, and the write data output from the CPU 2 is applied to the data bus 42 via the switch element 62, and furthermore, the programmable logic circuit 900 is instructed to perform the 1-operation.As a result, the processor 1 assigned to the desired address of the programmable logic circuit 900 specified by the address signal On the other hand, when the control signal 513 is at a high level, the AND output signal line 52 receives its inverted signal 5131 at the intersection of the circles.
91.5292.5293.5296 is CI) U
The control signals 5101 to 5104 outputted from the CPU 2 are negated to a low level regardless of their levels, and the control signals 520 and 521 are thereby always controlled to a low level, and are sent to the data bus 42 and the address bus 41 by the CPU 2. output of data and addresses is virtually impossible. That is, the CPU 2 is disconnected from the address bus 41 and data bus 42. In this state, the control signal 5121
When (TR,) is set to high level, AND output signal line 5294 becomes high level, and read mode based on external access is set. This operating mode is E
It is used for test reading for verification after writing by a PROM writer or the like. In this operating mode, the control signals 522 (T R4),
524.525.526 is asserted high. As a result, the address signal supplied from the outside to the signal line 519 is applied to the address bus 41 via the 3-state inverter 65 which is controlled to be operable by the control signal 525, and this address signal is applied to the address bus 41.
1 to the nonvolatile memory block 4 and the programmable logic circuit 900 via signal lines 426 and 5172. The nonvolatile memory block 4 and the programmable logic circuit 900 are instructed to perform a read operation by the control signal 522, and the data output terminals of the nonvolatile memory block 4 and the programmable logic circuit 900 are connected to the data bus 41 by the control signal 524. be done. Therefore, the required data to be read is provided to the data bus 42 by either the non-volatile memory block 4 or the programmable logic circuit 900 performing a read operation in response to an address signal supplied from the outside. . The read data applied to the data bus 42 is outputted by a high-level control signal 526 and is applied to the transmission line 518 via the 3-state driver 71 controlled to enable one operation, and is read out to the outside. When the control signal 513 is at high level, the control signal 5122
(TW2) is set to high level, the output signal line 52
95 becomes high level, and a write mode based on external access is set. This operating mode is used when thinning the IEP ROM writer. In this operating mode, control signals 525 and 527 are asserted to a high level. As a result, the address signal supplied from the outside to the signal line 519 is supplied to the address bus 41 via the 3-state inverter 65 which is controlled to be operable by the control signal 525. This address signal is transmitted from the address bus 41 to the signal line 426.
and 517F to the nonvolatile memory block 4 and programmable logic circuit 900. Further, data supplied from the outside to the signal line 518 is transmitted to the control signal 52.
The data is applied to the data bus 42 via the 3-state inverter 64 which is controlled to be operational by the data bus 42 and the nonvolatile memory block 4 and the programmable logic circuit 900 via the signal lines 424 and 5171. Given. In this state, no signal is received from the external terminal.
) High voltage for writing is applied to line 516! When the data is written, the write data is written to the nonvolatile memory element at a predetermined address of the nonvolatile memory block 4 or programmable logic circuit 900 specified by the address signal. The write high voltage is set to be a voltage sufficient for a write operation of about 10 to 25 [V] corresponding to a single memory LSI such as an EPROM. Note that EEPROM is electrically programmable and erasable.
When the nonvolatile memory block 4 and the programmable logic circuit 900 are configured using nonvolatile memory elements for configuration, erasing and writing voltages may be applied via the signal line 516, and The write voltage and erase voltage may be generated by an internal booster circuit. Even in the single-chip microcomputer 1 shown in FIG. 11, the non-volatile memory elements of the non-volatile memory block 4 and the programmable logic circuit 900 included therein meet the operational specifications required for the single-chip microcomputer 1 or its application system. Its logical configuration is determined according to the function. After erasing the stored information by irradiating external radiation through the window formed in the package of the single-chip microcomputer 1, the hardware in the single-chip microcomputer 1 is erased by electrically rewriting the logical information. It becomes possible to change the logic and correct errors in the programmable logic circuit 900 that plays a part of the software, and also to change the program stored in the nonvolatile memory block 4 and correct bugs.
The single-chip microcomputer 1 can now flexibly respond to changes in its operating specifications and functions. A detailed example of the programmable logic circuit 900 is illustrated in No. 13-1. In FIG. 13, 91 is a NOR array including nonvolatile memory elements, 961 to 9633 are logic modules, and 9
461 to 9463 are selectors, 94333 is a sense amplifier, and 9434 is a write circuit. 9431 and 9432 are address decoders, 941 is a data register, 942 is an address register, and 9435 is a multiplexer. The logic 1 module 961 is composed of a NOR gate 922, a flip-flop 92], selectors 923 and 924, an output driver 925, and an ANDNO gate 922927. NOR array 9] has 6 logic modules 96 that can adopt a logic configuration according to write program states for a plurality of non-volatile memory elements included therein.
1 to 963 further programmably change the logic of the signals output according to the logic configuration of the NOR array 91- according to the selection operating conditions of the selectors 923 and 924 and the state of the flip-flop tab 921. This constitutes a variable structure logic together with the NOR array 91. Logic modules 961 to 963 connect signal lines 5171 to
Data bus 42 and address bus 4 via 5173
1 and 1, and data can be input/output to/from the outside of the single-chip micro combi coater 1 via the terminals 9r>1-.993. When the control signal 513 is at a low level, the data input/output target is the logic module 96.
When the control signal 513 is at a high level, writing/reading to/from the nonvolatile memory element forming the NOR logic of the NOR array 91 is enabled. When the control signal 51-3 is set to low level and the internal device read mode is set, the address signal output from the CPU 2 is transferred from the address bus 41 to the signal line 51.
72. After this address signal is set in the address register 942, it is supplied to the address decoder 9432 via the A and ND gates 951, and is decoded by the address decoder 9432. This address decoder 9432 forms a selection Lf number that selects one of the logic modules 961 to 963 according to the input address signal. Note that the selection level is set to high level. The output selection signal 5310 of the 71-less decoder 9432 is provided to the AND gate 926 of the logic module. This AND gate 926 is also supplied with the Hokkaido control signal 522 at a high level in the operating mode. From this AND gate 926, the selector 92
3. The data of the flip-flop 921 is outputted via the output tno1 driver 925, and this output data is sent to the signal line 5.
311 and the selector 9435, and is read out from the signal line 5173 to the data bus 42. -1', when the control signal 513 is set to low level and the internal device write mode is set, CP t,
, the address signal output from J2 is on the believe line 5172.
and data is provided on signal line 517]. This provides data via AND game h 953 to AND game 1-927 of the logic module. This ANDNO gate 922 is supplied with a high level control signal 523 in the relevant operation mode, and
A selection signal corresponding to the decoding result of the address signal is supplied from the address decoder 9432. therefore,
The output data of the CPU 2 can be written to the flip-flop 921 specified by the address signal. When the control signal 513 is set to a high level to set a write mode based on external access, the output of the address register 942 is supplied to the address decoder 9431 via AND gates 1 to 952. This address decoder 9431 outputs the NOR array 91 . Select one of the lines 986 to 989. The data given to the signal line 5171 from the CPU 2 is set in the data register 941, and the AND gate 95
4 to the write circuit 9434. Write data is sent to selectors 9461 to 946H3 in synchronization with the timing when a write high voltage is applied from the outside.
I can get it. The selector selection signal 5312 of the address decoder 9431 responds to the input address signal.

[Bin 1 at -7~
Lines 981 to 985 are selected and write data is stored on the selected bit line, thereby writing to the nonvolatile memory element. At this time, the output of the selector 924 inside the logic module is controlled to a high impedance state by the signal 513, thereby preventing undesired signals from being mixed into the word lines 986-989 from the logic module 1. When the control signal 513 is set to a high level to set a read mode based on external access, line data is transferred to the pin 1 of the NOR array 91 specified by the address decoder 9431 to the selector 9, similarly to the write mode.
The signal is supplied to the sense amplifier 9433 via signals 461 to 9463, and read out to the signal line 5173 via the selector 9435. As shown in Figure 2, when the control signal 5]3 applied from the outside is at a low level, data is input/output to and from the flip-flop 921 inside the logic modules 961 to 963, and when the control signal 51z3 is at a high level, Writing and reading are performed based on external access to the NOR array 91 made up of nonvolatile memory elements C. N
When an electrically writable/erasable nonvolatile memory element is used in the OR array 9, an erasing operation can also be performed with the same circuit configuration as writing by adding an erasing circuit. Note that even if the configuration of the programmable logic circuit 900 changes, for example, if there are multiple NOR arrays 91, if the internal logic structure of the logic modules 96 to 963 differs, if the number of flip-flops 921 differs, or Even in the case where there are no signal lines 991 to 993 from the logic modules 961 to 963 to the external terminals, this embodiment allows access from the (2 P U 2 and external terminal -t) of a single-chip microcomputer. A similar configuration can be adopted.According to the following explanation, the programmable logic circuit 9 of the single-chip microcomputer 1 shown in FIG.
00 can include the PLΔ6 in FIG. 6, the subprocessor 100 in FIGS. 1-0, and the circuit shown in FIG. The nonvolatile memory block 4 and the nonvolatile memory block 4 can be arranged linearly in the same address space, although this is not particularly limited. FIG. 14 shows an example of an address mapping state between the programmable logic circuit 900 and the nonvolatile memory block 4 in the same address space. According to FIG. 14, the nonvolatile memory block 4 contains 0OOOH to 3
Addresses up to FFFH are assigned, and the programmable logic circuit 900 has addresses 40008 to 7FFH.
Addresses up to [;” Writing and test reading can be performed by giving a different address from the standard EP. By making it almost the same as ROM, in other words, it can be used as a standalone EPROM or EEIIR.
By matching the general specifications of a general-purpose writing device such as an EPROM writer for programming an OM, the general-purpose writing device W can be used as is to electrically write data included in the single-chip microcomputer 1. It becomes possible to perform write and verify processing on possible nonvolatile memory elements. When the control signal 513 is set to a high level to set the write/read mode by external access, the address bus 41 and data bus 42 to which the programmable logic circuit 900 and the nonvolatile memory block 4 are commonly connected are , are separated from the CPU 2 by gates such as switch elements 61 and 62. Therefore, in this operating mode, the single-chip microcomputer Y looks functionally similar to a single non-volatile memory LSI such as an EPROM. Paraphrase Lunala, m-body EPRO
EPR for programming M and EEPROM
For a general-purpose writing device such as an OM writer, external terminals with which it can be interfaced become visible. A general-purpose EPROM writer 1000 for writing and testing 1512 on an electrically writable non-volatile semiconductor memory device such as an EPROM supplies an electric voltage Vcc as shown in FIG. 1, although it is not particularly limited. a power supply terminal Pwvcc for outputting an address signal, an address output terminal Padrs for outputting an address signal, a control terminal Poe for outputting an output enable signal OE indicating 4B data input/output direction, and a high voltage VP for writing.
Terminal Pvp that can selectively output P or power supply voltage Vcc
p, a control terminal Pce for outputting a chip enable signal GE for instructing chip selection/non-selection, and a data input/output terminal f-Pdata for inputting read data and outputting write data. Such E
In the PROM writer 1000, during a write operation, the output enable signal OE is at a high level, the chip enable signal CE is at a low level, and the output terminal of the write voltage VPP is at a high level such as 12.5 [V].
It is subject to city pressure. On the other hand, during test I for verification to read, the output enable signal ○E is at a low level, the chip enable signal CE is at a low level, and the output terminal of the write voltage VPP is at a voltage of about 5 [■] in response to the power supply voltage Vcc. voltage. Such an EPROM writer and a single-chip microcomputer 1 as shown in FIG. 11 are different in number and arrangement of external terminals, as shown in FIG. They are electrically coupled via an adapter 1001 such as a socket adapter for connection. For example, an example of a manner in which the single-chip microcomputer 1 and the EPROM writer 1000 are connected via the adapter 1001 is shown in FIG. That is, EPR
An inverted signal of the chip enable signal CE output from the control terminal P c t+ of the OM writer 1001 is applied to the external terminal P9.3 of the single-chip microcomputer 1 as a control signal 513 shown in FIG.
The write voltage VPP or power supply voltage Vcc selectively output from the external terminal Pvpp of the M writer 1000 is applied to the external terminals P, 1 . is supplied to signal line 516 via EP
The inverted level of the output enable signal ○E output from the control terminal Poe of the ROM writer 1000 is applied to the external terminal P6.2□ of the single-chip microcomputer 1 as the control signal 512 in FIG. The enable signal OE is the control signal 5 in FIG.
As 122, the external terminal P! of the single-chip microcomputer 1 is connected. 1122 and output from the address output terminal Padrs of the EPROM writer 1000 is applied to the signal line 519 via the external terminal Psi'a of the single-chip microcomputer. And the data input/output terminal Pd of the E P ROM writer
ATA is connected to the data input/output terminal p, □8 corresponding to the signal line 518 of the single-chip microcomputer 1, and the power terminal Pwvcc of the EPR,0M writer 1000 is connected to the '11i source terminal PmV of the single-chip microcomputer 1. It is coupled to cQ. Note that if the control signal generation circuit 5°O is configured such that the control signal 5121 is converted into an inverted level signal of the control signal 5122 by an inverter (not shown) and only the control signal 5122 is directly applied from an external terminal, The output enable signal ○E can be directly applied to the external terminal. FIG. 3 shows another example of a connection mode. In such an embodiment, the power terminal Pw of the adapter 1001-H
The power supply voltage Vcc output from Vcc is used as a high-level control signal 513 to output terminals PS□ and 4 of the single-chip microcomputer to the alarm output enable signal OE and chip enable signal CE. The control signal 5 is the result of NOR logic on the adapter.
121 is applied to the external terminal i)S□2 of the single-chip microcomputer 1, and NOR logic is applied to the inverted level of OE (i?) and the chip enable signal CE with the adapter 1. The obtained result is applied as a control signal 5122 to the external terminal P1tzz of the single-chip microcomputer, and the other connections are the same as those shown in Fig. 2. Fig. 15 shows the data store loading and verifying. The timing chart required for test readout is shown in Figure 1.
is connected to the EPROM writer tooo.
] When a power supply voltage Vcc of about 100% is applied to the single-chip microcomputer 1, the single-chip microcomputer 1 becomes operational. After that, the address signal of the address to be written to the nonvolatile memory block 4 or the programmable logic circuit 900 is EPRO.
The Outputs 1 Hay Enable signal OE output from the M writer 1000 remains at a high level, and
A write high voltage vpp of approximately 2.5 [■] is output, and the chip enable signal C15 is asserted to a low level. As a result, writing of data to the required nonvolatile memory element selected by the TomomiA1Heres information is started. The period during which the chip enable signal CE is asserted to a low level is determined by the characteristics of the nonvolatile memory element for configuring the EP ROM, and is, for example, about 1 m5ec. Chip OK - The write mode is ended by negating the pull signal CE to a high level and returning the write voltage vpp supplied to the signal line 516 of the single-chip microcomputer 1 to the power supply voltage Vc, c. be done. When the chip enable signal CE is asserted to low level while the address used for writing (?1) is output, the non-volatile memory selected by the address signal is The data of the digital memory element is output from the single-chip microcomputer 1. By determining whether or not this read data matches the written data, a helifi process is performed to determine whether or not the data has been written normally by the write operation. When the necessary data is written and verified in this way, the single chip microcomputer 1 becomes able to execute data processing depending on the logic achieved by the written state. CP employing microprogram control
An example of a single-chip microcomputer including U2 is shown. In the single-chip microcomputer shown in FIG.
(also referred to as M) 600 and an EPROM 624 for storing operating programs consisting of multiple macro instructions.
It has two semiconductor substrates. CF) Micro EPR○M60 included in U2
(') indicates a write circuit 60 connected to the address bus 41 and data bus 42 through signal lines 653 and 652.
1 and a signal line 6 to the address bus 41 and data bus 42.
Test readout circuit 60 connected at 51,650
3 and the instruction fetch circuit 602 connected to the data bus 42, and is further connected to the instruction fetch circuit 602 connected to the data bus 42, and is further connected to "1" during the instruction control operation
It is connected to a read circuit 604 for reading micro instructions of the micro EPROM 600. The microinstruction output from the readout circuit 604 is applied to the control circuit 607 and decoded, and the control signal generated thereby controls the operations of the arithmetic circuit 605, the instruction fetch circuit 602, the address generation circuit 606, and the like. The address generation circuit 606 supplies the address of the macro instruction to the address bus 41 via a signal line 648. This CP
U2 is operated in synchronization with the clock signal φ. The non-volatile memory block 4 has a husband 4' address bus 41.
, a read circuit 621 connected to the data bus 42, a write circuit 622, a test read circuit 623, and an E I ROM 624 connected thereto. Further, the readout circuit 621 is also connected to the control circuit 607 of the processor 2 . The address bus 41 and the data bus 42 are connected by signal lines 654.655 to a bus precharge circuit 671 controlled by the clock signal φ, and the address bus 41 is further connected to the signal v;A612. The single-chip microcomputer is interfaced with the outside via an input circuit 608 and a signal line 611. Further, the data bus 42 includes a signal line 614, an input/output circuit 609,
In addition, the single-chip microcomputer can be interfaced with the outside via a signal line 613. Outputs 630 to 639 of the control signal generation circuit 500 connected to the external control signal line 610 are used for command control operations,
Micro EPROM600. It is connected to each of the above-mentioned circuits in order to control writing to the EPROM 624 and operations of the eggplants 1 to IA. -1=, writing to the micro EPROM 600 is. The control signal is set by applying a write mode signal to the input line 610, and in this state, among the outputs 630 to 639 of the control signal generation circuit 500, the write circuit 60
1 control signal 636. Control signal 638 for input circuit 608
．． Only the control signal 639 of the input/output circuit 609 becomes valid, and the other signals are controlled to a negated state. That is, output from the CPU 2, nonvolatile memory block 4, and bus precharge circuit 671 to the data bus 42 and address bus 4J- is prohibited, and each of the buses 41 and 42 is connected to the micro EPR○M 600 via the write circuit 601.
Used only for writing to. The external connection line 611 of the input circuit (408) is given address information for selecting a desired element from the group of non-volatile memory elements constituting the micro EPROM 600, and the external connection line 613 of the input/output circuit 609 is controlled in the input direction. The write data to the memory element selected by the above address information is given from
Furthermore, a write signal is given to the control human power line 610. This allows the microlE specified by the external address signal to
Necessary microinstruction information is written into a predetermined address of the PROM 600. A test as to whether or not the seeding operation has been performed correctly is performed by applying a MO1~ signal for test reading to the micro EFROM 600 to the control input line 610. When the operating mode is set, among the outputs 630 to 639 of the control signal generation circuit 500, the control signals 635. The control signal 638 of the input circuit 608 and the control signal 639 of the input/output circuit 609 become valid. As a result, when an address signal is applied to the external input line 611 and a signal No. 1 for reading test signals of the micro EPR○M600 is applied to the control input line 610, the input/output circuit 609 is controlled in the output direction. , the read data of the selected micro EPROM 600 is transmitted to the test read circuit 603, the connection line 650, the data bus 42,
The signal is output to an external connection line 613 via the connection lines 61 and 61 and the input/output circuit 609. This allows verification externally. Nonvolatile memory element group 624 of nonvolatile memory block 4
Writing to, and reading from Des1 as well. Writing of the above micro E P ROM +300,
Similar to test reading, this is performed by controlling the writing circuit 622, test reading circuit 623, input circuit 608, and input/output circuit 609 using a control signal from the control signal generation circuit 500. The operation of the semiconductor integrated circuit in normal mode 1, that is, during the instruction control operation, is performed in synchronization with the clock φ, for example, as follows. When the address information generated by the address generation circuit 606 of the CPU 2 is sent to the readout circuit 621 of the nonvolatile memory block 4 via the address bus 41,
Read signal line 671 from control circuit 607 of CPU2
A predetermined macro instruction is read from the nonvolatile memory element group 624 based on the signal, and is taken into the instruction fetch circuit 602 via the data bus 42. The information held in the instruction fetch circuit 602 is stored in the micro EPROM 60.
0, and based on that information micro EPROM6
00 is addressed and the microinstruction is read into the read circuit 604 accordingly. This read information is used as control information inside the CPU 2, etc. The mital instruction read by the read circuit 604 is input to the control circuit 607 and decoded, and based on this, the arithmetic circuit 605, address generation circuit 606, instruction fetch circuit 602, memory read circuit 621, etc. are controlled. In addition, in such an instruction control operation, the data bus 42 and address bus 41 are precharged by a bus precharge circuit 671 that operates in synchronization with the clock signal φ, and a series of operations of the single-chip microcomputer are carried out by the CPU 2. It is synchronized with the supplied clock signal φ. Test readout circuit 6 of the above CPU2
The number of parallel output bits of the test readout circuit 604 and the test readout circuit 604 do not need to be equal.
The number of parallel output bits from 03 is equal to the number of bits of data bus 42. Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. For example, in the above embodiment, the operating specifications of a single-chip microcomputer that allows writing to logic function blocks and non-volatile memory blocks from the outside using a malicious device such as a general-purpose EPROM writer is such that mode 1-1 such as the external signal 513 is used. Specifications that allow a single-chip microcomputer to look functionally similar to a single non-volatile memory LSI such as an EPROM by means of signals, in other words, an external specification of a single-chip microcomputer that can be interfaced with for a writing device such as a general-purpose EPROM writer. It is designed so that the terminals are visible. This allows single-chip microcomputers and EPR
A single-chip microcomputer 1 is converted into a general-purpose EP using an adapter 1001 with a simple configuration that exclusively changes the number and arrangement of external terminals between OM writers 1000.
By connecting to the ROM writer 1001, it is possible to write to nonvolatile memory elements included in logical function blocks and nonvolatile memory blocks. The present invention is not limited to such operational specifications, and the control circuit equipped with communication means or interface means can be connected to a single-chip microcomputer and a general-purpose E.
Interposed between the PROM writer and this general-purpose EPROM
The various information necessary for writing output from the writer is given to the required ■/○ of the single-chip microcomputer through the interface means, and in this way, the 4j
It is also possible to set the operation specifications such that the built-in CPU performs necessary control operations based on the obtained information to enable writing. At this time, the write operation instruction to the CPU is the general-purpose EPR.
It can be included in part of the address signal output from the OM writer. Furthermore, in the above embodiment, the logic function block and the non-volatile memory block are commonly connected to the internal address bus and the internal data bus, but the logic function block does not necessarily have to be connected to the internal address bus and the internal data bus in order to function. There isn't. When not coupled to the internal address bus and internal data bus, a dedicated transmission path for data and addresses for writing and verifying can be provided between the nonvolatile storage element of the logic function block and the external terminal. Further, the logical function block and the nonvolatile memory block are not limited to being placed in the same linear address space, but may be placed in different spaces. In this case, space switching control is required when logical function programming or writing or test reading from the nonvolatile memory block is performed from the outside. Such spatial switching can be accomplished by a simple switch on the adapter providing the spatial switching signal to a terminal assigned for such switching in a dedicated or predetermined operating mote. In addition, there are also four configurations of logic function blocks that can realize a required logic function depending on the writing state of an electrically writable nonvolatile memory element, and a configuration of a nonvolatile memory block for extending a software program. In addition, the structure of the electrically writable nonvolatile memory element included therein and the processing content for loading data into them are not limited to the above-mentioned embodiments, but can be modified as appropriate. Furthermore, data processing semiconductor integrated circuits such as single-chip microcomputers containing electrically writable non-volatile memory elements for the EPROM configuration applied to the above embodiments are not necessarily packaged in windowed pancases whose information can be erased by ultraviolet light. It is not limited to an enclosed form, and may be of a format that allows writing only once. In this case. By using a single-chip microcombicoater with exactly the same structure, writing new information into it, and installing it in the system, changes in operating specifications and functions during system development can be handled using a single-chip microcomputer with the same structure. be able to. The above explanation has mainly been about the case where the invention made by the present inventor is applied to a single-chip microcomputer, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, but can be applied to various types of data processing 16-conductor integrated circuits. The present invention can be applied to at least an electrically writable logic function block, or one in which this logic function block and a nonvolatile memory block are held on one semiconductor substrate. [Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. That is, a logic function block that can realize a required logic function depending on the write state applied to an electrically writable non-volatile memory element, or a combination of this logic function block and an electrically writable non-volatile memory element. A data processing semiconductor integrated circuit consisting of a non-volatile memory block including a non-volatile memory block and a logical operation control block such as a CPU formed on one semiconductor substrate is written externally using a writing device such as a general-purpose EPROM writer. Since the operating specifications are such that the nonvolatile memory elements of the data processing semiconductor integrated circuit can be written to, a special dedicated writing device is required to write the required data to the nonvolatile memory elements included in the data processing semiconductor integrated circuit. There is no need to prepare a general-purpose EPROM, and it is now possible to write and test read using a writing device such as a general-purpose EPROM. It is possible to improve the usability of the data processing semiconductor integrated circuit in terms of writing processing to the nonvolatile memory element included in the data processing semiconductor integrated circuit during debugging or development, and even during mass production. In addition, as an operation specification that allows writing to the nonvolatile memory elements of the logic function blocks and nonvolatile memory blocks from the outside with a writing device such as a general-purpose EPROM writer, data processing is performed using a mode signal. By making the semiconductor integrated circuit functionally similar to a non-volatile single memory such as an EPROM, in other words, making the external terminals that can be interfaced with it visible to a writing device such as a general-purpose EPROM writer, it is possible to use it for data processing. It is possible to interface between a semiconductor integrated circuit and a general-purpose writing device by using an adapter such as a socket adapter with a simple configuration that exclusively changes the number and arrangement of external terminals between the two. There is an effect that the usability of the data processing semiconductor integrated circuit can be further improved with respect to write processing to the data processing semiconductor integrated circuit.The logic function block and the nonvolatile memory block are commonly connected to the internal address bus and the internal data bus,
Alternatively, by commonizing access terminals such as data and addresses to be interfaced with the writing device between the logical function block and the non-volatile memory block, and placing both in the same address space,
When writing a logic function block or a non-volatile memory block from the outside with a writing device, no special processing or circuitry is required for address space switching, and the logic function block can be written by simply changing the address signal. It becomes possible to write information to both the non-volatile memory block and the non-volatile memory block using a common re-writing device, and in this respect as well, there is an effect that usability can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing the external appearance of a single-chip microcomputer according to an embodiment of the present invention when writing/test reading is performed using a general-purpose EPROM writer via an adapter. Figure 2 shows a single-chip microcomputer and a general-purpose E
An explanatory diagram showing an example of how a PROM writer is connected with an adapter. Figure 3 shows a single-chip microcomputer and a general-purpose E
An explanatory diagram showing another example of how a PROM writer is connected with an adapter, Fig. 4 is a block diagram showing an example of a single-chip microcomputer, and Fig. 5 is an example of a logic function block. A block diagram of another single-chip microcomputer centered around the center, Figure 6 is a circuit diagram showing an example of the AND side of the PLA in Figure 5, and Figure 7 is an example of the OR side of the PLA in Figure 5. A circuit diagram showing. 8(A) to 8(D) are explanatory diagrams of the operation mode when focusing on PLA and Ilo in the single-chip microcomputer shown in FIG. 5, and FIG. 9 is a subprocessor which is an example of a logical function block. 10 is a block diagram showing an example of the sub-processor shown in FIG. 9. FIG. 11 is a block diagram showing an example of the sub-processor shown in FIG.
A block diagram of a single-chip microcomputer equipped with an OM program memory, FIG. 12 is a logic diagram showing an example of a control signal generation circuit included in the single-chip microcomputer of FIG. 11, and FIG. 13 is a single logic function block. FIG. 14 is an explanatory diagram showing an example of address mapping of logical function blocks and nonvolatile memory blocks, and FIG. 15 is a block diagram showing a detailed example of the address mapping in the single-chip microcomputer shown in FIG. Timing diagram 1-1 shows an example of the timing required for data insertion and helifi test read operations for the included logical function blocks and non-volatile memory blocks. Figure 16 is a single chip that employs microprogram control. FIG. 2 is a block diagram showing an example of a microcomputer. l...Single chip microcomputer, 2...
・CPU, 4 ・Non-volatile memory block, 5... Processor, 6.1〕■, A, 7 (7a, 7b, 7c
)...1/○, 20...A N 0 plane, 21 - OR plane, 41... 71 Helles bus, 42... Data bus, 91
・N○R array, 500...control signal generation logic, 51
3. Control signal, 900. Programmable logic circuit, 1
000-General-purpose EPROM write 'j, LOO]...7 adapter. Figure Figure Figure One layer - Figure/ / Figure Figure AoA+ 2A3 Figure p A. △ Figure Figure ■ Figure Figure Figure 25A Figure Figure Figure Figure

Claims (1)

[Claims] 1. A logic function block that can realize a required logic function depending on the state of writing to an electrically writable nonvolatile memory element, and a logic that uses this logic function block to execute a logic operation. A data processing semiconductor integrated circuit in which an operation control block and an operation control block are formed on one semiconductor substrate, the logic function block being non-volatile from outside using a writing device for an electrically writable non-volatile semiconductor memory device. A semiconductor integrated circuit for data processing that has operational specifications that allow writing to memory elements. 2. A mode terminal is provided for specifying a write operation by the write device, and by specifying a write operation mode from this mode terminal, a predetermined external terminal is assigned as an access terminal for the nonvolatile memory element of the logic function block. 2. The data processing semiconductor integrated circuit according to claim 1, further comprising control means for controlling. 3. The above logic operation control block is a CPU, and this C
It includes a non-volatile memory block in which a program for operating the PU can be stored in an electrically writable non-volatile memory element, and has operational specifications that allow writing to the non-volatile memory block from the outside using the writing device. 2. The data processing semiconductor integrated circuit according to claim 1. 4. A mode terminal is provided for specifying the write operation by the write device, and by specifying the write operation mode via this terminal, a predetermined external terminal is connected to the nonvolatile memory of the logic function block and the nonvolatile memory block. 4. The data processing semiconductor integrated circuit according to claim 3, further comprising control means for controlling allocation as a common access terminal to the elements. 5. The access terminal is a terminal that can interface with an address output terminal, a control signal output terminal, and a data input/output terminal of the writing device, and can be coupled to the writing device via an adapter. Semiconductor integrated circuit for data processing. 6. The data processing semiconductor integrated circuit according to claim 5, wherein the logical function block and the nonvolatile memory block share an internal address bus and an internal data bus, and are arranged in the same address space.