JPS58129479A - Electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to an electronic pastry device suitable for use in teaching purposes.

Part of ##I (8) in 1st year is the song data of the current song (consisting of note data indicating the note length or clef of each f note that makes up this song). We set up 6 dance mediums such as recorded magnetic tapes, extracted the music data from this distribution stick and performed automatic recording, or sent gifts of 1M discs to the sister ministry. Electronic musical instruments, such as electronic organs, have been developed that can be used to direct

By the way, with such an electronic system, the amount of data such as musical note data to be recorded in the pre-arrangement media is miserable and multi-wave, when the music to be played is long. Due to the inherent limitations of the recording container, there was a problem in that it was not possible to record the music data of the previous song depending on the normal recording method.

The present invention solves the above problem by providing an electronic musical instrument that can perform music playback such as automatic performance using music data that is extremely efficiently recorded on a recording medium. The data converted according to the data Arashi Kai information is recorded as 1M2 note data with few conversions, and the 11" ml Teddy earthquake conversion report is also recorded on the same related media, and it is used as a means of tracking. In addition to storing data conversion information including data such as MiJ data change information, degree data, etc. from the MiJ recording medium,
Based on the stored data conversion information, the note data is inversely converted into note data and stored, and the stored note data is used to play back a piece of music.

Hereinafter, an embodiment of the award in which the electronic musical instrument according to the present invention is used as an electronic organ will be described in detail.

FIG. 1 is a block diagram showing the configuration of an electronic organ (electronic musical instrument) according to the present invention. In this figure, code 1 is a side, and a magnetic tape 2 on which the music data that is essential for playing the music dedicated to this #frkJl is recorded as a bit string is attached to the bottom of the 6th side 1. has been done.

Here, the recording format of the music data recorded on the magnetic tape 2 will be explained using Figure tJJJ2.

FIG. 2 is a diagram showing the above-mentioned recording format. In this diagram, the start mark 3 is, for example, "00...
・The final bit length called OIJ is composed of serial data of 32 bits (gae is 32 bits), which is +l II, and it reveals the starting point of this music data on the previous magnetic tape 2. At the same time, it is provided to synchronize the clock value for data reading in advance to the data to be read when reading the music data. Note that the final pitch "l" in this start mark 3 is referred to as a start bit.

4 panel data following start mark 3 Data for setting the timbre, envelope, etc. of the music that this electronic organ should generate when playing this music, if you can say, the operation of this electronic organ. The data corresponds to the power of each setting switch on the operation panel, and the fixed pitch) &S
This is the serial data of [.

Transposition data 5 is used to transpose the tsuba of this Okichi data 11 to the actual key, since the sound ^ data 11 (data indicating the sound part of each note composing this song), which will be described later, is always recorded in bars. It is also serial data with a fixed number of bits.

Next, table mark 6 is serial data of the FIT bit number and Ffr bit pattern indicating the starting point of table data 7 (data is information), and code length mark 8 is coded code length data 9 (f conversion). This is bloody IJ data with a predetermined number of bits and a particular bit pattern indicating the starting point of the note data). Here, the table data 7 and the court-shape length data 9 will be explained in detail with reference to FIGS. 1 and 4.

In this electronic organ, it is essential to have the ability to generate tones that correspond to a piece of music, as well as note length data that indicates the note length of each note and rest that make up the piece of music. This note length data corresponds to the note length of each yuzu note or rest as shown in FIG. Note length codes made up of base codes are arranged in one performance of a piece of music.

By the way, in such note length data, if n is the note description that composes a piece of music, then the data sumi will be mourning ``4XnJ'' and going into a big shift. On tape 2, this note length data is combined with each note length code of the note length data in accordance with table data 7 in FIG. Long data 9 is recorded using cedar with reduced data turtle. Below, if we clarify this f: code method, we can change the note length codes used in the square prefix data from the lower to the lower ha for each type of cypress, as shown in Figure 4 (a). Arrange them neatly. This figure 4 (a) is
The convenience class k of the note length code corresponding to the eighth note ((C) in Figure 3 0) is one note higher, and henceforth, the sixteenth note, quarter note, etc.
This example shows note length data whose frequency of use decreases to l- in . Next, for the array of @ and class code length codes in this Av(a), all other bits except the 1 & family bit are 11 or -#! 2 of the last bit
Value Peng J! ! ! 11 and ri different meat-21mwRjm
As shown in FIG. 4(b), a variable length bit code to be fl is assigned to till without adding the bit length starting from the bit length that is one scan shorter (that is, a 2-bit bit code). In this case, since there are two variable-length bit codes with the same bit length, the one with the comparison bit of 10'' is inserted first. Therefore, in this case b1, this variable length bit code is "10""01"
", JIIOJ, ..., "000001". In this way, the note length code and the
& information indicating correspondence with bit code, i.e.
You get a pull.

The magnetic tape 2 contains the same information (a) in the poverty table shown in figures (a) and (b), that is, the note length codes by virtue class arranged in order from the most frequently used to the least frequently used. The array information of rootoj[.

oooJ jololJ "oooOJ...
It is recorded as table data 7 consisting of bit data such as. Next, each note length code in the note length data is converted into a corresponding variable length bit code according to the conversion table shown in FIG. The bit data, which is the eastern part of , is stored on the magnetic tape 2 as encoded code length data 9 by β. In this case, the array l1111 of the variable length bit codes in this coded code length data 9 is of course the same as the array of each code length code in the previous ml code length data (reference 11).

Next, note mark 10 in figure @2 is interval data 1
Serial data of the number of FIT bits indicating the starting point of 1 and the number of bits of the position, and the timbre data 11 are data corresponding to the sound of each note of the music to be treated. This is serial data in which bit code information indicating the sound ^ of each note obtained in transposed case 1 is arranged in order in the order of numbers. Fl'lJ V in this intertone data 11
The flavor of each bit code is that the key code C corresponding to each key on the #1 board is an 8-bit code), which is composed of a note code and an octave code. . Note that these awards and rests are expressed as all-zero bit code information.

In the music data represented by this mzvMA arrangement format, the table data 7 corresponds to the data actual chivalry axis in this explanation, and the encoded note length data 9 corresponds to the friendly adjacent note data, and this code W+J note length data and clef data 1 added to note length data by 1s
1 corresponds to musical note data.

In addition, in the song data format shown in this figure, checkboxes such as @ are provided in i4 in the same recording format to check whether or not this song has been recorded correctly. The figures are omitted.

Next, returning to FIG. Fig. 2 shows the song data provided internally (not shown) and stored in one tube on the magnetic tape 2 when the operator manually runs the Japanese mask 1 without reading the data. This is a circuit to be used in the Kimi format.

This reading circuit 120 signal is supplied to the data temporary circuit 114.

The data demodulation circuit 13 uses the system clock ρ generated by the system clock generator 14,
Separately generate the data component and clock component from the data component of 141J Allocation Cycle 12, and output the previous data component as card data C-DATA and -ISS digital clock component card clock c-CLK, respectively. It is something. However, the relationship between card data C-DATA and card clock 0-cLK is based on the relative timing of card clock C-CLK (pulse signal), as shown in Figure 5 (a) and (b), respectively. , approximately at the center of each bit time of the card data C-DATA.

Data discrimination-8/Pi candidate circuit 15 is data bias circuit f6
13, the card data 0-DATA input in series to the recording format j- shown in FIG. 2 is input to the card clock C! The start mark 3, the table mark 6, the note length mark 8, and the note length mark 1o are each detected from the inserted data, and the start bit at the start mark 3 is read in sequentially using -0LK and the system clock. table mark 6 is W after
The signal P N L (false signal "1") is output until the picn is detected, and the signal P N L (false signal "1") is output after the table mark 6 is detected as 1.
The signal TAB ('''1
"signal)'@output, and one river from when note length mark 8 is detected to when Hiru-sho mark 10 is detected is signal LNG (1
The signal NT ("1") is output from the time the bamboo cylinder mark 1o is detected until the reading of the TF Wt day 11 is completed. The signal PNL becomes a signal indicating that the panel data 4 and the transposition data 5 are interrupted, the signal TAB becomes a signal indicating that the table data 7 is being read, and the signal PNL becomes a signal indicating that the table data 7 is being read. becomes a signal indicating that coded code length data 9 is interrupted,
Further, the signal NT is a signal indicating that the tone data 11 is fully absorbed. In addition, this data discrimination -8/P change circuit 15, in parallel with the above operation, the data discrimination circuit 13
The card data C-DATA supplied from the controller outputs the previous ml signal TAB from the time when the table mark 6 is detected, and the previous ml signal NT is output from the time when the AtJυ beep mark IO is detected. In the dark, data is output as DATA for each number of ph foot pits. In other words, this ★Poor, Data Discrimination-8/Pt Chivalry Circuit 1
5 is a mountain that doubles the signal TAB, for example, the card data C-DATA is converted into parallel data every 4 bits and is used as data DATA.
Card data (!-DA
':l'' A is combined into parallel data for each ijs bit and output as data DATA.

The panel/transposition data register 16 contains i21. This is a register that stores the panel data register for storing the panel data 4 shown at tK, and the Imaichi data register for storing the transposition data 5. Data discrimination -8/P summer!
While signals PNT, . This card data O-D
A? Of these, the data corresponding to panel data 4 is stored in the panel data register in the j-order column, and the data that has been completed is stored as panel data P-DAT.
The card data C-DA is used in parallel as A, and the card data C-DA
Of the TA, the data corresponding to the transposition data 5 is sequentially stored in the transposition data register in series, and the stored data is outputted in parallel as 0-tone data T-DATA.

The RAM (random access memory) 17 stores the table Cheetah in the song data shown in FIG. This is for storing the pitch data 11 and each pitch point of the area where the data of these three types are stored, respectively. The address generator 18 generates address information that specifies a predetermined location in the RAM 17 when the RAM 17 performs convolution creation and readout operations, and is used to generate address information that specifies a predetermined location in the RAM 17. ) table address counter 18&, used to specify a predetermined location in the area where note length data is stored (note length data area); note length address counter 18h1 tone cylinder data Pitch address counter 1 used to specify the FLT construction location in the area (tone part data area) where 11 is stored.
8c1, and an address data counter 18d for specifying the F9Tw landing in a relative (address data area) in which the valley tip meeting point of the note length data area and the bamboo tube data area is stored. The data transfer control 14 + circuit 19 uses the address information generated by the address generator 18 to load data into the RAM 17, read data from the RAM 17,
This is a circuit for controlling the transfer of data that has been extracted to other parts according to predetermined timing, and is also used to temporarily store data that has been extracted from the temporary storage memory 20ti and RAM 17. Rate-landing memory for. What about the RAM 17, address generator 18, and data transfer operations mentioned above? 14) The detailed configuration and operation of the circuit 19 and the temporary memory 2'0 will be described later.

Latte l! 2I Ayu 21 is when playing music (when automatic reconnaissance)
1 from RAM17. A circuit in which each clef code of the material part data 11 to be extracted is loaded sequentially in the order of performance,
When the load number LDI is supplied from the data transfer/decoration circuit 19 to the load terminal LD, the data output from the data terminal of the RAM 17 is loaded.

The latch circuit 22 is configured such that each note length code of the note length data read out from the RAM 17 when playing a song is 1m long for the 11th playback.
When the load signal LD2 is supplied from the data transfer control circuit 19 to the load terminal LD,
The data output from the data terminal of the RAM 17 is loaded.

The shift circuit 23 converts the output of the latch circuit 21, that is, the pitch code (M-(!01) IC), into the transposition data T-DATA (same as the shift data 5) output by the panel/'0 key data register 16. ), the key switch circuit 24 is a circuit that outputs a pitch chord (TO CO S E') that is sensitive to the drama of the song to be played. This circuit consists of key switches housed in correspondence with the needles, respectively, and an encoder that encodes and outputs the outputs of these valley key switches. The code (M-00DK') output from A11k transfer-U route 23 is Norisogata circuit 25 and press ii! The output of the drilling key code circuit 24, that is, the key code (K-
CODIC) is supplied to the tone forming circuit 25.

The musical tone forming circuit 25 has a bamboo tube (Peng wave number) corresponding to the sound code (M-00IIK') outputted by the ea11!1 circuit 23 or the key code (K-COIllC) outputted by the key switch circuit 24, and This is a circuit that generates and outputs a musical tone signal that sets the material color and envelope to 1 corresponding to the panel data P-DATA (same as panel data 4) output by the panel data register 16, and this musical tone forming Lgl path 25. The musical tone signal outputted from the amplifying device 27 is amplified and then emitted from the speaker 28.

Press display h26G-1 is for instructing the position of the key (age) to be pressed to the performance ministry (the paddy i1 ministry of this 汹子Orkan), and it is used to indicate the position of the key (age) to be pressed. The lamp (or the light emitting element of the first light diode temple) provided corresponding to the pair, and the f-edition code M-C! outputted by the MiJ je hook shifting circuit 23! Decode ODE' and start the previous run 1 (
Alternatively, the light emitting device may include a circuit or the like that causes the corresponding one of the light emitting elements to emit light.

Next, the note length code conversion circuit 29 latches (!21 path 2
A circuit for converting the note length code (L-00DK) output by the note length code 2 into a binary value (L-C0DE') indicating the note length (i.e. time) corresponding to this note length code or the number of unit times it has. , a tempo clock T of an arbitrary unit time period generated by the note length counter 30Fi and the tempo clock generation Sushi 31.
- A two-round counter for counting OLK and a case comparator circuit 32 use the binary value (L
-00DK') and the #f number peaks output by the note length counter 30! By comparing N Tl, the time corresponding to the note length is determined by H)7! This is a circuit that checks whether or not it has been done. Here, the erasure note length counter 30 counts the tempo clock T-(!LK supplied to the clock input terminal CK, and is cleared by cello when a 1" signal is supplied to the reset input terminal R. It has become.Compare also four roads 32
is a signal i Q ("l") from the comparison output terminal C only when the value of the data input to the first data input terminal ^ and the value of the data input to the second data input terminal B are equal.
signal) is output.

To briefly describe the other parts in FIG. 1, the delay processing unit @33 delays the card data C-DATA supplied to the input terminal a by a time T1 using a system clock. A circuit that outputs from 4 children,
The linked circuit 34 converts the output of the exclusive or gate circuit 35, which is supplied to the input terminal pre-charge, to the system clock ρ.
This is a circuit that uses a delay time T2 to abrade and then outputs the result from the output terminal. Further, when the preset human power Yako Psi/C "l" signal is supplied, the bit counter 36
is preset, and the previous card clock C-CLK is also supplied to the clock input terminal OK! This is a counter that performs tI2. - Also, the terminal 37 is the one to which the signal 100 is supplied, and the terminal 38 is turned on only when the electronic organ is made to play music (i.e., the automatic w1°C). This is an alternate switch (regeneration switch).

The details of the configuration of the RAM 7, the address generator 18, the data transfer control circuit 19, and the temporary storage memory 20 in FIG. 1 and the detailed operation of the entire circuit shown in FIG. 1 will be explained below with reference to the circuit operation. I'll explain.

First, the music data recorded on the magnetic tape 2 is
I will start by explaining the awards stored in AMI 7.

First of all, the regeneration switch 38 is set to 1, so the signal PLAY is a 10" signal. This signal PLAYtI'i is supplied to the data transfer control circuit 19, and the data transfer control circuit 19 is L-f)
ct! i'@P L A Y Ka"O"414 M -
In Ch 1+], the reading circuit 12 always reads the music data read from the magnetic tape 2 immediately.
The state is set such that it can be stored in AM17. Signal PL^ again! is supplied to the 10,000 input terminal 391 of the OR gate circuit 39 via the inverter 37, and the output of this OR gate circuit 390 is supplied to the reset input terminal R of the note length counter 30. Therefore, the signal PL AY is Il
O'' signal, the @1'' signal is supplied to the reset input terminal R of the note length counter 30, and as a result, the note length counter 30 is cleared to zero.

Further, the system clock generator 14 constantly generates a system clock, and the tempo clock generator 31
constantly generates a tempo clock T-OLE with a unit time period set by the operator.

Next, if the operator runs the a11 side 1tt of this electronic musical instrument, the reading circuit 12
1i1 magnetic tape 2 may be IIc as shown in Figure 2.
The Ic off-format music data is sequentially read and the read data is supplied to the data recovery II1 circuit 13. Therefore, the data demodulation circuit 13 outputs the music data to card data 0-DA in the order of the recording format.
It is output in series as TA, and data discrimination -8/P/
The signal is supplied to the conversion circuit 15. Hereinafter, the (9) action performed for this award will be explained in order.

First, when the data demodulation circuit 13 outputs the card data 0-DATA corresponding to the start mark 3, the data discrimination-8/P/conversion circuit 15#i outputs the card data 0-DA corresponding to the start mark 3.
Start mark 3 is detected from the bit pattern of TA. Then, the data discrimination -8/P/converting circuit 15 outputs a signal FIL (@l'' signal) from the time it detects the start bit at this start mark 3, and supplies it to the panel/transposition data register 16.Panel/ The 1Ik11 data register 16 reads the card data o-n'X'Ai supplied from the data tllli111 circuit 13 to which this signal PMII is supplied, and reads the card data 0-DA'll' of this. Data corresponding to panel data 4 is stored in the panel data register and output as panel data P-DATA, and data corresponding to transposition data 5 of the card data Q-DATA is stored in the transposition data register. Output as transposed data T-DATA.

Next, when the card data O-DATA corresponding to the table mark 6 is supplied to the data discrimination-8/P& conversion circuit 15, the data discrimination-s/pf conversion circuit 15 converts the bit pattern of the card data 0-DATA. The table mark 6 is detected based on the table mark 6, and from this detection point on, the signal PIJL
Instead, a signal TAB (@r scratch signal is output. This signal TAB is supplied to the data transfer control circuit 19.

The data transfer control i41 circuit 19 is supplied with the signal TAB.
When the address generator 18 is started, the value ``open'' is output to the address generator 18, and this value [φ'' is preset in the table address counter 18& in the address generator 18.

Next, the data transfer control circuit 19L1 outputs the count output of the table address counter 18& to the address input terminal AD of the RAM 17.

On the other hand, the data transfer control circuit 19 starts counting card clocks 0-0IIK from the time when the signal TAB is supplied, and when it has counted four card clocks 0-CLK,
In other words, the data discrimination-3/P tear exchange circuit 15 takes in the first 4 bits of table data 7 (in the example shown in Figure 84 (A), the note length code is "0010") and outputs them in parallel as data DATA. At this point, a write command signal Wl is output. At this time, since the data terminal of RAMI 7 is supplied with the data DATA output from the data discrimination-8/Pf conversion circuit 15, the first 04 bits of the table data 7 (for example, "o OI Oj) is written.

When this write operation is completed, the data sending control circuit 19 increments the table address counter 18&. As a result, the address input terminal D of the RAM 17 is supplied with the value country. Then, when the data transfer control circuit 19 counts four more card clocks 0-OLE, it outputs the write command signal W1 again, and at this time, the data discrimination-j's/P grouping circuit 15 outputs the data DA.
2 in the table data 7 output as TA
In the example of 4 bits (0 in Figure 4), [o o o o
j) is loaded into location 111 of RAMI 7, and when the loading operation is completed, the table address counter 18& is incremented. Data is transferred in the same way below.
The control circuit 19 sequentially loads each 4-bit code in the table data 7 into the RAM 17. Therefore, in this case, if the table data 7 has an arrangement of note length codes as shown in FIG. 4 ((a)), each of these note length codes is arranged as shown in FIG. The information will be stored in correspondence with each address.

After all the table data 7 has been convoluted into the RAM 17, when the card data 0-DA'l'm corresponding to the note length mark 8 is supplied to the data discrimination-8/P conversion circuit 15, the data discrimination -8/P Henkei Igl Road 15, Signal T
A signal hwa (@f signal) is output instead of AB. This signal LNGt;t is supplied to the data transfer control circuit 19 and the input terminal of the inverter 40, respectively.

When the signal LNG is supplied, the data transfer control circuit 19 first outputs the value "Xl" to the address generator 18, presets this value "country" to the address data counter 18d, and then outputs the count from the table address counter 181L. (This '@' presets the area where the table data 7 is written in the RAMI 7, that is, if the table data area's end location is address 1, it is ``i+lJ'') in the note length address counter 18b.

Next, the data transfer control circuit 19 converts the count output (in this case, the value rXl) of the address data counter 1811 into RA.
It is output to the address input terminal Muff of MI 7, and the count output of the note length address counter 18b (in this case, the value 1'
-i+lJ) is output to the data terminal of RAMI 7. Next, the data transfer control circuit 19 outputs a write command signal W1 to the RAMI 7. As a result, uiM1
The value "1+1" is written in the lil area of 7. When this write operation is completed, the data transfer control circuit 19 increments the address data counter 18d, and also outputs the count output of the note length address counter 18b to the address control circuit D of R11a17.

- Before the 10,000 signal LNG is output, the signal @0'' is supplied to the inverter 400A power terminal, so the output of the inverter 0'' supplied to one input terminal 41 & of the OR gate circuit 41 is ''' The ``1'' signal and the signal supplied from the output terminal of the OR gate circuit 41 to the preset input terminal P8 of the bit counter 36 were always fixed at ``-2''.

Hereinafter, the operation of the bit counter 36 after the output of the signal TJIG and the circuit operation performed based on the count output OMT2 of the bit counter 360 will be explained using the coded code length data 9 [lOJ "110J "0001"...・・・
In the case of an edible length bit code array of . This will be explained with reference to the time chart shown in the figure.

In FIG. 6, 0) corresponds to the first edible length bit code "lO", the second variable length bit code "110" and the third variable length bit code "ooolJ" in coded code length data 9. Card data 0-DAT
The waveform of A is shown, and (b) of the same figure shows the card clock 0-OL.
It shows E.

Here, first, the signal LMGFi, the bit preceding the first bit of the card data O-DmTm (the bit indicated by code 1 in FIG. 6(a)) corresponding to the coded code length data 9,
In other words, the last bit of the note length mark 8 (this bit is already shown in FIG. 6 (b), and this bit is assumed to be temporary KroI) is the point in time when the corresponding card clock 0-OXrK is output ([time t0) That is, from the time when the IWlIIIk final bit is read into the Dbit-8/P conversion circuit 15, the signal becomes @l'' (see tlpJ6 (c)).

This signal LNGFi is supplied to one input terminal 411L of the OR gate circuit 41 via the inverter 40. At this time, the other input terminal 41b of the OR gate circuit 41
The output of the OR gate circuit 41 shifts from the 11" signal to the 1o" signal because the Fi'"0" signal is supplied to the 11" signal. As a result, the pit counter 36 can perform counting operations from time t0. Also, at this time ~, there is a butterfly on the clock input terminal OK of the bit counter 36.
Since the card clock O-OLJ corresponding to the symbol b) of the final bit (FIG. 6 0) is supplied, the bit counter 36tillj immediately counts the card clocks 0-0-IL. As a result, the stitch count output 0NT2d of the bit counter 36 immediately changes from the value "-2" to the value "-1" (see FIG. 6).

Next, at time -, card data 0-DATA corresponding to the first bit of the first variable length bit code O in the coded code length data 9 (symbol a in FIG. 6(A)) is output from the data demodulation circuit 13. When output, at this time t1, the card data C→MU becomes the ""O'"O'" signal.
Stand up to Fugo. This card data 0-DATA! ,
The signal is supplied to one input terminal 35& of the exclusive OR gate circuit 35, and is also supplied via the delay circuit 33 to the other input terminal 35kl of the exclusive OR gate (9). Therefore, from the output terminal of this exclusive-or gate circuit 35, at time t1
A pulse-like signal S35 which becomes a 1f signal with respect to time 10 is output (see Fig. 2), and this signal 835 is
The data transfer control circuit 19 ignores the signal 835 generated at time t1. That is, the data transfer control circuit 19 transfers data within a predetermined period immediately after the signal LNG is generated (for example, card data C-DATA c/1 bit time @
signal 835 within the corresponding period) is ignored. In addition,
This signal 835 is not generated at time t1 if the code b) of the last bit of the code length mark 8 (FIG. 6 0) is "■". Further, at this time, the signal 835 outputted from the exclusive OR gate circuit 35 is supplied to the -000 blade input terminal 42& of the AND gate circuit 42 via the delay circuit 34. However, the other input terminal 42bK of the AND gate circuit 42 receives the least significant bit signal M of the count output OMTZ of the bit counter 36 via the inverter 43.
BB36 is supplied, and this most significant bit signal M8
Since B-36 is an 11" signal at this time (because the count output CNT2 of the bit counter 36 is F-IJ at this time), the output of the anti-game path 42 remains a 10" signal. Therefore, at this time, the 11" signal is not supplied to the other input terminal 41b of the OR gate circuit 41, and therefore, at this time t1, the bit counter 36 is mr-
It is never preset to 2J.

Next, at time 1, the card clock O-OLK corresponding to the first bit code of the first variable length bit code in the coded code length data 9 is transferred from the data recovery path 1iIIN path 13 to the card clock O-OLK corresponding to When the output is 36 bits counter this card clock.

-0LE is counted, so the counting output OMT2amr
-IJ to value rot K! .

Next, at time ts, the data demodulation circuit 13 outputs the card data po-DA corresponding to the 211th bit of the first variable length hit code in the coded code length data 9.
When the TA starts to appear, the card data 0-DATAtfill'' signal changes to a 10'' signal at time t1. As a result, exclusive or gate (9
) The signal at one input terminal 35& of path 35 changes from @l'' signal to "d" signal Kf at time t, and the other input terminal 5sbo multiplier changes from 11" signal to "0" after time Tl from time t. Changes to a signal. Therefore, a signal 835 which becomes the @1'' signal from time t1 to time T1 is output from the output terminal of the exclusive or gate 4-way 35. When the data transfer control circuit 19 is supplied with this signal 835, , provided that the signal IING is supplied.
Bit counter 360 count output OMT2 (count value at this time is "0...0") card data pa-
Data with DATA (value rOJ at this time) added as the least significant bit, that is, the value "0...OOJ" is supplied to the address input terminal AD of the RAM 17 via the address generator 18. As a result, the data at address 1700 in the RAM Data "oolo" (see FIG. 4) is read out and output from the data terminal. Next, the data transfer control circuit 19 sends a write command signal W2 to the temporary storage memory 1J20.
Output. As a result, the temporary storage memory 20 stores the data “
0010'' is stored. Next, data transfer control circuit J
ut, count output of note length address counter 18b in address generator 18 (here company value [t+1j)
is output to the address input terminal M D of the RAM 17, and then a write command signal W1 is output to the RAM 17.

In this case, since the data stored in the temporary memory 20 is supplied to the data terminal of the RAM 17, the data [o OI OJ-] is stored at address (1+1) of the RAMI 7. . Next, the data transfer control circuit 19 increments the mark length address counter 181).

On the other hand, the signal B35 generated at time t1 is delayed by time T3 and supplied to one input terminal 421 of the AND gate circuit 42. At this time, the signal supplied from the output terminal of the inverter 43 to the other input terminal 42bK of the AND gate circuit 42 is an 11'' signal because the count output of the bit counter 36 is ``q''. Therefore, a pulse signal of '1' is output from the output terminal of the AND gate circuit 42C after a time t1. As a result, the same bit counter 36 is again preset to r-2JK.

Next, at time t, when the card clock 0-OI, K corresponding to the 211th bit 4 [Ql of the first variable-length bit code is output from the data transfer control circuit 13,
Bit counter 36 is this card clock 0-OXaK
Since it counts, the same bit counter 360 count output OM
The Tltj value "-2" becomes the value "-1".

Next, at time tJtc, the card data C-DAT corresponding to the first bit "υ" of the second variable-length bit code is
When the signal A starts to be output, the exclusive OR gate circuit 35 outputs the signal 8 by the same operation as in the first operation described above.
35 is output. This signal 835 is supplied to the data transfer control circuit 19, and the data transfer control circuit 19
The signal 835 generated at this time 1° is ignored. That is, in this case, the data transfer control circuit 191i uses the signal 835 generated this time as the signal 835 generated last time.
If only the time has elapsed from 1 bit time of card data 0-DATA, then it is now l! 21 Ignore the signal generated by 835 companies. Also, the gi number 835 generated at time t is converted to 8 in time and is supplied to one input terminal 421 of the AND gate 42.
The other input terminal 4Zb of this # same AND gate circuit 42
Since K is supplied with the @0” signal (at this time, the bit counter 360 count output 011TT! is “-λ”)
), the bit counter 36 is never preset to "-2".

Next, at time ta, the second variable length bit 0-
When OLK is output, the bit counter 36 counts this card clock c-ax,t, so the count output ONT2 of the bit counter 36 changes from the value "-1" to the value roJ.
K becomes.

Next, at time t7, the second bit of the 211th variable-length bit code "υ" corresponds to the card clock O-C.
:LK is also output, the bit counter 36Fi counts the 0-01 sections of the same card clock in the same manner as described above. Therefore, bit counter 360 count output ON'
i'2 becomes the value [lI from the value 'side.

Next, at 1 o'clock -DM! The signal ``l'' changes from the ``l'' signal to the ``om a'' signal. As a result, the exclusive or game 11 path 35 outputs a signal 835 in the same manner as described above. The data transfer control circuit 19 When this No. 16 835 is supplied, the signal I
, NG is being supplied, the count output of the cut counter 36 is 0NTO (the count value at this time is "0...
...01") K card data 0-DA'l' (the value at this time is A) is added as the least significant bit, that is, the value "O...-0l0J" is sent to the address generator. 18 to the address input terminal AD of RAMI 7. As a result, data [ozozJ (see Figure 4) is read from address 2 of RAM 17 and output from the data terminal.
A path 19 supplies a convolution command signal W2 to the temporary storage memory 20.
Output. As a result, the temporary storage memory 20 stores the data “
ozozJ is written.

Next, the data transfer control circuit 19 inputs the note length address color/
The counting output of ri 18b (in this case, the value ri + 2J) is
It is output to the address input terminal p of AM17, and then the write command signal W1 is output. In this case, since the data stored in the temporary storage memory 20 is supplied to the data terminal of the RAMI 7, the data "0101" is written to address (1+2) of 11M17.

Next, the data transfer control circuit 19Iri code length address counter 18b is incremented.

On the other hand, the signal 835E generated at time t, time T
8 and one input terminal 4 of the AND gate circuit 42
2&, and the other input terminal 42b of the AND gate (b) path 42 receives a
A "1" signal is supplied (because at this time, the count output 0NT2 of the bit counter 360 is the value "l").As a result, from the output terminal of the AND gate circuit 42, from time t to time T, after ""l" A pulse signal is output, and this pulse signal is supplied to the preset input terminal ps of the bit counter 36 via the OR gate circuit 41. Therefore, the bit counter 36 is again preset to "-2".

Below is l! ! 1, to time, t,,1tr1,t1
! In the data recovery circuit 13, the bit counter 36 counts these card clocks 0-OLK every time the card clock low 01 section is output. and the time til
+, when the output of the card corresponding to the second bit [l of the third variable length bit code starts and the signal 835 is output, the data transfer control 11
The 14th path 19 outputs the stitch count output CλT2(of the bit counter 36 at this time) on the condition that the signal LNG is supplied.
In this case, the data is the value [0...0IOJ) with card data 0-DATA (arlJ in this case) added as the least significant bit, that is, the data "0...
0101J to RAM via address generator 18
Supplied to the address input terminal AD of I7. This result R
The data “oxooJ” (see FIG. 4) at the address AM17 is read out. Then, the data transfer control circuit 19 outputs a write command signal w2 to the temporary storage memory 20. As a result, the data “oxooJ” (see FIG. 4) is read out from the address AM17. The data “010
0" is written. Next, the data transfer control circuit 19t
f, the count output of the note length address counter 18b (in this case, 1kri+3J) is outputted to the address input terminal AD of the RAM 17, and then the write command signal 11 is outputted.

Therefore, the data "
oloo" is written. Then data transfer III
The control circuit 19 increments the note length address counter 18b.

Thereafter, by exactly the same operation, each variable length bit code a after the fourth variable length bit code in the coded code length data 9, the address of the address where the corresponding code length code in the table data area of the RAM 17 is stored. The address data is converted into data, and the corresponding note length code is read out using this address data.
The data written to the memory 2° and stored in the temporary storage memory 2° is written to the address of the RAM 17 pointed to by the note length address counter 18b each time. Thus, RAMI 70 (1+1).

After the address, corresponding code length codes are written in the order of each variable length bit code in the coded code length data 9.

Next, the pitch mark I is placed on the data discrimination-8/P@conversion circuit 15.
OK compatible card data O-DM! When the signal NT is supplied, the data discrimination-8/P conversion path 15 detects the pitch mark 10 based on the bit pattern of the card data 0-DATA, and outputs the signal NT from the time of this detection.

At this time, the signal LNG is used for data discrimination -8/P@:
At the time when the conversion circuit 15 detects data indicating the end of the coded code length data 9 (for example, it may consist of continuous data of a predetermined number or more bits), the data has already stopped being output. .

When the signal NT starts to be supplied to the data transfer system 19tlj, the count output of the note length address counter 18b in the address generator 18 (this count output is transferred to the area in the RAM 17 in which the note length data is written,
In other words, if the note length data area's Soju address is address j, the value "j+1" is preset in the pitch address counter 18o, and then the count output of the address data counter 18& (this value "x -14'') is output to the address input terminal M D of the RAM 17, and the count output of the pitch address counter 18o (in this case, the value rj+IJ) is output to the data terminal of the RAM 17. Here, the data transfer control circuit 19 outputs a write command signal w1 to the RAM 17. As a result, RAM1
The value rJ+lJ is written to address (X+1) of 7. When this write operation is completed, the data transfer control circuit 19 transfers the count output of the pitch address counter 18oO to the RAM 17.
output to address input terminal 5p.

On the other hand, the data transfer control circuit 19 starts counting the card clock 0-OLK from the time when the supply of the signal NT is started, and calculates the card clock 0-OLK based on the number of bits of each pitch code in the pitch data IIK (for example, 8 bits), that is, the data discrimination-8/F conversion circuit 15 takes in the first pitch code and converts it into data DA.
At the time when TA is output in parallel, a write command signal w1 is output. At this time, the data terminal DKIfi of RAM17
Data discrimination - data D output by the FJ/P conversion circuit 15
Since the ATA is being supplied, the first clef code in the pitch data 11 is loaded into address (j+1) of the RAM 17. When this loading is completed, the data transfer system #(9) path 19 is loaded. , the pitch address counter 180 is incremented.As a result, the value "j+2" is supplied to the address input terminal M°C of the RAM 17.Hereafter, according to the operation exactly the same as that described above, the RA
After address (j+2) of M17, the second and subsequent pitch codes in the pitch data 11 are sequentially stored.

Then, all pitch codes in pitch data 11 are P
When written to the AMI 7, the data discrimination-37P conversion circuit 15 detects data (not shown) indicating the end of the same pitch data 11 and stops outputting the signal N'l'O. Check whether the music data has been read correctly using the subsequent check information, etc.,
If it is normal, reading of all music data is completed.

Next, when the playback switch 38 in FIG. 1 is closed, the data transfer control circuit 19 controls the address generator. The address data counter 18 (1) at 18 is preset to the value 1, and the address data counter 1B (L (D) count output is set to PAM
It is output to the address input terminal AD of I7. This result R
AMI 7f:) f-I'm child Dh et al. rule RhM17t
The data stored in vX address Kk2 (in this case, the value "i"
+lJ) is output. Data transfer control circuit 19#'
i This data "1+1" is stored in the note length address counter 18b.
Preset to . Next, the data transfer control 1 circuit 19 increments the address data counter 18.

As a result, from the data terminal of RM M17, the (
The data (value rj+lJ in this case) stored at address X10:L) is output.

The data transfer control circuit 19 presets the pitch address counter 18ok with this data rj + IJ.

Next, the data transfer control circuit 19 sends the count output of the pitch address counter 1800 to the address input terminal of PAMI7.
D, and output the load signal LD to the latch circuit 21.
Outputs I. As a result, the latch circuit 21 only has a memory M.
]7, the data stored at address (j+1) (ie, the first pitch code) is loaded. Next, the data transfer control circuit 19 increments the pitch address counter 180 and increments the note length address counter 18b by 1.
The number output is outputted to the address input terminal AD of the RAM 17, and a load signal LD2 is outputted to the latch circuit 22. As a result, the latch circuit 22 has (1+) of the RAM 17.
1) The data stored at the address (ie, the first note length code) is loaded. Next, the data transfer control circuit 19 increments the mark length address color/input 18b.

The data loading operation to the latch circuits 21 and 22 described above is instantaneously performed. The first pitch code loaded into the latch circuit 21 is then transposed in the shift circuit 23 and supplied to the rear tone forming circuit 25 and the push*6 indicator section 26, respectively. As a result, the speaker 28 has a pitch corresponding to the first ringing pitch code and the panel data P
- A musical tone having a timbre and envelope corresponding to the DAT tune starts to be generated, and before the final stage, the lamp of the key corresponding to the first pitch chord starts to light up.

On the other hand, the first note length code loaded into the latch circuit 22 (in this case, the value "ooloj is the note length code (L-00
DI) to the code length code conversion circuit 29.

Therefore, the code length code conversion circuit 29 outputs a binary value (L-coDI') indicating the number of unit times of the note length (time) corresponding to the first note length code, and the comparison circuit 32 1 data input terminal A.

On the other hand, the signal PLAY is inverted by the inverter 37 and supplied to one input terminal 391 of the OR gate circuit 39. In addition, in this case, the llO'' signal is supplied to the other input terminal 39 of the OR gate circuit 39 (because at this time, the ON'l'l' signal is supplied to L-OODM'.
)L/ Therefore, the note length counter 30 starts counting the text/record clock T-OLK from the time when the signal PLAY is output. When the binary value (L-CODK') corresponding to the first note length code and the count output 0NTI of the note length counter 30 match, a signal IQ is output from the comparison output terminal C of the comparison circuit 32. is output. This signal IQ
clears the note length counter 30 to zero via the OR gate circuit 39. Furthermore, the data transfer control circuit 19 receives this signal I.
When Q is supplied, note length address counter 18b1 and note cylinder address counter 18o are each incremented, and RA
The second pitch code stored in the (J+2) incense is read from M17 and loaded into the latch circuit 21, and the R
The second mark length code stored at address (i+2) of AMI 7 is read and loaded into the latch circuit 22.

As a result, the sound from the speaker 28 corresponds to the soft initial pitch code. After the musical tone is produced for a time corresponding to the first note length chord, a musical tone corresponding to the second pitch begins to be generated, and the key press display &26 corresponds to the first pitch code. After the lamp of the key corresponding to the first note length chord is lit for a time corresponding to the first note length chord, the lamp of the key corresponding to the second pitch code starts to be lit.

Thereafter, following exactly the same operation, pitch codes and note length codes are sequentially read out from the RAM 17 in the order of performance, musical tones corresponding to these pitch codes are played for a time corresponding to these note length codes, In addition, the lamps of the corresponding keys on the movement board are lit in the order in which they are played.

In addition, in this example explained above, only note length data and pitch data were used as musical note data, but
This note data includes garrigado note length data that shows the note length of each note in the oblique part of the song, opligado pitch data that shows the pitch of each instrument in the obbligado part of the song, and the types of chords in the accompaniment part of the song. Of course, it is also possible to add chord data, etc. shown.

As is clear from the above explanation, according to the electronic music according to the present invention, there is a recording medium on which music data including data conversion information and converted note data is recorded, and music data is extracted from this recording medium. A reading means, and an inverse conversion memory that stores data conversion information based on the output of this European removal means, and uses the stored data conversion information to inversely transform converted musical note data into musical note data and store it. and a playback means for reproducing a piece of music using the note data stored by the inverse conversion storage means, so even if a long piece of music is recorded on a recording medium with a limited storage capacity, the recording capacity can be reduced. It is possible to record music data extremely efficiently without increasing the amount of data, and it becomes possible to perform music playback such as automatic performance using this extremely efficiently recorded music data.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an embodiment in which the electronic musical instrument according to the present invention is applied to an electronic organ, Fig. 2 is a diagram showing the distribution format of music data in the same embodiment, Fig. 3 Figure 4 shows the correspondence between notes, rests, and note length codes. Figure 4 shows the correspondence between note length codes, variable/bit codes, and memory notes. Figure 3 shows the card data 0-DAT.
FIG. 6 is a time chart showing the relationship between A and card clock 0-OL[, and FIG. 6 is a time chart for explaining the circuit operation in the embodiment shown in FIG. 1...L1 side, 2...Recording medium (Mi tape), 12...Reading circuit, 13...Data demodulation circuit, 15...Data discrimination -8/P switching circuit, 17...RAM (random access memory,
18...Address generator, 19...
Data transfer control circuit, 2゜...temporary storage memory,
21.22... Latch circuit, 25... Tone formation circuit, 26. Song key display section, 33.34...
Delay circuit, 36...bit counter. Applicant Nippon Raku! ! Manufacturing Co., Ltd.

Claims (1)

[Scope of Claims] (1) [Existence] A combination of adjacent note data that can be served by changing the f-row data for each note pseudo-rate information, and the data that contributes to making the data change faster. A recording wire rod in which iron data including data and chivalry information is stored, and music data including 'ff1J distribution data from the f91 recording medium and data quality chivalry information and previous d'collection of chivalry data. A rainbow-retrieving means for reading the information, ■ stores information on the data sampled by the previous aC-retrieval means, and uses this stored data change information to read the data by the #1 distribution ΦC-retrieval means. Inverse conversion storage means for storing the f@ circular note data into the note data, ■Punishment 1 stored by the pre-delivery conversion storage means! An electronic musical instrument characterized by being equipped with an external means for reproducing a string tune using note data. (2) The reduction data paternal information is to transfer the useful amount of money to the unit code with fewer pits f: g8
An electronic musical instrument according to claim 1, characterized in that it is a variable length code conversion table that converts musical note element information that is infrequently used into a unit code with a larger number of bits. (8) In each of the above unit codes in the @allocation variable length code conversion table, the values of all other bits except the mosquito end bit are 2@klil of the Shiganken bit! The same 2111i1 that is different from ii Burihan! The electronic musical instrument according to claim 2, characterized in that the electronic musical instrument is an edible long bit code having a logical value. (4) The reproduction means may include key press instruction means for instructing key press positions on the keyboard, musical tone generation means for generating musical tones corresponding to the note data, or both of these tsutsumugi instruction means and musical tone generation means. An electronic musical instrument according to any one of claims 1 to 3, characterized in that the electronic musical instrument comprises: