JPS58128096A - Memory clear system - Google Patents

Abstract

PURPOSE:To reduce the clear processing time at memory exchange, by clearing only a memory block detected with a parity error and accessing the next a block after skipping a block where no readout data is obtained even with the access for readout. CONSTITUTION:In converting a block BL1 of a stage ST1, the memory clearing is started from the readout of a stage ST0 to the block BL0. An MPU restores the vlaues in a stage ADR(address) counter and a block ADR counter to the initial value and counts up the value simply, then it is required for the time reading out all the data in the block even if the block BL0 is not mounted. Thus, whether or not the BL0 exists is checked at first. If mounted, the data of the BL0 is read out parity check is done. When no parity error exists in the block, the block ADR is incremented to read out the next block BL1.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a large-capacity memory. ``Regarding an effective rear method when changing.

(2) Background of the technology If there is an error in the read data of the memory, rewriting will be attempted, but if the error still occurs, it is an 8-card failure and there is no other choice but to replace the memory.The parity of the memory part where the memory was replaced There is no guarantee that this is correct (in general, there is a probability of a parity error of 50-50), but if you run the program t-41, the parity error will automatically disappear. However, a parity error occurs because the work area for saved data, which is not a target for program loading and is not a target for data writing, is up to 1 at the time of exchange. If the microprocessor (MPU) starts operating with this work area t as it is, a parity error will be detected when the core work area is exposed, and the system will go down. To avoid this, clear the memory of the replaced memory.

By the way, when the main memory becomes large in capacity, the main memory becomes composed of multiple memory chips (one set of a circuit) mi! Assuming a structure consisting of a plurality of IF@ memory stages (also called banks), exchange is performed in units of memory stages or in units of memory chips. In this case, we will refer to this exchange unit as a memory block. To give a numerical example, 1 memory stage is 1
In the case of 28KB, the memory size is 8KB.

(3) Conventional technology and problems When replacing such a large capacity memory, clearing is not required when replacing n7
(It is desirable to target only memory processors.

This is because it takes time to completely clear the entire memory space, and there is a desire to preserve data stored in memory blocks that have not been replaced. However, the only program that notifies the t-cPU to clear the memory when memory is replaced is a basic program stored in read-only memory (ROM), and conventionally it was simple to simply clear the entire memory space. Therefore, it is not possible to meet the above request.

(4) Purpose of the Invention 1JIN is an attempt to make it possible to quickly clear only the memory program that has been substantially replaced without complicating the above-mentioned memory clearing program in the ROM. .

(9) Structure of the Invention The present invention provides a clearing method for a large-capacity memory that includes a plurality of sets of memory processors and memory processors as replaceable units, and in which the address space also includes the address area of non-implemented memory.
When converting memory, parity check for all memories,
If a parity error is detected, the entire memory block to which the memory address belongs is cleared, and if there is no read attack 9 data, all addresses in the memory block to which the memory address belongs are skipped and the next one is executed. It is characterized by checking the parity of memory block addresses.

(6) Embodiments of the Invention The present invention will be explained below with reference to illustrated embodiments. Figure 1IE1 is a professional diagram of a processing unit that uses large-capacity memory as its main memory, and MPU is a microprocessor.
Floppy disk as PH loader, 8TO-11
Tm is a memory stage included in the main memory M8, BLe
-BLn is a memory processor, which constitutes each memory stage; in this example, it is a memory chip. 1 Memory Pro, RiBL
The capacity of i (1=o~m) is, for example, 4KW (W is a word, here 1 word is 2 bytes), and a maximum of 64KW is implemented in one memory stage 8Tj (j=0~m). . The number of stages m is, for example, 16, which constitutes the main memory MSt of MW order as a whole. However, professionals at each stage,
However, not all functions are necessarily implemented, and some functions of the system have been removed. For example, if an automatic deposit/withdrawal device has only a withdrawal function but no deposit function, the relevant deposit function may be removed. Additional memory blocks are not implemented. An area 8 indicated by a broken line on the stage 8T1 is such an unmounted area. Considering the address space, 64 is the memory address /a0000~FFFF, which is represented by 16 over 4 bits, and the memory address space is 4, and the address space is 1/a0000 to FFFF.
161: occupies K, so there is a free friend address space that is an integral multiple of 1/16.

FIG. 2 is a 70-chart showing one embodiment of the present invention. The clearing operation at the time of memory replacement will be explained below with reference to this figure. In the jlI diagram, stage sT director's professional, RiB
LI is converted to 9. Memory clear is stage 8T
・Start with reading from the professional BLe. Reading has two meanings. One is Memory Pro, RiBi2
It is used to determine whether or not it is implemented. Tsuma lj
The MPU is a station DR (address) counter and a pro.
Since the value of the RAM DR counter is returned to the initial value and simply counted up from there, it takes time to read out all the data in the block even if the PRO or BL is not installed. Therefore, first, it is determined whether or not Pro BL is implemented. If it is installed, the program reads the data of the RI-BL and performs a parity check. If there is no parity error in the block, the block DR is uploaded and the next block BL1'i is started.

This is also done in the same way as for Pro and BL. This is repeated for all pros, until BLn, and for all pros at stage 8T.

If there is no parity error (block WND),
Stage ADRt-a, pre-The same stone massing is performed in the next stage STl. Stage ST, block B
Since the LI was replaced, a parity error is detected there (probably 50 whispers should have caused a parity error). Clear the memory only in this case. This clearing is not necessarily limited to writing all 0s, it is sufficient to write some data, and the attached circuit is activated by writing data.
Balitipi.

The parity is OK because the bits are added.

After that, memory read and parity check are repeated block by block, but unimplemented area A like stage 8Tl
When R exists, no data is obtained even if it is accessed, so we know that it is unimplemented. By simply adding block DRt-+1, the continuation and haritice for all addresses of the block are omitted. Finally, when the final step of stage STm, BLn, is reached, the entire process ends.

(7) Effects of the Invention As described above, according to the present invention, if a parity error is detected and the memory processor clears the memory and no read data is obtained even after the ninth read access, Since the transfer is skipped and the next block is accessed, the clear exit time when exchanging memory is shortened, and there is no need to worry about erasing all the data in the memory. In the method of the present invention, if a parity error is detected even in a non-switching program, the program is cleared, but if it is normal, there is no parity error in the non-switching program. If this is the case, it is necessary to clear the defective program, clear it, and re-load it.

[Brief explanation of the drawing]

Figure 1 shows 1! of large capacity memory! FIG. #4 and FIG. 2 are Jiro charts showing one embodiment of the present invention. In the figure, MS is a main memory, s'ro to 5Trth are memory stages, and BL to BLn are memory processors. Applicant Fujitsu Limited

Claims (1)

[Claims] Equipped with multiple sets of memory blocks as replaceable units,
In addition, in the clearing method for large-capacity memory where the address space includes the address area of non-implemented memory, when converting the memory, a parity check is performed on all memories, and if a parity error is detected, the corresponding memory address is Clear the entire Memory Pro to which it belongs,
This memory clearing method is characterized in that when there is no NIL data, all addresses in the memory processor to which the concerned memory address belongs are skipped, and a parity check is performed on the address in the next memory processor.