JPS6091482A - Memory management system - Google Patents

Abstract

PURPOSE:To cope with reception of data from each terminal by means of a buffer memory of a prescribed capacity by dividing the buffer memory into plural cells and allocating dynamically these cells to each terminal device. CONSTITUTION:A control part checks how many cell parts are already used with the data related to (a terminal device of) an address A through a cell use counter part UC. A numeric character 2 is set to a counter CA and therefore data Q is stored to both cells CL1 and CL2. Then the sizes of residual parts of both cells CL1 and CL2 are checked by a writing pointer WR2 of a pointer part WA and the final address E (known already) of the cell CL2. The sizes of said residual parts are smaller than the side of received data D, a flag F3 where a numeric character ''0'' is set is retrieved within a cell control flag part MF. Then the data D is written to a cell CL3 designated by a flag F3.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a memory management method for managing reading and writing of data in a buffer memory.

(b) Prior Art and Problems A system that collects data from multiple data sources;
For example, in a system that collects data from a group of terminals at a center, a method is adopted in which a buffer is provided for each terminal at the center and data in each buffer is sequentially read and processed. Normally, the amount of data sent out from a terminal is variable, while the speed at which data is read from each buffer is constant. Therefore, when the amount of data sent from a certain terminal device exceeds the amount of data read out of the buffer, data overflow occurs in the buffer allocated to the terminal device. In order to avoid this, it is sufficient to prepare a buffer with a capacity corresponding to the expected maximum amount of data, but this has the disadvantage that the buffer capacity becomes large and the device becomes expensive.

(e) Purpose of the invention The present invention has been made to solve the above-mentioned drawbacks.
The purpose is to provide a memory management method that can reduce the capacity of buffer memory.

(d) Structure of the Invention The present invention provides a system in which a plurality of terminals, a memory, and a control device are connected, data from the terminals is stored in the memory, and then data in the memory is retrieved at a predetermined period.
The memory comprises a plurality of cells of a predetermined capacity, means for managing whether or not the cells are in use, means for managing the number of the cells allocated to the terminal, and a write address for the cells. means for managing a first pointer indicating a read address of the cell, means for managing a second pointer indicating a read address of the cell, and data capacity from the terminal and writability in the cell allocated to the terminal. when the remaining capacity of one or more cells allocated to the terminal is larger than the received data capacity when data money is received from the terminal. stores the data in the cell, and when the data capacity exceeds the remaining capacity of the cell, assigns a second cell other than the cell to the terminal, writes the received data in the second cell. This is a memory management method characterized by the following. As described above, the present invention provides a buffer memory made up of several n (n≧m) cells on the center side for a group of several m terminals, and stores the buffer memory according to the amount of data from the terminals. By allocating the number of cells, smooth reception processing can be performed with a small buffer memory capacity.

(e) Examples of the Invention The present invention will be explained below with reference to the drawings. Figures 1 and 2
The figure is a block diagram illustrating an embodiment of the present invention. In the concentrator 1 in FIG.
and the address of each terminal is A-
Let it be Z. It is also assumed that data D issued from the terminal (TA-TZ) has the configuration shown in FIG. Second
As shown in the figure, the data D consists of a header section H and a data section d, and the header section H includes an identification section, an address section, and a data number section DX. The identification portion I is a portion in which a bit for identifying whether or not the received data D is written, and “0” is always added to the beginning of the data D. Addresses A to 2 of the terminals TA-TZ are attached to the next address section t, which indicates the data source. In addition, the data number section DX includes data d1 to d1 in the data section d.
The data number X of dX is attached. 3 memories in FIG. 1, n cells CL]~CLn as shown in FIG.
The number n has a relationship with the number m of terminals (TA-TZ) as follows. The flag section 4 also includes a cell management flag MF, a cell usage counter section UC, and a read pointer section R, as shown in FIG.
P and a write pointer section WP are provided.

In FIG. 1, the analysis section 5 analyzes the data D received from the concentrator 1, but first determines the address (for example, A) in the address section t of the header section (see FIG. 2). The management unit 6 determines that the data related to (the terminal at) this address A is
The cell use counter unit UC of the flag unit 4 checks how many cell units are already in use. As shown in FIG. 4(b), the counter CA of the usage counter unit UC has a number "
2'' is set, so in this case, for example, as shown in FIG. 5, data Q is stored across both cells CLl and C'L2. Further, a read pointer RDl indicating the first address of data Q is set in the pointer section RA of FIG. It is set in the pointer section WA of the write pointer section WP.

As mentioned above, the data D from the terminal TA with address A will be written into the remaining portion J of cells CL1 and CL2 shown in FIG. ) write pointer WR of pointer section WA and cell C
The final address E (known) of L2 is checked. If this remaining portion J is larger than the data size of the received data D, data D is written. On the other hand, if it is small, writing is not possible and another empty cell will be searched for.

The management section 6 in FIG. 1 checks the cell management flag section MP of the flag section 4. In other words, find the flag (for example, F3) in which the number rOJ is set in the cell management flag part MP shown in FIG. 4(a), and write data D to the cell CL3 specified by this flag F3. I do. At this time, the read pointer Rn1 of the pointer part R4 of the read pointer part RP in FIG. 4(a) is updated to Rn3, and the write pointer WPO write pointer WR2f in FIG. 4(d) is updated:
At the same time, the value ``2'' of the counter CA of the cell usage counter unit UC in FIG. 2(e) is updated to ``3''. Further, a terminator code TC (1 byte) shown in FIG. 6 is written in the area CN after the data Q of the cell CL2 in FIG. I at the beginning of this terminator code Tc
’ is set to 1-bit data “1” for identification,
Subsequently, cell (number) CL3 is set. Furthermore, a signal "1" is sent seven times to the flag part F3 of the cell management flag part MF in FIG. 4(a).

The above is a case where newly received data D is written when data from one terminal has been written to two cell sections. On the other hand, when the counter section CAO value shown in FIG. 4(b) is "1",
There are three possible cases shown in the figure. The hatched areas in the figure indicate the already written data Q, Ql, Q2, and therefore, in these cases, the starting address G of the cell is
and the final address E, the remaining part (J, Jl,
J2).

As described above, in FIG. Data (D) is written into the memory section 3, and next, a case in which the reading section 8 reads data from the memory section 3 will be described. In FIG. 1, when reading data, the reading unit 8 identifies whether it is the received data D or the terminator code TC by reading out the leading identification pit I or bit. If the value is "0", it is data D, and if it is "■", it is terminator code TC (see FIG. 6).

If the terminal code is TC, the reading unit 8 issues a control signal S, starts the management unit 6, and updates the flag unit 4. That is, the pointer RD2 in the pointer section (for example, Rs) of the read pointer section RP in FIG. 4(c) is updated (unused), and the value of the counter (for example, CB) in the cell use counter section UC in FIG. 4(b) is updated. Count down from "1" to rOJ.

(f) Effects of the Invention As described above, the present invention has means for dividing a buffer memory for storing received data into a plurality of cells and dynamically utilizing these cells for each terminal, so that a predetermined capacity can be obtained. It has the advantage of being able to handle data reception from each terminal using the same buffer memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining one embodiment of the present invention, and FIG.
3 is a block diagram illustrating the configuration of the memory 3, FIG. 4 is a block diagram illustrating details of the flag section 4, and FIG. , FIG. 7. 8 and 9 are block diagrams explaining details of the memory,
FIG. 6 is a block diagram illustrating the structure of the terminator code, and the symbols used in the diagram are as follows. 1 is a collection unit, 2 is a line, 3 is a memory, 4 is a flag unit, 5
is the analysis section, 6 is the management section, 7 is the write section, 8 is the read section, 9 is the processor, A, Z are addresses, CA, CB, Cz
is a counter, CL l+ CL 21 CL 31 C
Ln cell, CN is the area, D is the data, DX is the number of data parts, d is the data part, dl * d2 + d3 Hdn is the data, E is the final address of the cell, Fil F21
F31 Fn is a flag, G is the start address of the cell, H is the header part, I, I' are the identification part, J, Jl, J2 are the remaining parts, MF is the cell management flag, Q, Ql, Q2 are the written Data, RA, RA RZ are write pointers, RD and RDl are read pointers, RP is a read pointer section, S is a control signal, TC is a terminator, t is an address section, UC is a cell use counter section, and WP is a Write pointer section, WRI, WP2 are write pointers, X is the number of data.

Claims (1)

[Claims] In a system in which a plurality of terminals, a memory, and a control device are connected, data from the terminal is stored in the memory, and data in a diagnostic memo η is retrieved at a predetermined period, the memory is connected to a plurality of a means for managing whether or not the cell is in use; a means for managing the number of cells assigned to the terminal; and a first pointer indicating a write address of the cell. a means for managing a second pointer indicating a read address of the cell; and a comparison between the data capacity from the terminal and the remaining writable capacity in the cell allocated to the terminal. and a means for determining the
The remaining capacity of one or more cells allocated to the terminal is
When the data capacity is larger than the received data capacity, the data is stored in the core cell, and when the data capacity exceeds the remaining capacity of the cell, a second cell other than the received data capacity is allocated to the terminal,
A memory management method characterized in that the received data is written in the second cell.