JP2001188711A - Method for judging flag of storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a memory in which data cannot be overwritten nor erased by byte units. SOLUTION: When writing data are transmitted from a main body processor 2 to a storage device 1, a control means 1b writes data in the new sector or block of a storage area 1a. A flag with a plurality of bits corresponding to the same function is recorded on the storage area 1a, and the flag is judged according to the AND of the flag. Thus, it is possible to always output a correct judgment value as log as all bits are not turned to be defective, thereby improving the reliability of this system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for determining a flag in a storage device such as a flash memory used for an external storage device of a personal computer which cannot be overwritten.

[0002]

2. Description of the Related Art In recent years, an external storage device using a flash memory has attracted attention as an external storage device for a personal computer or the like. A flash memory is non-volatile and does not require a backup power supply, can be electrically rewritten, and is inexpensive, but has the following problems. Unless data has been erased, data cannot be written, and the unit of erasure cannot be a byte unit, but is a sector, block or chip unit. Therefore, unlike a normal memory, data cannot be rewritten in byte units, and the writing speed or the erasing speed is lower than the reading speed. There is a limit on the number of erasures.
It is said that erasure becomes impossible after about 1 million times. For this reason, unless the sector or block is used so that the number of erasures is averaged, a portion having a large number of erasures becomes defective first, and the usable area decreases. Since flash memory has the above problems, flash memory
When using the memory, a data save area is prepared, data is saved when data is rewritten, a management table is provided to manage writing / erasing of data, and defective sectors, blocks, and the like occur. In such cases, various measures need to be taken, such as taking remedies.

[0003]

The flash memory has the advantages that it is non-volatile and can be electrically rewritten, but has many problems as described above. Unlike semiconductor memories such as DRAMs and SRAMs, there are many problems that need to be solved when using them. An object of the present invention is to improve the reliability of a memory such as a flash memory that cannot be overwritten and cannot be erased in byte units.

[0004]

FIGS. 1 to 5 are diagrams showing the principle of the present invention. FIG. 1 is a diagram showing the general structure of the present invention, and FIGS. 2 to 5 show the outline of the present invention. FIG. 1 to 5, reference numeral 1 denotes a storage device, 1a cannot be overwritten, and data can be erased only in a predetermined unit such as a sector or a block. Storage area, 1b
Controls writing of data to the storage area 1a,
The control means 1c for erasing the storage area 1a temporarily stores data when writing data to the storage area 1a, or a primary storage medium 1d, 1e for saving data in the storage area 1a. Is a decode table for decoding the address of the storage area 1a, and 2 is a main body processing device. In order to solve the above-mentioned problem, the invention according to claim 1 of the present invention is directed to a storage device including a storage area 1a and control means 1b for controlling data writing to the storage area 1a, as shown in FIG. When determining a flag recorded on the storage area (1a) that may not be able to be erased, a flag of a plurality of bits corresponding to the same function is recorded on the storage area (1a), and the logical product of the flags is recorded. Is used to determine the flag.

[0005]

In FIG. 1, the main processing unit 2 transmits data to the storage device 1.
When the write data is sent to the primary storage medium 1c, the control means 1b stores the data in the primary storage medium 1c. The address is decoded with reference to the decode table 1d (1e), and the data stored in the primary storage medium 1c is stored in the storage area 1d.
Write to a new sector or block a. At this time, if data having the same logical address as the logical address of the data to be written already exists in the storage area 1a, the data is erased or an erasable flag is set in the area storing the data. When an erasure flag is set in the area storing the data, the control unit 1b saves the non-erasable data to the primary storage medium 1c and erases the storage area 1a in a predetermined unit at a predetermined time. Processing such as writing back the data saved in the primary storage medium 1c to the storage area 1a is performed, and creation of a free area is performed. Further, when a part of the storage area 1a becomes defective, the control unit 1b
The defective area is replaced with a spare area by rewriting the decode table 1d (1e).

A storage area 1a shown in FIG. 2A is composed of a plurality of blocks 1a-1,..., 1a-N and sectors dividing the blocks, and erases written data in block units. In a storage device in which a storage area 1 shown in FIG. 4 is composed of a plurality of sectors that cannot be overwritten and erases data written in a sector in sector units,
Writing / erasing of data is performed as follows. (1) The storage area 1a includes a plurality of blocks 1a-1,.
-N, and a storage device 1 composed of sectors that divide the block and erasing written data in block units.
In FIG. 2B, as shown in FIG.
When saving non-erasable data in 1,..., 1a-N to another block having empty sectors, m blocks from the block with the largest number of erasable blocks and n blocks (m, (n is an arbitrary integer), and the selected block is simultaneously evacuated to other blocks having empty sectors by dispersing the sectors uniformly.
As a result, a free block can be created, and as a result, a sector in which many rewrites are performed and a sector in which few rewrites are performed coexist in each block, and the number of erasures of the block can be averaged. (2) The storage area 1a includes a plurality of blocks 1 including a save area.
a-1... 1a-N, and erases written data in block units.
Block 1 containing erasable data as shown in (c)
After moving only the non-erasable data of the data of a-1,..., 1a-N to the save area, the data of the block is erased, and the erased block is set as a new save area, so that the free area is saved. Create Thus, erasable data can be eliminated, and by performing this processing in advance, the writing time can be reduced. (3) Only the non-erasable data of the block on the opposite side of the save area with respect to the data writing direction is moved to the save area, and then the data of the above block is erased, and the erased block becomes a new save area. . This allows all free areas to exist between the write pointer indicating the write location and the save area. Therefore, even if the processing is interrupted, data can be written from the position indicated by the write pointer, and the amount of processing required after the interruption of the processing can be reduced. (4) The storage area 1 includes a plurality of blocks 1a including a spare area.
-1... 1a-N, and erases written data in block units.
(A), as shown in FIG. 3 (a), a write point is set in a spare area, non-erasable data of a block to which data has been written is moved to the spare area, and then data of the block is erased. When the number of free sectors in blocks other than the last erased block is equal to or larger than the number of sectors in the spare area, data in the spare area is moved to a block other than the last erased block. Thereby, a free area can be created. Also, when an empty block becomes unusable,
An unusable block can be salvaged to create an empty block. Further, when moving the data in the spare area to a block other than the block from which the data was erased last, the write point of the movement destination is searched from the block after the block from which the data was erased last, and the data in the spare area is searched. By moving, all empty sectors can be present between the last erased block and the write pointer, and the processing after the interruption of the processing can be simplified. Furthermore, when the processing is resumed after the interruption of the processing, whether there is erasable data in the spare area,
Alternatively, it is possible to determine the processing interruption point according to whether there is only data that cannot be erased, and it is possible to simplify the determination of the processing interruption point. (5) The storage area 1 has a plurality of blocks 1a-1,..., 1a-
In the storage device 1 composed of N and erasing written data in block units, a flag F1 indicating whether or not writing is performed is provided for each block, and referring to the flag F1 as shown in FIG. And erase the written data. Thus, unnecessary erasing can be avoided, the erasing time can be reduced, and the life of the storage medium can be extended. In addition, by providing an in-execution flag F2 indicating that the erasing process of all storage areas is being executed, when the processing is interrupted while the erasing processing of all storage areas is being executed, the execution flag is referred to. It is possible to determine that the erasing process is being performed on all the storage areas, and it is possible to cope with an unexpected interruption of the processing. (6) As shown in FIG. 4, in a storage device in which the storage area 1 is composed of a plurality of sectors that cannot be overwritten and erases data written in the sector in sector units, at least two sectors having the same sector number are used. Prepare and if there is data in one of the sectors with the same number,
At the same time as writing data to the other sector, data in one sector is erased. Thereby, the writing speed can be improved. (7) In the storage device shown in FIG. 4, if there is data in the sector to be written, the data in the sector is erased while the data is being transferred to the primary storage device 1c, and after the data is erased, or After the data transfer is completed, data is written to the sector. Thereby, the writing speed can be improved. (8) In the storage device shown in FIG. 4, spare areas 1b-1 and 1b-2 for replacing a defective sector and a rewritable decode table 1d for managing a write sector are provided, and a defective sector occurs. At this time, by rewriting the decoding table 1d, the spare area 1b-
1, the write sector is changed to 1b-2, and the spare area 1 is changed.
When b-1 and 1b-2 have disappeared, the decoding table 1d is rewritten to reconfigure the sector, so that it is possible to relieve when a defective sector occurs. (9) In the storage device shown in FIG. 4, N + 1 sectors are provided for N sector numbers, and N + 1 sectors are shared by N sector numbers. Is written to a vacant sector among the N + 1 sectors. Thus, the writing speed can be improved, the number of extra sectors can be reduced, and the cost can be reduced. A spare area 1b for replacing a bad sector
-1 and 1b-2, when a bad sector occurs,
The decoding table 1d is rewritten, and the spare area 1b-
The write block or sector is changed to 1, 1b-2, or the decoding table 1d is reorganized. As a result, it is possible to relieve when a defective sector occurs. (10) A storage area 1a that is readable and writable and a part of the storage area may be destroyed, and a rewritable decoder 1d indicating a location where data in the storage area 1a is stored are provided. In the storage device, two stages of decoders are provided as shown in FIG. 4, and when a part of the storage area 1a of the storage device 1 is destroyed, or when a part of the decoders 1d and 1e is destroyed, a two-stage decoder 1d , 1e, or both, so that decoding to the destroyed portion is not performed. Thus, even when a storage medium such as an EEPROM or a flash memory which may be partially destroyed is used as a decoder, the probability of an address error can be significantly reduced, and reliability is ensured. be able to. (11) As shown in FIG. 5, the size of the data to be written to the storage area 1a is sent to the control unit 1b, and the control unit 1b needs to write the data based on the size of the data to be written to the storage area 1a and the internal state of the storage area 1a. To estimate the time. As a result, it is possible to determine whether or not writing is possible with the current remaining power based on the estimated writing time of the storage area 1a and the power required for writing, thereby improving the reliability of the system. (12) The storage area 1a is divided into a plurality of blocks, and a plurality of blocks are provided in the divided chip. When writing data to a block in the chip, the data is written in a new block, and the written data is stored in the chip. If the data already exists in the storage device, in the storage device that erases the data in block units, the chip to which the data is written is fixed in correspondence with the data to be written. Thereby, the control means 1
b needs to manage only the data in each chip, and does not need to manage the entire area. Therefore, the management table in the control unit 1b can be simplified, and the writing speed can be improved. Further, by providing a plurality of work blocks for writing data in each chip, when a work block is defective, the defective work block can be relieved.

According to a first aspect of the present invention, there is provided a storage apparatus comprising: a storage area for performing writing / erasing as described above; and control means for controlling writing of data to the storage area. As shown in FIG. 5, a flag of a plurality of bits corresponding to the same function is recorded in the storage area 1a, and the flag is determined by the logical product of the flags. Therefore, unless all bits become defective, A correct determination value can always be output, and the reliability of the system can be improved.

[0008]

Next, embodiments of the present invention will be described. A. 1 illustrates a configuration of a storage device that is a premise of the present invention. FIG. 6 is a block diagram showing a configuration of a storage device using a flash memory as a premise of the present invention. In the figure, reference numeral 20 denotes a storage device such as a memory card, and 21 denotes a flash memory.
A controller LSI 22 for controlling rewriting and erasing of data in the memory is a processor, 23 is an SRAM used to store various tables and used as a data buffer or save buffer when writing data, 24 is a clock oscillator, 25 -1 to 25-5 are flash memories. In the figure, data transferred from the main body to the SRAM 23 is stored in flash memories 25-1 to 25-5.
When writing data, since the flash memory cannot be overwritten as described above, when writing data, the data is written to a new area. In the case of updating data, measures such as setting an erasure flag on old data are taken.
If the old data has an erasure flag set, only the data to which the erasure flag is not attached is saved in the save area of the SRAM 23 in a predetermined unit at a predetermined time.
After erasing the area to be written in the flash memory, the data is rewritten to organize the data.

FIG. 7 is a diagram showing the contents of the SRAM 23. As shown in FIG. 7, the following data is stored in the SRM 23. (1) Erase count table This table holds the erase count for each block of the flash memory. (2) Erasable sector count table This table holds the total number of erasable sector flags for each block. (3) Write pointer Chip No. to start writing to flash memory,
Holds block No. and sector address No. (4) WORK-BLOCK-No. Indicates the current WORK-BLOCK-No. And the chip No.
, Block No. are held. (5) Arrangement pointer Holds the currently organized chip number, block number, and sector address number. (6) Rewrite Indicates whether the data to be written is new. (7) Number of times of writing Manages the number of times of writing to the main body when organizing. (8) Save counter Manages the number of sectors in the save operation at the time of sorting. (9) Number of chips Holds the number of flash chips mounted on the card. (10) Sector map table Holds chip No., block No., and sector address No. for logical address conversion.

FIGS. 8 and 9 show the flash memory 25-1.
FIG. 25 is a diagram showing the contents of .about.25-5. In each sector of the flash memory, control information, data and the like shown in the following (1) to (5) are stored. In this example, 126 sectors are provided, and each sector includes (1)
The (5) management information and the like and data are stored, and after the 126th sector, the following management information (6) to (14) are stored. (1) Bad flag Indicates the status of this sector. If it cannot be used, write it here. (2) Erasure flag This indicates the data status of this sector. If the data is invalidated by rewriting or the like, writing is performed here. (3) Logical address Indicates the logical address of this sector. (4) Data Data written to this sector. (5) Checksum Checksum of written data (6) Bad sector memory Indicates bad sectors in the block to be rearranged. (7) Erase count of rearrangement source The number of times the block to be rearranged is erased. (8) Saved block No. Chip No. and block No. from which data is saved (9) Erase Start Set when erasing the rearrangement target block is started. (10) Erase End Set when erasing of the rearrangement target block is completed. (11) All Erase target Set when the erase target is determined during All Erase. (12) Empty block Indicates whether there is data in the block and is set when there is data. (13) Block status Indicates the status of this block and is set when it becomes unavailable.

FIGS. 10 to 14 are flow charts showing processing in the processor 22 when data is written to the flash memories 25-1 to 25-5. The operation at the time of writing will be described in detail with reference to FIG. . FIG.
In step S1, the “whether rewriting” (see FIG. 7) indicating whether the data to be written in the SRAM 23 is new is set to 0, and in step S2, it is determined whether or not the data is being sorted. . If not, the process proceeds to step S5, where the "number of times of writing" in the SRAM 23 for managing the number of times of body writing at the time of organizing is set to 0, and the process proceeds to step S7. If the data is being sorted, the process proceeds to step S3, where 1 is added to the "number of writes", and in step S4, it is determined whether or not the number of writes is 6. If the number of times of writing is 6, the procedure goes to step S6, and the number of times of writing is set to 1. In addition, the number of times of writing is 6
If not, go to step S7. The above-described processing is for avoiding frequent organizing operations by not performing the organizing operation when the number of writings is 2 to 5 and performing the organizing operation only when the number of writings is 1 as described later. , By setting the number of writes as described above,
The sorting operation is performed once every five times. In step S7, it is determined whether or not the logical address of the data to be written is over, and if it is, error processing is performed. If the logical address is not over, go to step S8, and determine whether or not there is old data, that is, determine whether or not the data to be written is new data. S9
, The "whether rewriting" of the SRAM 23 is set to 1 and the process goes to step S11. In the case of new data, in step S10, "whether rewriting is performed" in the SRAM 23 is set to 0, and the process proceeds to step S11. Then
In step S11, data is transferred from the main body to the SRAM, and in step S12, it is determined whether or not there is a transfer error. If there is a transfer error, error processing is performed. If there is no transfer error, step S in FIG.
13 to determine whether or not there is rewriting, that is, whether or not the data is new data. If the data is not new data, the data is to be updated.
go to.

In step S15, the "number of times of writing" for managing the number of times of writing in the SRAM 23 is 1
Is determined, and if the “write count” is 1, the flash memory is sorted out from step S16. If the “write count” is not 1, the process goes to step S46 in FIG.
Write the data in the SRAM 23 to the flash memory. In step S16, the "save counter" for managing the number of sectors in the save operation at the time of sorting on the SRAM 23 is set to 0, and in step S17, the "sort pointer" indicating the currently organized sector address No.
It is determined whether or not (sector address) is greater than 126 sectors. If it is not smaller than 126, it is determined that sorting has been completed, and the process proceeds to step S38 in FIG. Also,
If the “arrangement pointer” (sector address) is smaller than 126 sectors, the process proceeds to step S18, where it is determined whether or not the organization pointer is 0. If the “arrangement pointer” is not 0, the process proceeds to step S22.

If the rearrangement pointer is 0, step S
In step 19, the number of erasures and the number of erasable sectors of each block are obtained from a table in the SRAM 23, and based on the table, an arranging target is selected. Next, in step S20, the chip No. to be rearranged is stored in the save block No. of the WORK-BLOCK (see FIG. 9) on the flash memory.
And block No. are written. In step S21, it is determined whether or not there is a write error. If there is a write error, error processing is performed. If there is no write error, the flow proceeds to step S22. Step S2
In step 2, data to be saved is searched. That is, if the erase flag (see FIG. 8) has been written to the data in the flash memory, the operation proceeds to the next sector. Also,
If there is no logical address, an erasure flag is written and the operation goes to the next sector. If the logical address is abnormal, an erasure flag and a failure flag are written and the operation goes to the next sector.

Next, go to step S23 in FIG.
It is determined whether there is a write error. If there is no write error, in step S24, it is determined whether the organizing pointer (sector address) points to the 126th sector, and the organizing pointer is 126. In this case, it is determined that the rearrangement has been completed, and step S3 in FIG.
Go to 8. If the rearrangement pointer is not 126, the process proceeds to step S25, and the data to be saved is moved from the flash memory to the SRAM 23. In step S26, the generated checksum matches the checksum on the flash memory (see FIG. 8). It is determined whether or not to perform.
If they do not match, it is determined in step S27 whether the checksum is FFh. If the checksum is not FFh, the process proceeds to step S28, the checksum on the flash memory is set to FFh, the defect flag of the data saving source sector is written, and the process proceeds to step S29. In step S29, it is determined whether or not there is a write error, and the process proceeds to step S30.
If the checksums match in step S26 or if the checksum is FFh in step S27, the process goes to step S30 to search for a writable sector from the sector indicated by the write pointer, and in step S31 there is a writable sector. It is determined whether or not. If there is no writable sector, perform error processing,
If there is a writable sector, the process proceeds to step S32, and the data on the SRAM 23 is moved to the flash memory.

In step S33, it is determined whether or not there is a write error. If there is a write error, the flow returns to step S30. If there is no write error, the procedure goes to step S34 in FIG. 13, and the erasure flag of the data save source sector is written. Then, step S3
At 5, it is determined whether or not there is a write error. If there is no write error, at step S36, the sector map table on the SRAM 23 is rewritten, and 1 is added to the save counter. Next, in step S38, it is determined whether or not the evacuation operation has been performed a predetermined number of times (in this case, 60 times). After finishing, go to step S38. If the evacuation operation has not been performed 60 times, the process returns to step S22 in FIG. 11 to repeat the above processing.

If the save counter is 60 or if it is determined in step S17 of FIG. 11 that the rearrangement pointer is not smaller than 126, the flow advances to step S38 to determine whether the save counter is 0. Determine. If the evacuation counter is 0, that is, if the rearrangement pointer is not smaller than 126 and the evacuation operation is not performed, step S3 is executed.
Then, in step S39 and thereafter, processing such as writing the information of the defective flag to the defective sector memory is performed. That is, when the save counter is 0, the processing time is short, so that processing such as writing the information of the bad flag after S39 to the bad sector memory is performed, and when the save counter is not 0, Going to step S46 in FIG. 14, processing such as moving the data on the SRAM 23 to the flash memory is performed.

In step S39, the information of the defective flag of the evacuated block is written to the write destination (the write destination is WO
RK-BLOCK) bad sector memory (see Fig. 9)
9 and the number of erasures is indicated by the number of erasures in the sorting source column (FIG. 9).
See). In step S40, it is determined whether or not there is a write error. If there is no write error, the process proceeds to step S41, and the arranged blocks are erased. In step S42, it is determined whether or not there is an erasure error. If there is no erasure error, the flow goes to step S43 in FIG. And write the number of erases. Next, in step S44, 1 is added to the number of erasures of the table corresponding to the erased block, and the number of erasable sectors is set to 0. In step S45, the rearrangement pointer is set to WORK-BLOCK.
And the rearrangement pointer is set to 0.

Next, in step S46, a writable sector is searched from the sector indicated by the write pointer, and in step S47, it is determined whether or not there is a writable sector. If there is a writable sector, the process goes to step S48 to flash data in the SRAM 23.
The process moves to the memory, and in step S49, it is determined whether or not there is a writing error. If there is a write error, the process returns to step S46. If there is no write error, the process goes to step S50. In step S50, it is determined whether or not the rewrite is 1 or not, that is, whether or not the data to be written is new. If the rewrite is 1 or not, it corresponds to the sector in which the erase flag was written in step S51. One is added to the value of the erasable sector number table (see FIG. 7) to be executed, and the process goes to step S52.
If the presence or absence of rewriting is 0 in step S50, the sector map table (see FIG. 7) is rewritten in step 52, and in step S53, a writeable sector is searched from the sector indicated by the write pointer in preparation for the next write. And exit.

B. Write / erase processing. As described above, the flash memory has a limit on the number of erasures, and it is necessary to average the number of erasures in order to effectively use all the memories. In addition, flash memory cannot be overwritten, and when rewriting data, take measures such as writing data to a new sector and setting an erasable flag on old data, and erasing at appropriate time. It is necessary to erase the sector where the enable flag is set. Therefore, it is necessary to secure an empty area for erasing erasable data and to write the data, and to take a remedy when the empty area becomes unusable due to a bad block or the like. A new free area needs to be created. In the following, averaging of the number of erasures described above (Embodiment 1), creation of an empty area for erasing erasable data to secure an empty area (Example 2), and creation of an empty area when a defective block occurs are described. An example of the present invention regarding area processing such as a rescue procedure (Example 3) will be described.

(1) Embodiment 1 (Average of Number of Erasures) As described above, the number of erasures in a flash memory is limited, and in order to effectively use all memories, the number of erasures is averaged. There is a need to. This embodiment shows an embodiment in which the variation in the number of erasures can be suppressed without being aware of the number of erasures in each block. In this embodiment, additional writing is performed in sector units and erasing is performed in block units. In the memory, the blocks are divided into sectors, and as shown below, a block having many digestible sectors and a block having few erasable sectors are mixed and written in a new block, thereby averaging the number of erasures. I have. Next, this embodiment will be described. FIG.
FIGS. 5 to 19 are diagrams showing the write processing in this embodiment. In this embodiment, an example is shown in which a logical sector from A to O is written into a flash memory of 6 blocks having 6 sectors. In the following description,
The number of empty sectors in the block is N (2 in this embodiment).
M blocks (2 in this embodiment)
Save operation), and m blocks (one block in the present embodiment) are used in descending order of the number of erasable sectors.
And n blocks (one block in this embodiment) from the smaller number of erasable sectors are selected and simultaneously saved. In addition,
When performing the save operation, as described above, the sector in which the erasable flag is not set is read, and the S shown in FIG.
After moving to the RAM 23, the sector moved to the SRAM 23 is written in a new block.

In FIG. 15A, since there is no identical sector, blocks 1 and 2 have sectors A, B,
C, D, E, F, G, H, and I are written in order from the first sector. In (b), sectors C and D are written. In this case, since the same sectors C and D are present, an erasable flag is set for the sector in which C and D have already been written, and new sectors C and D are written. Next, FIG.
In (c), the sectors J, K, L, M, N, and O are written. Also in this case, as in the case of (a), since there is no identical sector, writing is performed sequentially after the already written sector. In (d), sectors H, I, J, K,
Write M and N. Since the same sector has been written, an erasable flag is set and new sectors H, I, J,
Write K, M, N.

In FIGS. 17 (e-1) and (e-2),
Write sectors C and D. At this time, since the number of empty blocks is two, a save operation is performed. That is, in FIG. 16D, the block 3 having the largest number of erasable sectors and the block 4 having the smallest number of erasable sectors are selected, and the sectors of the block 3 and the block 4 are mixed, and each of the save destinations is selected. The data is written in the empty blocks 5 and 6 so that the number of sectors in the block becomes uniform. As a result, FIG.
7 (e-1), sectors O, I, K, and M belong to block 5, and sectors H, J, L, and N belong to block 6.
And blocks 3 and 4 become empty blocks.
In this state, an erasable flag is set for the block 2 in which C and D have already been written, and the sectors C and D are set as shown in FIG.
Write to block 5 as shown in FIG.

In FIG. 18 (f-1), sectors H,
Write I and J. Also in this case, since the same sector already exists, the erasable flag is set in the blocks 5 and 6, and the sectors H and I are written in the block 6, but when the sector J is written, there are two empty blocks. So
The evacuation operation is performed as described above. That is, as shown in (f-2), block 2 having the largest number of erasable sectors,
The block 6 having the least erasable sector is selected, the sector of the block 2 and the sector of the block 6 are mixed, and the data is written in the empty blocks 3 and 4 so that the number of sectors of each block at the save destination becomes uniform. Next, as shown in (f-3), the sector J is written. Also in this case, since the same sector exists, an erasable flag is set for the already written sector of block 4 and sector J is written to block 3.

In FIG. 19 (g), sectors E, F, G
Write. Also in this case, since the same sector exists, an erasable flag is set for the already written sectors of blocks 1 and 3, and sectors E, F and G are written to blocks 3 and 4, respectively. FIG. 20 is a flowchart showing the processing of this embodiment, and the processing of this embodiment will be described with reference to FIG. In step S1, when data is received from the main unit, in step S2, the number of blocks having an empty sector becomes N.
It is determined whether or not: If the number of blocks with empty sectors is not N or less, the process proceeds to step S7. If the number of blocks with empty sectors is N or less, in step S3, the number of blocks from the large number of
Blocks are set to be evacuated, and in step S4, n blocks are set to be evacuated from blocks having a small number of erasable sectors. In step S5, data is moved from the block to be saved to an empty block. The writing method at that time changes the writing block every time data is moved, and returns to the first written block after writing in M blocks. Next, in step S6, the block to be saved is erased. If there is the same logical sector in step S7, an erasable flag is set for the physical sector that has already been written, and in step S8, the data received from the main unit is written to the flash memory.

By the way, in general, a system
There are sectors that store data that is hardly rewritten, such as programs, and sectors that store data that is constantly rewritten. When data is written / saved normally, sectors that are hardly rewritten are stored. The block with the larger number has a smaller number of erases. Therefore, as described above, a block having many erasable sectors (a block having many sectors that are constantly rewritten) and a block having a few erasable sectors (a block having many sectors that are hardly rewritten) are mixed. By writing to a new block in this way, as a result, a sector with many rewrites and a sector with few rewrites are mixed in each block, and the number of erasures of the block can be averaged. In the present embodiment, since the writing process is performed based on the above principle, it is possible to suppress the variation in the number of erasures without being aware of the number of erasures of each block, and to reduce the variation in the number of erasures as in a flash memory. Can extend the life of a finite memory. In addition, since the variation in the number of times of erasing can be suppressed without counting the number of times of erasing, memory management can be performed without providing an area for counting the number of times of erasing.

(2) Embodiment 2 (Creation of Empty Area by Erasing Erasable Data) As described above, the flash memory cannot be overwritten, and can only be written after erasing. . Therefore, at the time of writing, if there is the same sector, it is necessary to set an erasable flag and to erase the sector where the erasable flag is set at an appropriate time. As described above, the present embodiment shows the area processing for eliminating the erasable data with the erasure flag set from the storage medium. By doing so, a writable area can be secured, and the writing time can be reduced.

FIGS. 21 to 24 are diagrams showing the write / erase processing in the present embodiment. The present embodiment will be described with reference to FIGS. In this embodiment, the following points are assumed. The number of blocks is 6, and there are 6 sectors per block. Read / write is performed in sector units, and erase is performed in block units. The write method is a write-once write method, and when writing a logical sector at the same address, an erasable flag is set in the physical sector stored in the old logical sector. For the additional writing, the writing area is assumed to be 5 blocks + an evacuation area 1 block (block 1 to block 6). When there is no more write area, the data of the non-erasable physical sector of the block having the largest number of physical sectors with the erasable flag set is moved to the save area, and the source block is erased. Then, the block is used as a save area, and the save area up to now is set as a write area (this series of operations is called a save operation). The address of the sector sent from the main unit is A to P
And When there is m or more erasable data in a block,
It is set as a target of the area processing in the present embodiment (m = 1 in the examples of FIGS. 21 to 24). Note that FIG.
The arrows from 1 to the right of the block in FIG. 24 indicate the position of the write pointer indicating the write location.

In FIG. 21A, logical sectors A to G
Write. In this case, since there is no logical sector having the same address, writing is performed sequentially from the position indicated by the write pointer. In (b), the logical sectors A, D to G are written. In this case, the logical sector (A,
D, E, F, and G), the erasure flag is set, and then the data is written in the same manner as in (a). In (c), the logical sectors H to N are written. In this case, since there is no logical sector having the same address, the data is written as it is. FIG.
In (d), A, G to L are written. In this case, the logical sector (A, G, H, I, J,
K, L), the data is written after setting the erasable flag. In (e), A, H to J are written. Also in this case, the logical sector (A, H, I, J,) of the same address
Therefore, write after setting the erasable flag.
In (f-1), writing of A, I to L is to be performed, but since there is no writing area, a save operation is performed. That is, the data of the block (block 3) having the largest number of physical sectors with the erasable flag set is moved to the save area (block 6), and the source block is erased. Then, the block (block 3) is used as a save area, and the save area up to now (block 6) is set as a write area. As a result, it becomes like (f-1).

Next, as shown in FIG. 23 (f-2),
A, I to L are written. In this case, since there is a logical sector having the same address, after setting the erasable flag, A,
Write I to L. At this time, the write pointer is at the head of the save area (block 6). Since the erasable data is increased by writing as described above, the area processing according to the present embodiment is performed. That is, when viewed from the save area (block 3), a save operation is performed in blocks 2 and 3 with a block (block 2) in the opposite direction to the writing direction as a processing target. As a result, as shown in FIG. 23 (g-1), the block 2 becomes the save area, and the non-erasable data of the block 2 is moved to the block 3. Next, a retreat operation is performed in blocks 1 and 2 in the same manner as described above. As a result, as shown in (g-2), the block 1 becomes a save area, and the non-erasable data of the block 1 is moved to the block 2.

Next, a retreat operation is performed in blocks 5 and 1 in the same manner as described above. As a result, as shown in FIG. 24 (g-3), the block 5 becomes a save area, and the non-erasable data of the block 5 is moved to the block 1. Block 6
Since there is no erasable data in, it is not subject to area processing. Similarly, the retreat operation is performed in blocks 4 and 5. As a result, as shown in (g-4), the block 4 becomes a save area, and the non-erasable data of the block 4 is moved to the block 5. Then, since the position of the save area has reached the position of the save area before performing the processing, the area processing ends. By performing the above processing, the erasable data disappears from the storage medium. Next, as shown in (h), A, H to J
Write. Also in this case, since there is a logical sector at the same address, writing is performed after setting an erasable flag.

FIG. 25 is a flowchart showing the processing of this embodiment. The processing of this embodiment will be described with reference to FIG. In step S1, the block number of the current save area is stored, and in step S2, the save area is set as a processing target. In step S3, the processing target is advanced by one in the direction opposite to the writing direction. In step S4, the processing target and the storage block N stored in step S1
o. are compared, and if they are the same, the process ends. If the processing target and the storage block number are different, the process goes to step S5, where the number of erasable sectors to be processed is compared with a predetermined value m.
3 and the above process is repeated. Number of erasable sectors is m
If it is larger, the process proceeds to step S6, where the processing target is set as the evacuation target, and the write pointer is moved to the head of the evacuation area in step S7. In step S8, data is moved from the block to be saved. In step S9, the block to be saved is erased, and in step S10, the block to be saved is set as a save area, and the process returns to step S3 to repeat the above processing.

In this embodiment, since the area processing is performed as described above, erasable data can be eliminated. By performing the area processing in this embodiment in advance, the writing time can be reduced. be able to. Also,
Since the block to be subjected to the area processing is advanced in the direction opposite to the writing direction, all free areas can be present between the write pointer indicating the writing location and the save area. As a result, no matter what case the processing is interrupted, data can be written from the position indicated by the write pointer, and the number of processes required after the process is interrupted can be reduced. There is no problem even if you do not finish.

(3) Embodiment 3 (Rescue Measures for Creating Free Space) As described above, the flash memory needs to secure a free space in the memory for writing data. The embodiment shows an embodiment in which, when the above-mentioned empty area becomes unusable due to the occurrence of a bad block or the like, a remedy is taken to create a new empty area.
FIG. 26 to FIG. 32 are diagrams showing a process of creating a free area according to the present embodiment, and the present embodiment will be described with reference to FIGS. In this embodiment, the following points are assumed. The number of blocks is 7, and there are 6 sectors per block. Read / write is performed in sector units, and erase is performed in block units. The write method is a write-once write method, and when writing a logical sector at the same address, an erasable flag is set in the physical sector stored in the old logical sector. A spare area (block 0) of one block is reserved for rescue at the time of failure, and the write area is set to 5 blocks + one block of save area (block 1 to block 6) for additional recording. When there is no more write area, the data of the non-erasable physical sector of the block having the largest number of physical sectors with the erasable flag set is moved to the save area, and the source block is erased. Then, the block is used as a save area, and the save area up to now is set as a write area (this series of operations is called a save operation). The address of the sector sent from the main unit is A to P
And

In FIG. 26A, sectors A to G are written. In this case, since there is no same logical sector, the data is written from the block 1 as it is. In (b), sectors A and D to G are written. In this case, sector A,
Since there is the same logical sector as D to G, an erasable flag is set in the same logical sector before writing. In (c), sectors H to N are written. In this case, since there is no same logical sector, the data is written as it is. In FIG. 27D, sectors A and G to L are written. In this case, since there is the same logical sector as the sectors A, G to L, writing is performed after setting an erasable flag in the same logical sector. (E)
, Sectors A, H to J are written. In this case, since there is the same logical sector as the sectors A, H to J, writing is performed after setting an erasable flag in the same logical sector.

In FIG. 28 (f-1), sectors A and I
ＬL are written. In this case, since there is no write area, the write operation is performed after the save operation is performed. That is, the non-erasable data of the block (block 3) having the most data with the erasable flag set is moved to the save area (block 6), and the source block is erased. Then, the block (block 3) is used as a save area, and the save area up to now is set as a write area.
Next, in (f-2), the sectors A and I to L are written into the block 6 which has become the write area. Next, (g)
In the above, A, M and N are written.
Since there is no write area as in the case described above, first, a save operation is performed. That is, the non-erasable data of the block (block 5) with the largest number of data with the erasable flag set is moved to the save area (block 3), and the source block is erased. Then, the block (block 5) is used as a save area, and the save area up to now is set as a write area. Here, if block 5 becomes unusable due to erasure failure, rescue measures are taken because there is no save area.

Therefore, as shown in FIG. 29 (h), a retreat operation is performed using the spare block 0 as a temporary rescue area. That is, in FIG. 28G, the non-erasable data of the block (block 1) having the largest number of non-erasable data is moved to the temporary save area (block 0), and the source block is erased. Then, the block (block 1) is used as a save area. Next, as shown in (i), the evacuation operation of the spare block (block 0) is performed. That is, the logical sectors B and C of the spare area (block 0) used as the temporary save area are moved to block 3. Now that the spare area and save area have been created,
In (j), the logical sectors A, M, and N are written in the block 3. Next, sectors A, G, H, O, and P are to be written, but there is no write area.
The evacuation operation is performed as shown in 1). That is, the non-erasable data of the block (block 4) having the largest number of erasable data is moved to the save area (block 1), and the source block is erased. Then, the block (block 4) is used as a save area. Then, (k-
As shown in 2), sectors A, G, H, O, and P are written. However, since sectors A, G, and H have logical sectors of the same address, block 1 is set after an erase flag is set.
And the sectors O and P are written as they are.

Next, in (l), an attempt is made to write sector A, but since there is no write area, a save operation is performed. As a result, the block 2 becomes a save area, and the sectors D, E, and F in the block 2 move to the block 4.
Here, if the block 2 becomes unusable due to the erasure failure, there is no save area, so a rescue measure is taken. That is, the data of the block (block 3) having the largest number of erasable data is moved to the temporary save area (block 0), and the source block is erased. Then, the block (block 3) is used as a save area. As a result, the result is as shown in FIG. In this state, if the processing is temporarily stopped due to power shortage or the like, when the processing is restarted, the apparatus determines that the spare area has no erasable sector and that there is data, and that a free area is being created. it can. Subsequently, a rescue procedure for creating a free area is performed, and sectors I and J of block 6 are moved to the spare area (block 0), and sectors K and L of block 6 are moved to block 3. As a result, the result is as shown in FIG.

Here, since the number of free sectors excluding the sectors in the save area is equal to or greater than the number of data in the spare area (block 0), a write point is searched from the back of the save area. Data is moved from the area (block 0). At this time, as shown in FIG.
It is assumed that the main unit temporarily stops processing due to power shortage or the like at the stage when the sectors B, C, M, and N of the spare area (block 0) are moved. In this case, when the processing is restarted, the device side has an erasable sector in the spare area.
It can be determined that data is being moved in the spare area where the empty block is being created. Subsequently, as shown in FIG. 32 (p), the logical sectors I and J in the spare area (block 0) are moved to block 4 and the process is terminated.

FIG. 33 is a flowchart showing the free area creation processing in this embodiment. The processing in this embodiment will be described with reference to FIG. In step S1, it is determined whether or not there is an erasable sector in the spare area.
Go to step S11. If not, the process proceeds to step S2, where the write pointer is set as the head of the spare area, and in step S3, it is determined whether or not there is data in the spare area. If there is data in the spare area, step S10
If no, go to step S4 and set the save area as a spare area. In step S5, if there is no erasable sector in each block of the write area, the process is aborted because no free area can be created. If there is an erasable sector, the process proceeds to step S6, where the block having the largest number of erasable sectors is set as a save target, and in step S7, data is moved from the save target block to the spare area.

In step S8, the block to be saved is erased, and in step S9, the block to be saved is set as a save area. In step S10, it is determined whether or not the number of data in the spare area is larger than the number of free sectors other than the save area. If ≤,
In step S11, a write pointer is searched for from the next save area in the write direction. In step S12, data is moved from the spare area to a free sector.
In step S13, the spare area is erased and the process ends. In the present embodiment, since the free area is created as described above, even if an unusable block occurs in the storage medium, the free area can be created by the rescue procedure and used as a storage device. You can avoid becoming impossible. In addition, even if the processing is interrupted due to a power shortage on the main body side during the processing, it is possible to easily determine at which stage the processing was interrupted, and to simplify the determination of the processing stage in the processing interruption. It becomes possible.

C. Efficiency of Erasing Process The flash memory cannot be overwritten as described above, and can only be written after erasing. In the present embodiment, in the flash memory as described above, by providing a flag indicating whether or not writing is being performed and an in-execution flag indicating that the entire space erasing process is being executed, the erasing when erasing the entire storage space is performed. An example is shown in which the processing can be performed efficiently and the processing can be restarted even if the processing is interrupted for some reason during erasing. Next, the processing of this embodiment will be described with reference to FIGS. In this embodiment, the number of blocks is six, an area for writing a write flag is provided in each block, and an area for writing an in-execution flag indicating that the entire space erase process is being executed is provided in block 6. I have.
In FIG. 34 (a), before writing in blocks 1, 2, and 4, a writing presence / absence flag is written in blocks 1, 2, and 4. Next, in the initialization processing for clearing the entire space, the execution flag is written in the block 6 as shown in (b-1). In (b-2), the block 1 in which the writing presence / absence flag is written is erased, and the writing presence / absence flag is erased.

In FIG. 34 (b-3), the block 2 to which the write presence / absence flag has been written is erased, and the write presence / absence flag is erased. Here, after the block 2 is erased, the stop sequence is shifted to the stop sequence for some reason, and even if the block 2 starts up, since the execution flag is written in the block 6, it is immediately determined that the initialization operation is being performed. You can move on. In (b-4), since the writing flag is not written in the blocks 1 to 3, the block 4 is erased and the writing flag is erased. In (b-5), since the writing presence / absence flag is not written in the blocks 1 to 5, the block 6 is erased and the execution flag is erased.

FIG. 36 is a flowchart showing the processing of the present embodiment. The present embodiment will be described with reference to FIG. In step S1, it is determined whether or not the execution flag is written. If yes, the process goes to step S3. If not, the execution flag is written in the last processing block in step S2. In step S3, the processing target is cleared, and in step S4, it is determined whether or not the processing target has a writing presence / absence flag. If there is no writing presence / absence flag, the process goes to step S6. If there is, the process target is deleted in step S5, and the process target is advanced to the next in step S6. Step S7
In, it is determined whether or not a running flag has been written. If so, the process returns to step S4 and repeats the above processing. If there is no running flag, the process ends.
In this embodiment, since the writing presence / absence flag is provided as described above, unnecessary erasing can be avoided, the erasing time can be shortened, and the life of the medium can be extended. Further, since the execution flag indicating that the initialization is being executed is provided, it is possible to cope with an unexpected interruption.

D. Improvement of Write Speed and Allocation of Spare Area when Bad Sector Occurs As described above, a flash memory cannot be overwritten and cannot be written to a sector unless it has been erased. For this reason, as described above, it is necessary to set an erasable flag when there is the same sector at the time of writing, and to erase the sector where the erasable flag is set at an appropriate time, which takes a long time for writing. Also,
As described above, the flash memory has a limit on the number of erasures, and if the erasure is performed more than a predetermined number of times, the erasure cannot be performed. For this reason, when a bad sector occurs, it is necessary to allocate a spare area and take a remedy. In the embodiment described below, in the memory which cannot be overwritten and which can be erased in sector units, In this embodiment, the time lag is eliminated, the writing speed is improved, and a spare area is allocated when a defective sector occurs. FIG. 37 is a diagram showing a system configuration of this embodiment.
An EEPROM 26 is added to the system shown in FIG. 6, and the other configuration is the same as that shown in FIG. The EEPROM 26 stores a decode table for performing address conversion, and the EEPROM 26 decodes an address. When a part of the flash memory becomes defective, the EEPROM 2
6 is rewritten and remedy is performed. In FIG. 37,
Although the EEPROM 26 is illustrated, the storage medium storing the decode table may be any rewritable storage medium, and may be a flash memory or the like.

(1) Embodiment 1 FIGS. 38 and 39 show the structure of this embodiment.
In FIG. 8, reference numeral 261 denotes a sector conversion unit composed of an EEPROM 26 (or a rewritable ROM such as a flash memory). Reference numeral 25 denotes a flash memory. The flash memory is provided with a first area A, a second area B, and a spare area C.
In the area B, four sectors 1 to 4 are provided, respectively. In FIG. 38, when writing data to the sector 1, the first area A and the second area B are viewed, and when data already exists in the first area A, the second area B is read.
Write data to While writing the data, the sector 1-A in the first area A is erased. At this time, if a write error occurs, the spare area C is assigned as a substitute sector. That is, the first area A
If a write error occurs in sector 1-A of
In order to substitute the spare area C for the sector 1-A, the ROM of the sector conversion unit 261 is rewritten, as shown in FIG.
The spare area C is allocated as the sector 1-A.

As described above, when a write error occurs, a sector in a spare area is allocated as long as there is a spare, and when there is no spare, all data is saved to an external area such as the SRAM 23 shown in FIG. And the sector conversion unit 2
The 61 ROMs are reorganized and divided into a data space and a spare space. At that time, sectors are allocated in ascending order or descending order in the same manner as in the initial state according to the system configuration, but defective sectors are excluded. In the present embodiment, as described above, erasing is performed simultaneously with writing, so that a time lag at the time of writing can be eliminated, and the writing speed can be improved. In addition, a spare area is provided, and when a defective sector occurs, the spare area is replaced with the spare area, so that it is possible to perform relief when a defective sector occurs.

(2) Embodiment 2 FIGS. 40 and 41 show the structure of this embodiment.
0, reference numeral 261 denotes a sector conversion unit composed of a rewritable ROM such as an EEPROM or a flash memory, and 25 denotes a flash memory. The flash memory has a first area A and a spare area C. , The first area A is provided with four sectors 1-4. Reference numeral 231 is a primary storage medium for data such as the SRAM 23 shown in FIG. In FIG. 40, at the time of data writing, while data is being transferred to the primary medium 231, the sector to be written is checked, and if there is data in the sector to be written, the sector is erased. If the transfer is completed earlier,
If the transfer is slow, data is written after the transfer is completed. Further, when a write error occurs, the ROM of the sector conversion unit 261 is rewritten, and FIG.
As shown in FIG. 1 (the case where an error occurs in the sector 1-A), the sector 1-A is written in the spare area C. As long as normal sectors do not fail,
Writing to the spare area C is not performed. In this embodiment, as described above, if data is present in the sector to be written while data is being transferred to the primary storage medium 231, erasing is performed. The time lag at the time of writing can be eliminated, and the writing speed can be improved. In addition, a spare area is provided, and when a defective sector occurs, the spare area is replaced with the spare area, so that it is possible to perform relief when a defective sector occurs.

(3) Embodiment 3 FIGS. 42 and 43 show the structure of this embodiment.
2, reference numeral 261 denotes a sector conversion unit composed of a rewritable ROM such as an EEPROM or a flash memory; and 25, a flash memory. 2, each block has a block 1, and a block 2 has sectors 1-3A, 1-3.
B, ..., 1-3D, 4-6A, 4-6B, ..., 4-6D
Is provided. Then, sectors 1-3A, 1-3
Each of B,..., 1 to 3D is one sector as a physical address, and data of a logical address 1, 2, or 3 can be written therein. That is, the area for writing the data of the logical address 1, 2, or 3 is provided for four sectors A to D.
ＤD is written in an empty area. Similarly, sectors 4 to 6A, 4 to 6B,..., 4 to 6D are the same as above, and when data of logical addresses 4, 5, or 6 is to be written, Write. As described above, in the present embodiment, blocks are formed in units of n + 1 (n = 3 in this embodiment) sectors.
One sector space is provided for the logical address to be written.

Referring to FIG. 42, when data is written to sector 1, sectors 1 to 3A, 1 to 3B,..., 1 to 3D are looked at, and if sector 1 already exists, to erase. Since there is always a vacant sector in the sector, writing is performed on the vacant sector at the same time as the above-described erasure. At the time of writing, if a write error occurs, a spare block is assigned as a substitute block. For example, when the sectors 1 to 3A become defective, the spare block 1 is assigned as a substitute block as shown in FIG. Then, the ROM of the sector conversion unit 261 is rewritten, and an alternative process of allocating the block 1 having an error to the spare block 1 is performed. As a result, the spare block 1 becomes the block 1. The above processing is performed as long as there is a spare, and when there is no spare, all the data is saved to an external area such as the SRAM 23 shown in FIG. 37, the ROM of the sector conversion unit 261 is reorganized, and And a spare space. At that time, sectors are allocated in ascending order or descending order in the same manner as in the initial state according to the system configuration, but defective sectors are excluded. When converting a logical sector into a physical sector, the sector converting unit 261 blocks the data in units of n + 1 sectors as described above, and configures the sector 1 to be decoded so that there are n + 1 writable sectors. When some sectors become defective, the writing block is moved by rewriting the table of the sector conversion unit 261 to always create a block of (n + 1) sectors. In the present embodiment, as described above, blocks are formed in units of n + 1 sectors, one sector is left, and erasing is performed at the same time as writing, so that the time lag at the time of writing is eliminated as in the first and second embodiments. And the writing speed can be improved. In addition, a spare area is provided, and when a defective sector occurs, the spare area is replaced with the spare area, so that it is possible to perform relief when a defective sector occurs.

(4) Fourth Embodiment FIGS. 44 and 45 are views showing the structure of the present embodiment.
4, reference numeral 261 denotes a sector conversion unit composed of an EEPROM or a rewritable ROM such as a flash memory, and 25 denotes a flash memory.
1D are provided, and blocks 1 and 2 have sectors 1 to 3A, 1 to 3B,.
A, 4 to 6B,..., 4 to 6D are provided. Also,
In the present embodiment, similarly to the third embodiment, the block is divided into n + 1 (n = 3 in this embodiment) sector units, and 1
Leave a sector empty. In FIG. 44, when data is written to sector 1, sectors 1 to 3A, 1 to 3B,.
Looking at the 3D, if the sector 1 already exists in these, the sector is erased. Since there is always a vacant sector in the sector, writing is performed on the vacant sector at the same time as the above-described erasure. When writing,
When a write error occurs, spares 1A to 1D are assigned as substitute sectors. For example, sectors 1-3A
Becomes defective, as shown in FIG.
Blocks A to 1D become block 1, and a spare 1A is allocated to sectors 1 to 3A, and the substitution process is performed by rewriting the ROM of the sector conversion unit 261. As a result, the spare sector 1A becomes the sectors 1 to 3A, and the spares 1B to 1D become spares for the block 1.

The above processing is performed as long as there is a spare,
When there is no spare, all data is saved to an external area such as the SRAM 23 shown in FIG. 37, the ROM of the sector conversion unit 261 is reorganized, and divided into a data space and a spare space. At that time, sectors are allocated in ascending order or descending order in the same manner as in the initial state according to the system configuration, but defective sectors are excluded. Sector conversion unit 26
As described above, when converting from a logical sector to a physical sector, block 1 is provided in units of n + 1 sectors, and at the time of decoding, a table for performing address conversion based on the decoded data is provided, and n + 1 sectors that can be written to sector 1 are provided. Is configured to exist. When some sectors become defective, the table of the sector conversion unit 261 is rewritten to always create a block of (n + 1) sectors. In this embodiment, as described above, blocks are formed in units of n + 1 sectors, one sector is left, and erasing is performed at the same time as writing. Therefore, similarly to the first, second, and third embodiments, the time lag at the time of writing is reduced. The writing speed can be improved.
Also, a spare area is provided, and when a bad sector occurs,
Since the spare area is used, it is possible to relieve when a defective sector occurs.

(5) Fifth Embodiment FIGS. 46 and 47 show the structure of this embodiment.
6 and 47, the same components as those shown in FIGS. 38 and 39 are denoted by the same reference numerals, and 261 is an EEP
A sector conversion unit composed of a rewritable ROM such as a ROM or a flash memory, 25 is a flash memory, and the flash memory is provided with a block 1, a block 2, a spare block 1, and a spare block 2. Block 1, Block 2, Sectors 1-3A, 1
... 3B, ..., 1-3D, 4-6A, 4-6B, ..., 4-
6D is provided. In the present embodiment, as in the third embodiment, n + 1 (n = 3 in this embodiment).
It is divided into sectors, and one sector is left. In FIG. 46, when writing data to sector 1, sectors 1 to 3A, 1 to 3B,..., 1 to 3D are looked at, and if sector 1 already exists in these sectors, the sector is erased. Since there is always an empty sector, writing to the empty sector is performed at the same time as the above-described erasure. When writing, if a writing error occurs,
A spare sector is assigned as a substitute sector. For example, if the sectors 1 to 3A are defective, the spare block 1
Is assigned, and the ROM of the sector conversion unit 261 is rewritten to perform the substitution process. As a result, as shown in FIG. 47, the sectors 1, n, and mA of the spare block are replaced with the sector 1, the sector 1 is present in the spare block, and the sectors 2, 3 remain in the original block.

That is, in this embodiment, the configuration of the block need not be a continuous sector, and the number of the original block configuration is changed. The above processing is performed as long as there is a spare, and when there is no spare, all data is
And the ROM of the sector conversion unit 11 is reorganized to divide the data into a data space and a spare space. At that time, sectors are allocated in ascending order or descending order in the same manner as in the initial state according to the system configuration, but defective sectors are excluded. In this embodiment, as described above, blocks are formed in units of (n + 1) sectors, one sector is left, and erasing is performed at the same time as writing. The time lag can be eliminated, and the writing speed can be improved. Also, a spare area is provided, and when a bad sector occurs, it is replaced with a spare area.
Relief when a bad sector occurs can be performed.

FIGS. 48 to 50 are flow charts showing the processing in the above embodiment. The processing of this embodiment in the system shown in FIG. 37 will be described. In step S1, when there is a write request for sector data from the main body,
In step S2, the CPU 22 sets the controller LS
It recognizes that there is a data write request from the notification from I21. Note that the controller LSI 21 has a CPU
The data write request may be notified by interrupting 22. In step S3, the CPU 22 executes EE
.., 25-5 in order to read the data in the PROM 26, recognize the writing location, and check whether sector data has been written.
To access the ECC data or flash
Reference is made to management information and the like stored in the memory. Then, in a step S5, it is determined whether or not data is written in the flash memory. If the data is not written, the process proceeds to a step S8 in FIG. If data has been written, information for writing data to the second sector is read in step S6.
The CPU 22 accesses the EEPROM 26 to obtain data. Then, in step S7, the data in the flash memory is erased (error checking is performed later to improve efficiency), and the process proceeds to step S8 in FIG.

In step S8, the data is transferred from the main body to the SRAM 23, and the process waits for the end. In step S9, to write data to the flash memory, the CPU 22 notifies the controller LSI 21 of data writing, and the controller LSI 21
Data is written from the RAM 23 to the flash memory. Next, in step S10, the CPU 22 receives a data write completion notification from the controller LSI 21, and determines in step S11 whether a data write error has occurred. If there is no data write error, the process ends. If there is a write error, it is determined in step S12 whether or not there is a replacement sector. If there is a replacement sector, the process proceeds to step S13. EE to change the sector address
The data is changed by accessing the PROM 26, and the process returns to step S9. In addition, when there is no replacement sector, FIG.
0, go to step S14 to determine whether there is a flash memory being erased. If there is a flash memory being erased, go to step S15, wait until the end of erasure, and store data in the erased sector. Is written.
If it is determined in step S14 that there is no flash memory being erased, an error is notified to the main body in step S16. In step S17, the main body sends a command to download the data and reorganize the EEPROM 26. On the storage device side, the EEPROM 26 is reorganized in response to a command from the main unit side,
Two or more sectors can be selected for one logical sector sent from the main unit. As a result, the storage capacity can be reduced but the storage device can be used. In the above-described processing, the case where data is transferred to the SRAM 23 and data is written to the flash memory has been described.
It is also possible to write data directly to the flash memory without providing the SRAM 23 (in this case, steps S8 and S9 in the above flowchart are one process).

E. Improving Reliability of Decoding Unit for Address Conversion A ROM may be used as a conversion table for converting a logical address into a physical address. Also, RO
Flash EEPROM, EEPROM instead of M
Although it is possible to use such a method, it is usually rarely used because the decoding unit does not need to be variable.
On the other hand, in the flash memory, the number of erasures is limited due to the nature of the medium, and when the flash memory becomes defective, the defective address cannot be used. Therefore, the above-mentioned D.I. As shown in the embodiments (1) to (5), when a rewritable decoding unit such as a flash EEPROM or an EEPROM is used as a conversion table for converting a logical address to a physical address, In this case, a method is used in which the decoding unit is rewritten so that there is no defective address. However, as a conversion table,
When a flash EEPROM, an EEPROM, or the like is used, the flash EEPROM, the EEPROM, and the like also have a limitation on the number of times of erasing, and a defect occurs when the erasing is performed a predetermined number of times or more. In the present embodiment, as described above, when a rewritable storage medium such as a flash EEPROM or an EEPROM is used as the decoding unit, the life of the decoding unit is extended by providing the decoding unit in two stages, 9 shows an embodiment for improving the reliability of the address conversion decoding unit.

FIGS. 51 (a) and 51 (b) show the structure of the decoding unit of this embodiment. FIG. 51 (a) shows a normal case, FIG. 51 (b) shows a case where a sector becomes defective, and FIG. , Where 301 is the primary decoding unit, 302
Indicates a secondary decoding unit, and 303 indicates a sector of the flash memory. In the figure, when the sector of the flash memory is normal, the primary decoding unit 301 outputs the address “0000h” as the decoded value of the address of the sector 0 as shown in FIG. 3
02 outputs the physical address "5555h" as the decoded value of "0000h", and designates the physical address of sector 0 of the flash memory. Here, when the number of erasures of the flash memory exceeds the limit value and the sector becomes defective and the physical address of sector 0 is switched to the spare sector at address 8888h, as shown in FIG. Rewrite the decoding unit 302 to “0000”
h ”from“ 5555h ”to“ 8888h ”
Switch to As a result, the physical address “8888h” is assigned as the sector 0. By rewriting the secondary decoding unit (or the primary decoding unit) several times as described above, the rewriting limit value is exceeded or more.
If the next decoding unit becomes defective, the primary decoding unit 301 is rewritten to shift its decoding value, and the secondary decoding unit 302 outputs “2288h” as the decoding value, as shown in FIG. Rewrite so that it is output as a decoded value. Thus, even if the secondary decoding unit 302 becomes defective, the physical address “88”
88h "can be output as the decoded value.

As described above, the decoding section is divided into two stages, and when one of the decoding sections becomes defective, the other decoding section is rewritten, so that the life of the decoding section can be squared. For example, the number of times until the sector becomes defective is L (rewrite limit value), the number of times until the secondary decoding unit becomes defective is M (rewrite limit value), and the number of times until the primary decode unit becomes defective. Is N times (rewrite limit value), the number of times until an address becomes an error is N
× M × L times. Basically, the rewrite limit value is said to be 100,000 to 1,000,000 times for a flash EEPROM and about 10,000 times for an EEPROM. Therefore, it is practically sufficient to secure sufficient reliability only by providing two stages of decoding units. it can.

F. Write Time Estimation Process In a flash memory, it is necessary to perform a save process or the like when writing data, and it takes longer to write than in a normal semiconductor memory. This embodiment shows an embodiment in which the writing time to the flash memory is estimated, the power consumption is estimated, the abnormality is detected, and the like. Next, this embodiment will be described. Now, consider a case in which data of three sectors is written when the storage device is in a state as shown in FIG. First, the number of sectors to be written is sent from the main unit of FIG. When the number of sectors to be written is sent to the processor 22, the processor determines the writing time from the number of sectors to be written. Here, when there is no block to be written as shown in FIG. 52,
Since the saving operation is performed, the writing time t is obtained as follows. t = [time required to write one sector] × 3 + [data save time] (second) The processor 22 calculates the write time as described above and returns it to the main unit. The main body obtains the power consumption W1 at the time of the write operation based on the write time by the following equation. W1 = t ÷ 3600 × [power consumption of write operation]
(W) The main body reads the remaining power W2 from the power supply unit, compares the remaining power W2 with the obtained writing power, and writes data if W2> W1. On the other hand, the main body compares the writing time t obtained as described above with the actual writing time, and if the writing is not completed even if the writing time t is exceeded, it judges that the storage device is abnormal, and And take measures such as stopping the writing process.

FIG. 53 is a flowchart showing the processing of the main body in this embodiment, and this embodiment will be described with reference to FIG. In step S1, the size of data to be written is sent to the storage device, and the time required for writing is obtained. In step S2, the time required for writing,
The power required for writing is obtained by consuming power per hour. In step S3, the remaining power is compared with the power used for writing. If the remaining power is smaller,
Perform error processing. If the remaining power is more,
In step S4, the data is written, and in step S5, it is determined whether or not the actual writing time is longer than the predicted time, and if it is, abnormality processing is performed. If the writing time is within the expected time, step S
6 to determine whether the writing is completed or not. If the writing is not completed, the process returns to step S5. If the writing is completed, the process is ended.

As described above, in this embodiment, since the power required for writing is estimated by obtaining the writing time, it is possible to determine whether or not writing can be performed with the remaining power. For this reason, in a system driven by a battery or the like, it is possible to prevent the power from being lost during the writing and to prevent the writing from being interrupted, thereby improving the reliability of the system. Further, by comparing the actual writing time with the estimated writing time, it is possible to detect an abnormality in the storage device, and by notifying the user by displaying the writing time, for example, Can be determined.

G. Next, an embodiment of the invention according to claim 1 of the present invention will be described. In most cases, the flag is determined by assigning one bit to one function. However, the flash memory structurally has a fatal cause of failure, that is, erasure cannot be performed due to excessive erasure, and the cell in which this has occurred remains high and does not return to low. Therefore, when a flag on the flash memory is made to correspond to one bit and one function, when the bit becomes defective, the validity of the flag is lost. The present embodiment addresses the above-described structural disadvantages of the flash memory and improves the reliability of flag determination by preparing a plurality of flags for the erase flag, the defective flag, the parity, etc. on the flash memory. An example is shown.

(1) Embodiment 1 FIGS. 54A and 54B show Embodiment 1. FIG. 54A shows a flag register, FIG. 54B shows an AND circuit for determination, and FIG. 54C shows a truth table. Is shown. In the present embodiment, as shown in FIG.
Prepare b4 and store it in the flag register. Then, when the flag is determined, a final determination result is obtained by calculating the logical product of these flags as shown in (b). Since the determination is made as described above, FIG.
Even if the bit b0 is fixed at the high level as in the row number 2 of the above, a correct result can be obtained as the logical product result. Similarly, even when the bit b4 is fixed at the high level as in the row number 3, a correct result can be obtained as the logical product result.

(2) Embodiment 2 FIGS. 55A and 55B show Embodiment 2. FIG. 55A shows a first flag register, FIG. 55B shows a second flag register,
(C) shows an AND circuit for performing flag determination. In this embodiment, the flags for the same function are stored in different flag registers. The flag is stored in bit b0 of the first flag register shown in FIG.
Flags corresponding to the same functions as the flags stored in the first flag register are stored in bits b0 and b2 of the second flag register shown in FIG. And
When determining the flag, the logical product of the flag is obtained by the logical product circuit shown in FIG. Also in this embodiment, as in the first embodiment, a correct determination result can be obtained even if a part of the flag is fixed at a high level. As described above, in the present embodiment, the determination of the flag is performed with a plurality of bits, so that a correct determination value can always be output as long as all the bits do not become defective.
The reliability of the flag determination can be improved.

H. In this embodiment, the storage device is composed of a plurality of chips and a flash memory in which a plurality of blocks are provided in each chip.
An example is shown in which the management table can be simplified and each block can be used on average in the system. In the embodiment described above, there is no restriction on the chip or block into which data is written, and data can be written in the sectors of all blocks. Therefore, it is necessary to provide a table for managing all areas. Simplifies flash memory management by fixing the data to be written in each chip and moving the blocks to be written in the chip to write data without having to manage the entire area. In addition, the use of each block is averaged. In this embodiment, the data to be written in the chip is reduced by a certain amount from the total capacity of the chip, and this fixed amount of blocks is used as a work block and a rescue block when a defective block occurs. Then, the arrangement of the data in the block is fixed, and when rewriting the data, if there is already valid data in the old block,
The data is saved in the SRAM 23 shown in FIG.
Writing is performed in an empty area together with the new data, and when the writing is successful, the block of the old data is erased.

Next, this embodiment will be described. FIG. 56 is a diagram showing a configuration in a chip, a block, and a sector in the present embodiment. As shown in FIG. 56, the chip has 2 Mbytes, and the chip has a No. 000-No. 511
Is divided into 512 blocks, and in each block,
No. of 528 bytes in one sector. 00-No. 07 eight sectors are provided. The block No. in FIG. And sector No. Indicates a physical address. Further, in the sector, as shown in the figure, a real data area of 256 bytes, an ECC area for a long instruction, a bad data flag, a bad block flag, a block address, a 256 byte
e is provided with an actual data area ECC area. The block address indicates the address value of the block pointer stored in the SRAM 23, and the sector determined to have no actual data is also written in the block address. By doing so, it is possible to determine that data having a large number of sector addresses is normal data at the time of hot-line insertion / removal. If the number of sector addresses is the same, the determination is made based on whether the ECC and checksum are correct. The bad block flag indicates the condition of the block.
Fh is a normal block, and ≠ FFh is a bad block. The bad data flag indicates a data condition, and normal data is indicated by FFh, and defective data is indicated by $ FFh. ECC area for Long instruction is up to 4 bytes
It is. The ECC area indicates the condition of actual data, and data correction and error detection are performed based on the value of this area.

FIGS. 57 to 61 are diagrams showing the write processing in the present embodiment. The present embodiment will be described with reference to FIGS. In this embodiment, the chip is No. 00-No.
04 shows the writing and management method when four work blocks are provided in each chip. FIG. 57 shows a state in which all blocks have been erased. As shown in FIG.
4 are provided, and data is written to the work blocks work01 to work04. Writing can be performed in sector units, but writing to the lower sector cannot be performed after writing to the upper sector, such as writing to sector 004 after writing to sector 005. In addition, data does not move beyond the chip, and the order of the sectors in the block does not change. Further, when the write data does not satisfy all the eight sectors, for example, when only the sectors 000 to 005 are written to the logical block address 00, the data of the sectors 000 to 005 are written and then the blocks 006 to 007 are written. Write only the address. In this case, since one block has eight sectors and five chips, the data of the logical address n is obtained by further dividing the quotient of (logical address n） 8) by 5. It is written to the surplus chip. For example, when n = 121, 121 ÷ 8 is 15 and the remainder is 1
15 ÷ 5 is 5 and the remainder is 0. 00 is written to the chip.

The data write processing in this embodiment is performed as follows. First, from the state where all the blocks shown in FIG. When 40 sectors 000 to 039 (logical addresses) are continuously written, data is written to work01 of each chip as shown in FIG. That is, the sector No. to be written first. 00
Since the logical block address of 00 to 007 is 00, the sector No. 000 to 007, and the chip No. Data is written from work01 pointed to by the 00 write pointer. The logical block address is managed on a chip-by-chip basis. In this case, since the logical block address 00 does not exist in the past, the chip No. Work01 of 00 is work0
Move to the free area next to 4. When writing for eight sectors is completed, the write pointer is set to the chip No. 01 w
ork01, and sector No. 008
Write the data of .about.015 to work01.

As described above, writing is performed on chip N
o. 04, the write pointer is set to chip N
o. It moves to work02 of 00. Next, from the state of FIG. 58, as shown in FIG. 120-19
Continuous writing of 72 sectors of 1 (logical address) is performed. In the same manner as described above, the sector number is stored in the SRAM 23 from the main unit.
The data of the sector Nos. 12
Since the logical block address of 03 to 0 to 127 is 03, the chip No. Data is written from work02 pointed to by the 00 write pointer. Then, as described above, the chip N
o. 00 work02 and work03 work01
Move to the next free space. Similarly, the sector No.
The data of 128 to 191 is stored in the chip No. 00-No. 0
Write to 4. Here, from the state of FIG.
o. When two sectors 002 to 003 are continuously written,
As shown in FIG. First, the sector number is stored in the SRAM 23. 002 to 003 are transferred. in this case,
If the write data is a sector No. Since it is 002-003,
Since the logical block address 00 is specified and exists in the past, it is determined that the old data needs to be saved. When the write data is the sector No. 002-003,
Since data is not written from the beginning of the logical block address 00, the data of the old logical block address 00 is stored in the SRAM 2
Evacuate to 3. When the write data is two sectors from the head of the logical block address, the write data is processed first, and then the data of the old logical block address is saved.

Next, the old data 0 saved in the SRAM 23
Chip N pointed to by write pointers 00, 001, 004, 005, 006, 007 and new data 002, 003
o. Write to work04 of 00. At that time, the writing is 000,001,002,003,004,005,
Write in the order of 006 and 007. Next, since the logical block address 00 already exists, the old logical block address is erased. Also, work04 is moved to the old logical block address 00. After performing two-sector continuous writing as described above, the power is turned off,
When turned on again, as shown in FIG. 61, the work block is specified after the used block. Also,
When the work blocks are designated as described above and all the work blocks cannot be designated even when the search is performed to the end of the chip, the process returns to the beginning of the chip and the work block is designated. In the above processing, when a block erase error occurs, 00h is set in the failure flag, and writing and reading of the block are disabled. In other words, a measure is taken by crushing one work block, and when there is no more work block, the system is set to be unable to write. If an error occurs during data saving, data is written after setting a bad data flag. In the read operation, even if an error is detected in the block, the block is not treated as a bad block. If a data write error occurs,
The block is regarded as a bad block. The method of setting the bad flag is to save the data once written, set only the bad block flag, and write again. The bad block flag is set for all sectors of the block in the same manner as in normal writing. If an error is detected during data erasure, the block is determined to be a bad block. The method of setting the bad block flag is not limited to setting only the bad block flag.

Write [00]. The defect processing is performed on all sectors of the block.

As described above, in this embodiment, the data to be written in each chip is fixed, and the block to be written is moved and written in the chip, so that it is not necessary to manage the entire area. Therefore, it is only necessary to manage data only in each chip, so that the management table can be saved and the speed of the write operation can be increased. In addition, since data was written to the work block and the work block was moved within the chip,
Each block can be used on average.

[0072]

As described above, in the present invention, a flag of a plurality of bits corresponding to the same function is recorded in the storage area 1a, and the flag is determined by the logical product of the flags. As long as all the bits do not become defective, a correct judgment value can always be output, and the reliability of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a principle diagram showing an overall schematic configuration of the present invention.

FIG. 2 is a principle diagram (1) showing an outline of the present invention.

FIG. 3 is a principle diagram (2) showing an outline of the present invention.

FIG. 4 is a principle view (3) showing an outline of the present invention.

FIG. 5 is a principle view (4) showing an outline of the present invention.

FIG. 6 is a block diagram showing a configuration of a storage device as a premise of the present invention.

FIG. 7 is a diagram showing the contents of an SRAM in the storage device.

FIG. 8 is a diagram showing the contents of a flash memory in a storage device.

FIG. 9 is a diagram (continued) showing the contents of the flash memory in the storage device.

FIG. 10 is a flowchart illustrating a write process in a storage device.

FIG. 11 is a flowchart (continued) showing a write process in the storage device.

FIG. 12 is a flowchart (continued) showing processing at the time of writing in the storage device.

FIG. 13 is a flowchart (continued) showing processing at the time of writing in the storage device.

FIG. 14 is a flowchart (continued) showing processing at the time of writing in the storage device.

FIG. 15 is a diagram showing an embodiment for suppressing variation in the number of times of erasing.

FIG. 16 is a diagram (continued) showing an embodiment for suppressing variation in the number of times of erasing;

FIG. 17 is a diagram (continued) showing an embodiment for suppressing variation in the number of times of erasing;

FIG. 18 is a diagram (continued) showing an embodiment for suppressing variation in the number of erasures.

FIG. 19 is a diagram (continued) showing an embodiment for suppressing variation in the number of erasures.

FIG. 20 is a flowchart illustrating a process according to an embodiment that suppresses variations in the number of erasures.

FIG. 21 is a diagram showing an embodiment of a process for eliminating erasable data.

FIG. 22 is a diagram (continued) illustrating an embodiment of processing for eliminating erasable data;

FIG. 23 is a diagram (continued) showing an embodiment of a process for eliminating erasable data.

FIG. 24 is a diagram (continued) showing an embodiment of a process for eliminating erasable data.

FIG. 25 is a flowchart showing an embodiment of a process for eliminating erasable data.

FIG. 26 is a diagram showing an embodiment of a process of creating a free area.

FIG. 27 is a diagram (continued) illustrating an embodiment of a process of creating a free area;

FIG. 28 is a diagram (continued) illustrating an embodiment of a process of creating a free area;

FIG. 29 is a diagram (continued) illustrating an embodiment of a process of creating a free area;

FIG. 30 is a diagram (continued) illustrating an embodiment of a process of creating a free area;

FIG. 31 is a diagram (continued) illustrating an embodiment of a process of creating a free area;

FIG. 32 is a diagram (continued) illustrating an embodiment of a process of creating a free area;

FIG. 33 is a flowchart of an embodiment of a process of creating a free area.

FIG. 34 is a diagram illustrating an example of an erasing process.

FIG. 35 is a diagram (continued) illustrating an example of an erasing process;

FIG. 36 is a flowchart of an embodiment of an erasing process.

FIG. 37 is a diagram showing a system configuration of an embodiment for improving a writing speed.

FIG. 38 is a diagram showing a first embodiment for improving the writing speed.

FIG. 39 is a diagram (continued) showing the first embodiment for improving the writing speed.

FIG. 40 is a diagram showing a second embodiment for improving the writing speed.

FIG. 41 is a diagram (continued) showing a second embodiment for improving the writing speed.

FIG. 42 is a diagram showing a third embodiment for improving the writing speed.

FIG. 43 is a diagram (continued) showing a third embodiment for improving the writing speed.

FIG. 44 is a diagram showing a fourth embodiment for improving the writing speed.

FIG. 45 is a diagram (continued) showing a fourth embodiment for improving the writing speed.

FIG. 46 is a diagram showing a fifth embodiment for improving the writing speed.

FIG. 47 is a diagram (continued) showing a fifth embodiment for improving the writing speed;

FIG. 48 is a flowchart of an embodiment for improving the writing speed.

FIG. 49 is a flowchart (continued) of the embodiment for improving the writing speed.

FIG. 50 is a flowchart (continued) of the embodiment for improving the writing speed.

FIG. 51 is a diagram showing an embodiment in which the address conversion decoding unit has two stages.

FIG. 52 is a diagram illustrating a state of a storage area in the embodiment of the writing time estimation processing.

FIG. 53 is a flowchart of an example of a writing time estimation process.

FIG. 54 is a diagram illustrating a first example of a flag determination process.

FIG. 55 is a diagram illustrating a second example of the flag determination process.

FIG. 56 is a diagram showing a configuration of a storage area in an embodiment for saving a management table.

FIG. 57 is a diagram showing an embodiment for saving the management table.

FIG. 58 is a diagram (continued) showing an embodiment for saving the management table;

FIG. 59 is a diagram (continued) showing an embodiment for saving the management table;

FIG. 60 is a diagram (continued) showing an embodiment for saving the management table.

FIG. 61 is a diagram (continued) showing an embodiment for saving the management table.

[Explanation of symbols]

 1, 20 Storage device 1a Storage area 1b Primary storage medium 1c Control means 1d, 1e Decoding table 2 Main body processing unit 21 Controller LSI 22 Processor 23 SRAM 24 Clock oscillator 25-1 to 25-5 Flash memory 26 EEPROM 261 Sector conversion Unit 301 Primary decoding unit 302 Secondary decoding unit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 29/00 631 G11C 17/00 601C 671 601B 639A 639C 639Z (72) Inventor Tomohiro Hayashi Kanagawa 4-36 Honcho-ku, Fujitsu Computer Technology Co., Ltd. (72) Inventor Shogo Shibasaki 4-36, Honmachi, Naka-ku, Yokohama-ku, Kanagawa Prefecture Co., Ltd. Fujitsu Computer Technology Co., Ltd. (72) Inventor Hiroyuki Ito Naka-Yokohama, Kanagawa Prefecture 4-36, Honcho-ku, Fujitsu Computer Technology Co., Ltd. (72) Inventor Masaru Takehara 4-36, Honmachi, Naka-ku, Yokohama-shi, Kanagawa Prefecture Inside Fujitsu Computer Technology Limited

Claims (1)

[Claims] Claims 1. A storage area that may not be erased.
(1a) A method of judging a flag recorded on a memory area (1a), in which a flag of a plurality of bits corresponding to the same function is recorded in a storage area (1a), and the flag is judged by a logical product of the flags. A method for determining a flag of a storage device, the method comprising: