JPS58127364A - Semiconductor ic device - Google Patents
Semiconductor ic deviceInfo
- Publication number
- JPS58127364A JPS58127364A JP57008935A JP893582A JPS58127364A JP S58127364 A JPS58127364 A JP S58127364A JP 57008935 A JP57008935 A JP 57008935A JP 893582 A JP893582 A JP 893582A JP S58127364 A JPS58127364 A JP S58127364A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- island region
- island
- conductivity type
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000926 separation method Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 7
- 230000002265 prevention Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 27
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 1
- 229910002090 carbon oxide Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はｔＣ（半導体集積回路装置）特Ｋ ＩＪニア部
とディジタル部を共存させたＩＣにおけるサイリスタ防
止技術に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thyristor prevention technique in an IC (semiconductor integrated circuit device) in which a special KJ near section and a digital section coexist.
第１図に示すようＫＰ−型Ｓｉ （シリコン）基板１
上に部分的に形成したＮ＋型埋込層２ａ、２ｂを介して
Ｎ−＠Ｓ＋層３をエピタキシャル成長させ、このＮ″″
″層３の表面からＰ−基板１に接続するアイソワーフ１
フ１層４によっていくつかの島領域（３ａ、３ｂ）Ｋ分
離し、一つの島領域（３ｍ）にリニア部として横形ＰＮ
Ｐ）ランジスタを形成し、隣れる島領域（３ｂ）にディ
ジタル部としてＩＩＬ （集積注入論理回路）を形成し
た場合に、ＰＮＰ）ランジスタのコレクタＰ＋層５が飽
和動作したときペースＮ一層３ａの正孔が増加し、基板
に流れ出しアイソレージ曹ンＰ＋層４の電位が高くなる
一方ＩＩＬのＮ＋埋込層２ｂ（インバース・トランジス
タのエミッタ）が接地されていることにより第２図に等
何回路で示すようなＰＮＰＮ動作（サイリスタ）を起し
リニア側から大電流■が集中的にＩ’Ｌの接地側へ流れ
てＩ！Ｌが動作しなくなる問題があった。As shown in Fig. 1, a KP-type Si (silicon) substrate 1
The N-@S+ layer 3 is epitaxially grown through the N+ type buried layers 2a and 2b partially formed thereon, and this N''''
″Isowarf 1 connecting to P-substrate 1 from the surface of layer 3
Several island regions (3a, 3b) K are separated by layer 4, and horizontal PN is formed as a linear part in one island region (3m).
When a P) transistor is formed and an IIL (integrated injection logic circuit) is formed as a digital part in the adjacent island region (3b), when the collector P+ layer 5 of the PNP) transistor is saturated, the positive polarity of the PNP layer 3a is As the pores increase and the potential of the isolation P+ layer 4 increases as the pores flow out into the substrate, the N+ buried layer 2b of the IIL (the emitter of the inverse transistor) is grounded, as shown in the circuit shown in FIG. A PNPN operation (thyristor) occurs, and a large current ■ flows intensively from the linear side to the ground side of I'L, causing I! There was a problem where L stopped working.
本発明は上記した問題点を解決するためになされたもの
であり、その目的とするところはリニア部とＩＬＬ部の
境界に生じるサイリスクを防止するＩＣ構造の提供にあ
る。The present invention has been made to solve the above-mentioned problems, and its purpose is to provide an IC structure that prevents a risk from occurring at the boundary between the linear section and the ILL section.
以下実施例にそって本発明を詳述する。The present invention will be described in detail below with reference to Examples.
第３図はＩＬＬと９ エア部を有するＩＣＫ本発明を適
用した場合の一実施例を示すものであっエリニア部とＩ
”Ｌとの間に抵抗の島領域を介在させた例である。Figure 3 shows an embodiment of an ICK having an ILL and 9 air sections to which the present invention is applied.
This is an example in which a resistive island region is interposed between the "L" and "L".
同図において、１は共通のＰ−８五基板、２ａ。In the same figure, 1 is a common P-8 five board, 2a.
２ｂ・・・はＮ＋壌込地層３ａはリニア部となる島領域
のＮ−８ａ層、３ｂはＩ”Ｌ部となる島領域のＮ″″Ｓ
ｉ層、３ｃは３ａと３ｂとの関に介在させた第３の島領
域のＮ一層、４はＰ アイソレーン１フ層である。５は
リニア部ＰＮＰ）ランジスタのコレクタＰ＋層、６は同
じくエンツタＰ＋層である。2b... is the N+ embankment layer 3a is the N-8a layer in the island area that will be the linear part, and 3b is the N''''S layer in the island area that will be the I''L part.
The i layer, 3c is the N layer of the third island region interposed between 3a and 3b, and 4 is the P isolene 1f layer. 5 is the collector P+ layer of the linear part PNP transistor, and 6 is the collector P+ layer.
７はＩ’Ｌ部のインバースＮＰＮ）ランジスタのイー３
２層、８は同じくコレクタＮ＋層である。９は第３の島
領域Ｎ一層３Ｃの表ＩＩＫ設けた拡散抵抗Ｐ層である。7 is E3 of the inverse NPN) transistor in the I'L section.
The second layer and 8 are also collector N+ layers. Reference numeral 9 denotes a diffused resistance P layer provided in Table IIK of the third island region N layer 3C.
このようなＩＣ構造、において、リニア部とＩ”Ｌ部と
の関に第３の島領域を介在させることで、第ｐ＋、ベー
スＮ、アイソレージ嘗ンＰ＋とＩＬＬ側の埋込層Ｎ＋と
の間はＰ−基板１により隔てられ、すなわち抵抗Ｒ１が
挿入された回路と等価となり、ＮＰＮ）ランジスタのベ
ース・エミッタ電圧■□がＲ１での電圧ドロップで動作
しＫ＜くなると共に実効的ベース巾が島領域によっ℃大
きくなることでｈ□を大巾に低下させ全体としてサイリ
スタ動作を防止する。したがって前記発明の目的を達成
できる。In such an IC structure, by interposing the third island region between the linear part and the I"L part, the connection between the p+, base N, isolation P+ and the buried layer N+ on the ILL side is improved. The circuit is separated by the P-substrate 1, that is, it is equivalent to a circuit in which a resistor R1 is inserted, and the base-emitter voltage of the NPN transistor operates due to the voltage drop at R1, and as K becomes less, the effective base width increases. As the temperature increases due to the island region, h□ is greatly reduced and thyristor operation is prevented as a whole.Therefore, the object of the invention can be achieved.
本発＃４によれば、リニア部とＩ”Ｌ部との間に単に第
３０島領域を設けることでサイリスク防止ができるが、
この第３の島領域に拡散１層９を設けてこの島電位を高
電位（例えば■。、）に接続し。According to the present invention #4, the risk can be prevented by simply providing the 30th island region between the linear part and the I''L part.
A diffusion layer 9 is provided in this third island region, and this island potential is connected to a high potential (for example, ■).
２層９を抵抗又は配線の一部としてこの第３の島自体を
抵抗として（エピタキシャル抵抗）利用することｋより
、集積度を損うことなく前記目的を達成できる。By using the second layer 9 as a resistor or part of the wiring and using the third island itself as a resistor (epitaxial resistor), the above object can be achieved without impairing the degree of integration.
本発明は前記実施例に＠定されず、これ以外にも下記の
ような変形例を有する。The present invention is not limited to the above-mentioned embodiments, but includes the following modifications in addition to the above embodiments.
（１） Ｉ）エア部とＩ”Ｌ部との間に形成する第３
の島領域な工！Ｌ部を包囲するよ５に形成する。(1) I) The third part formed between the air part and the I"L part
A craft in the island area! 5 to surround the L part.
（２）各島領域を分けるアイソレーション部は拡散ＰＭ
ＩＩＣ限らず、選択酸化により形成したアイソレーショ
ン酸化膜であってもよい。この場合、隣り合う島領域の
間のチャネルストッパとしてアイソレージ曹ン酸化膜の
直下ＫＰ層を設けるのが畳通であるがこのＰ層がリニア
部のトランジスタの飽和によって■ルのＮ＋場込地層の
間ｋＰＮＰＮ動作（サイリスク）を起す場合に本発明を
同様に適用できる。(2) The isolation part that separates each island area is a diffused PM
It is not limited to IIC, but may be an isolation oxide film formed by selective oxidation. In this case, it is a good idea to provide a KP layer directly under the isolation carbon oxide film as a channel stopper between the adjacent island regions, but this P layer will cause the N+ field layer in the The present invention can be similarly applied to cases in which inter-kPNPN operation (silisk) occurs.
本発明はリニア部とＩ”Ｌ部が共存する全ての■ＣＫ応
用できるうThe present invention can be applied to all CKs where a linear part and an I''L part coexist.
第１図は一つの半導体基板Ｋ ＩＪ ニア部とＩ！Ｌを
共存させるＩＣの例を示す断面図、第２図は１１１図の
ＩＣにおけるサイリスタ原理を示す等価回路図である。
第３図は本発明による１７ ニア部とＩ”Ｌを共存させ
るＩＣの一例を示す正面断面斜面図。
第４図は第３図のＩＣにおけるサイリスタ防止原塩を示
す等価回路図である。
１・・・Ｐ−基板、２・・・Ｎ＋埋込層、３・・・Ｎ一
層（島１［域）、４・・・Ｐ＋アイソレージ璽ン、５・
・・Ｐ＋コｖクタ、６・・・Ｐ＋エミッタ、７・・・Ｐ
ペース、８・・・Ｎ＋コレクタ、９・・・Ｐ拡散抵抗。Figure 1 shows the near part of one semiconductor substrate K IJ and I! FIG. 2 is a sectional view showing an example of an IC in which L coexists, and FIG. 2 is an equivalent circuit diagram showing the thyristor principle in the IC shown in FIG. FIG. 3 is a front sectional slope view showing an example of an IC in which the 17 near part and I"L coexist according to the present invention. FIG. 4 is an equivalent circuit diagram showing a thyristor prevention raw salt in the IC of FIG. 3. 1 ...P-substrate, 2...N+ buried layer, 3...N single layer (island 1 [area)], 4...P+ isolation board, 5...
・・P+contact, 6・P+emitter, 7・P
Pace, 8...N+ collector, 9...P diffusion resistance.
Claims (1)
を介して第２導電型半導体層が形成され、第２導電型半
導体層は表面から第１導電型基体に接続する第１導電型
分離層によっていくつかの島領域に分けられ、第１の島
領域に飽和動作する半導体素子が形成され、第２の島領
域に第２導電型高濃度埋込層を接地した半導体回路が形
成された半導体集積回路装置において、第１の島領域と
第２の島領域の間に第３０島領域を介挿したことを特徴
とする半導体集積回路装置。 ２、上記第３の島領域を抵抗素子として形成する特許請
求の範囲第１項に記載の半導体集積回路装置。[Claims] 1. A second conductivity type semiconductor layer is formed on a first conductivity type semiconductor substrate via a second conductivity type high concentration buried layer, and the second conductivity type semiconductor layer is formed from the surface of the first conductivity type semiconductor substrate. It is divided into several island regions by a first conductivity type separation layer connected to the mold substrate, a semiconductor element that operates in saturation is formed in the first island region, and a second conductivity type is buried in a high concentration in the second island region. 1. A semiconductor integrated circuit device in which a semiconductor circuit with a grounded layer is formed, characterized in that a 30th island region is interposed between the first island region and the second island region. 2. The semiconductor integrated circuit device according to claim 1, wherein the third island region is formed as a resistive element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57008935A JPS58127364A (en) | 1982-01-25 | 1982-01-25 | Semiconductor ic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57008935A JPS58127364A (en) | 1982-01-25 | 1982-01-25 | Semiconductor ic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58127364A true JPS58127364A (en) | 1983-07-29 |
Family
ID=11706519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57008935A Pending JPS58127364A (en) | 1982-01-25 | 1982-01-25 | Semiconductor ic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58127364A (en) |
-
1982
- 1982-01-25 JP JP57008935A patent/JPS58127364A/en active Pending
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