JPS58127328A - Etching method for insulating protection film of semiconductor substrate - Google Patents

Etching method for insulating protection film of semiconductor substrate

Info

Publication number
JPS58127328A
JPS58127328A JP1037282A JP1037282A JPS58127328A JP S58127328 A JPS58127328 A JP S58127328A JP 1037282 A JP1037282 A JP 1037282A JP 1037282 A JP1037282 A JP 1037282A JP S58127328 A JPS58127328 A JP S58127328A
Authority
JP
Japan
Prior art keywords
film
semiconductor substrate
water solution
subjected
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1037282A
Other languages
Japanese (ja)
Inventor
Tadahiro Nakamichi
中道 忠弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP1037282A priority Critical patent/JPS58127328A/en
Publication of JPS58127328A publication Critical patent/JPS58127328A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

PURPOSE:To remove stains from an insulating protection film and to improve the shape of a stage, by making a window in the film by a dry-etching processing, and then subjecting the same to immersion processing with an HF water solution. CONSTITUTION:The result of analysis of a semiconductor substrate just after a window is opened in an insulating protection film by a dry-etching processing is indicated by a broken line 1, while the result of analysis of the surface of the semiconductor substrate which is subjected to an immersion processing for a short time thereafter with an HF water solution is indicated by a broken line 2. The comparison between these broken lines 1 and 2 shows that C, F, Mg, Na, K, etc. are reduced more in the substrate subjected to the additional immersion processing than in the substrate not subjected thereto, and that the additional immersion processing with the HF water solution is effective for removing stains on the surface. In practice the substrate subjected to the immersion processing with the HF water solution is excellent in the bonding property with an Al film or an Al alloy film, the corners of a staged part are chamfered, and the coating property of the Al film or the Al alloy film is also excellent.

Description

【発明の詳細な説明】 本発明は、半導体基板上の81酸化膜を、ガスプラズマ
を利用するドライエツチング処M1.によって蝕刻する
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention processes an 81 oxide film on a semiconductor substrate by a dry etching process M1. Concerning the method of etching by.

半導体集積回路の絶縁保護膜として、一般的KP (I
Jン)拡散されたS(酸化11(P2O膜)が使用され
ている。この絶縁保II膜(PEIG膜)K窓あけした
後、電極や配線材料として、五!膜あるいはム!合金膜
を蒸着し、絶縁保I!膜下の各素子間の相互接続を行な
っている。ここでムj膜あるいはAj合金膜と、窓あけ
したところの各素子との接合性が良い(電気抵抗が低い
)ことが重要である。又、ai酸化膜を窓あけすると、
そこに段差が生ずるが、この段差部においてもムj膜あ
るいはム!合金膜の被覆性が良く、断線しないことが重
要である。
General KP (I) is used as an insulating protective film for semiconductor integrated circuits.
J) Diffused S (oxidized 11 (P2O film)) is used. After opening the K window in this insulating II film (PEIG film), a 5! film or a MU! alloy film is used as an electrode or wiring material. It is vapor-deposited and interconnects between each element under the insulation insulation film.Here, the bonding between the Muj film or the Aj alloy film and each element where the window is opened is good (low electrical resistance). ) is important.Also, when opening the ai oxide film,
There is a step, but even at this step there is a muj membrane or mu! It is important that the alloy film has good coverage and does not break.

ところで、この絶縁保護膜(P2O膜)への窓あけは、
非常に微細な加工(2〜4μm )が要求されるために
、CX’In (7レオン)系統のガスプラズマを応用
したドライエツチング方法が用いられている。ドライエ
ツチング処理は、微細加工ができるだけでなく、従来の
水浴液(例えば7ツ酸水溶液)利用のエッチ処理に比べ
、廃液の必要性がなく、無公害化、あるいは作業の自動
化が図れるなどの多くの利点をもつ。
By the way, opening a window in this insulating protective film (P2O film) is as follows:
Since very fine processing (2 to 4 .mu.m) is required, a dry etching method using CX'In (7 Leon) type gas plasma is used. Dry etching processing not only enables microfabrication, but compared to conventional etching processing that uses a water bath solution (for example, aqueous hexachloric acid solution), dry etching processing does not require waste fluid, is non-polluting, and can be automated. It has the following advantages.

しかしながら、絶縁保護膜の窓あけをドライエツチング
処理した場合、半導体基板上に、反応ガスの成分、ある
いは反応生成物が付着したシ、浅く拡散している。この
現象は、工M五分析など行なうことで、付着あるいは拡
散された成分又は反応生成物を明らかにできる。
However, when the opening of the insulating protective film is subjected to dry etching, components of the reactive gas or reaction products adhere to the semiconductor substrate and are diffused in a shallow manner. This phenomenon can be clarified by performing engineering M5 analysis or the like to identify the components or reaction products that have adhered or diffused.

分析結果の1例を第1図に示す。これらの付着物あるい
は反応生成物が半導体基板上に残っていると、窓あけし
たところのムJW#と基板との接合性が惑い(電気抵抗
が高い)ことが明らかにされている。
An example of the analysis results is shown in Figure 1. It has been revealed that if these deposits or reaction products remain on the semiconductor substrate, the bonding properties between the substrate and the MJW# where the window is opened will be compromised (the electrical resistance will be high).

又、ドライエツチング処理にて窓あけしたところの断面
形状は第2図に示すように、角度80〜90° で非常
に急使であるために1ム!又はムj合金膜の被覆性が悪
く、段差部で断線する危険性が高い。フォトレジスト1
は81酸化膜2をパターン形成するための被覆材である
Also, the cross-sectional shape of the window opened by dry etching is at an angle of 80 to 90 degrees, as shown in Figure 2, and is very courier, so it is 1 mm! Alternatively, the coverage of the Mj alloy film is poor, and there is a high risk of wire breakage at the stepped portion. Photoresist 1
is a covering material for patterning the 81 oxide film 2.

こうした欠点を取り除くために1絶縁膜(PaGI[)
t−ドライエツチング処理した後、H4F(7ツ酸)水
溶液に短時間浸漬処理することが、非常に有効である。
In order to eliminate these drawbacks, one insulating film (PaGI[)
After the t-dry etching treatment, it is very effective to immerse the material in an aqueous H4F (heptonic acid) solution for a short time.

111水溶液への浸漬処理によシ、半導体基板上に付着
したガス成分あるいは反応生成物が、かなシ除去される
ことが確認された。
It was confirmed that gas components or reaction products adhering to the semiconductor substrate were completely removed by the immersion treatment in the 111 aqueous solution.

又、B(酸化膜の窓あけ部の段差部の角が面取りされ、
ムj又はム!合金膜の被覆性も改善されるという効果も
確認できた。本発明は、このように絶縁保護膜(PEG
膜)をドライエツチング処理にて窓あけした後、HIF
HF水溶液浸漬処理すことを特徴とする半導体基板の絶
縁保護膜の蝕刻方法である。
In addition, B (the corner of the step part of the oxide film opening part is chamfered,
Muj or mu! It was also confirmed that the coverage of the alloy film was improved. The present invention thus provides an insulating protective film (PEG).
After opening the window by dry etching the film), HIF
This is a method of etching an insulating protective film of a semiconductor substrate, which is characterized by immersion treatment in an HF aqueous solution.

次に本発明の詳細な説明する。第3図には絶縁保護膜(
pse膜)をドライエツチング処理にて窓あけした直後
の半導体基板の分析結果例を折線lとして、又、その後
HIFHF水溶液短時間浸漬処理した半導体基板上の分
析結果の1例を折線2として比較して示す。第3図にお
いて、示し丸ように、HF水溶液による浸漬処理を追加
したものの分析結果例2は、浸漬処理のない分析結果例
1に比べC(炭素) t ’ (フッ素) t Mrt
 (マグネシウム)9Ma(ナトリウム)、K(カリウ
ム)などが低減し、HF水溶液の浸漬処理を追加するこ
とか表面汚染の除去に大変効果的であることが理解でき
る。実際、このようVcHIF水溶液浸漬処理をしたも
のは、ムjH1hるいはムj合金膜との接合性が良い(
電気抵抗が低い)仁とが確認できた。
Next, the present invention will be explained in detail. Figure 3 shows an insulating protective film (
An example of an analysis result of a semiconductor substrate immediately after dry etching (pse film) to open a window is shown as a broken line 1, and an example of an analysis result of a semiconductor substrate that has been subsequently immersed in a HIFHF aqueous solution for a short time is shown as a broken line 2. Shown. In Fig. 3, as shown in the circle, analysis result example 2 with addition of immersion treatment with HF aqueous solution has a lower C (carbon) t' (fluorine) t Mrt than analysis result example 1 without immersion treatment.
(Magnesium) 9Ma (sodium), K (potassium), etc. are reduced, and it can be understood that adding HF aqueous solution immersion treatment is very effective in removing surface contamination. In fact, products subjected to such VcHIF aqueous solution immersion treatment have good bonding properties with MujH1h or Muj alloy films (
It was confirmed that the electrical resistance was low.

また、第4図1(HIF水浴液処理した場合の窓あけ部
の断面形状を示す。段差部の角が面取シされ、ムj膜あ
るいはムj合金属の被覆性が良好となることが理解でき
る。
In addition, Fig. 4 (1) shows the cross-sectional shape of the window opening after HIF water bath treatment.The corners of the stepped portions are chamfered to improve the coverage of the muj membrane or the muj alloy. It can be understood.

以上説明し九ように、本発明は半導体集積回路の絶縁保
−膜として用いたPf3Gmを、HF水溶液にて浸漬す
ることで、半導体基板上の汚染除去及び段差形状の改良
を効果的にかつ、簡単に行なうものである。
As explained above, the present invention effectively removes contamination and improves the shape of steps on a semiconductor substrate by immersing Pf3Gm used as an insulating film in a semiconductor integrated circuit in an HF aqueous solution. It's easy to do.

なお、絶縁保護膜として、リン拡散したPsa膜につい
て実施例説明をしたが、リン以外の元素を含んだS(酸
化膜、あるいは単なる8(酸化膜についても適用できる
ことは云うまでもない。
Although the embodiment has been described using a Psa film in which phosphorus is diffused as the insulating protective film, it goes without saying that the present invention can also be applied to an S(oxide) film containing an element other than phosphorus, or a simple 8(oxide) film.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図には、絶縁保護Jll(P2O膜)をドライエツ
チング処理して窓あけした直後の表面分析結果の1例を
、第2図にはその時の窓あけ部の断面形状を示す。第3
図には、ドライエッチ後にHF水溶液浸漬処理を行なっ
た場合と行なわない場合を比較した表面分析結果例を示
す。 ま九第4図には、HF水溶液浸漬処理した時の断面形状
を示す。 第2図において l・・7オトレジスト 2・・8イ酸化膜 3・・半導体基板 を示す。 以   上 出願人 株式会社諏訪精工舎 代理人 弁理土量 上  務 第・1図 1 第2図
FIG. 1 shows an example of the surface analysis results immediately after dry etching the insulation protection Jll (P2O film) to open a window, and FIG. 2 shows the cross-sectional shape of the window at that time. Third
The figure shows an example of surface analysis results comparing cases where HF aqueous solution immersion treatment was performed after dry etching and cases where HF aqueous solution immersion treatment was not performed. FIG. 4 shows the cross-sectional shape when immersed in an HF aqueous solution. In FIG. 2, a semiconductor substrate is shown. Applicant Suwa Seikosha Co., Ltd. Agent Patent Volume Volume 1 Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 111絶嶽保護膜としてS<酸化膜を形成する工程(2
1上記S(酸化膜を覆うフォトレジストの塗布工程及び
霧光工程 131上記牛導体基板をプラズマガスによシトライエツ
チングする工程 上記工程を含み、第3の工程の後、HP(7ツ酸)水浴
液浸漬を行なうことを特徴とする半導体基板の絶縁保護
膜の蝕刻方法。
[Claims] 111 Step of forming an S<oxide film as a protective film (2)
1 above S (coating process of photoresist covering the oxide film and fogging process 131 process of etching the above-mentioned conductor substrate with plasma gas). After the third process, HP (hetamine acid) A method for etching an insulating protective film of a semiconductor substrate, the method comprising immersing a semiconductor substrate in a water bath.
JP1037282A 1982-01-26 1982-01-26 Etching method for insulating protection film of semiconductor substrate Pending JPS58127328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1037282A JPS58127328A (en) 1982-01-26 1982-01-26 Etching method for insulating protection film of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1037282A JPS58127328A (en) 1982-01-26 1982-01-26 Etching method for insulating protection film of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS58127328A true JPS58127328A (en) 1983-07-29

Family

ID=11748314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1037282A Pending JPS58127328A (en) 1982-01-26 1982-01-26 Etching method for insulating protection film of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS58127328A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194833A (en) * 1985-02-25 1986-08-29 Fujitsu Ltd Etching method for silicon substrate
JPS62250645A (en) * 1986-04-24 1987-10-31 Hoya Corp Washing method
JPS62272541A (en) * 1986-05-20 1987-11-26 Fujitsu Ltd Surface treating method for semiconductor substrate
JPS63178542A (en) * 1987-01-19 1988-07-22 Rohm Co Ltd Isolation method of dielectric for semiconductor device
JPH02219231A (en) * 1988-12-21 1990-08-31 American Teleph & Telegr Co <Att> Method of reducing mobile ions its semiconductor integrated circuit
JPH0426120A (en) * 1990-05-22 1992-01-29 Nec Corp Treating method for semiconductor substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49100974A (en) * 1973-01-31 1974-09-24
JPS5021679A (en) * 1973-06-25 1975-03-07
JPS5240978A (en) * 1975-09-27 1977-03-30 Fujitsu Ltd Process for production of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49100974A (en) * 1973-01-31 1974-09-24
JPS5021679A (en) * 1973-06-25 1975-03-07
JPS5240978A (en) * 1975-09-27 1977-03-30 Fujitsu Ltd Process for production of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194833A (en) * 1985-02-25 1986-08-29 Fujitsu Ltd Etching method for silicon substrate
JPS62250645A (en) * 1986-04-24 1987-10-31 Hoya Corp Washing method
JPS62272541A (en) * 1986-05-20 1987-11-26 Fujitsu Ltd Surface treating method for semiconductor substrate
JPS63178542A (en) * 1987-01-19 1988-07-22 Rohm Co Ltd Isolation method of dielectric for semiconductor device
JPH02219231A (en) * 1988-12-21 1990-08-31 American Teleph & Telegr Co <Att> Method of reducing mobile ions its semiconductor integrated circuit
JPH0426120A (en) * 1990-05-22 1992-01-29 Nec Corp Treating method for semiconductor substrate

Similar Documents

Publication Publication Date Title
US4264374A (en) Cleaning process for p-type silicon surface
EP0617459A2 (en) Semiconductor wafer cleaning and rinsing techniques
JPH05259066A (en) Positive photoresist removing liquid and manufacture of semiconductor device
JPS58127328A (en) Etching method for insulating protection film of semiconductor substrate
US4430152A (en) Process for fabricating a semiconductor device
JPH03228327A (en) Cleaning method of semiconductor wafer
JPS62272541A (en) Surface treating method for semiconductor substrate
JPS62281332A (en) Etching method
KR100211648B1 (en) Method for generating semiconductor wafer
JP2002162755A (en) Method of manufacturing semiconductor device
JPH09213612A (en) Method for manufacturing semiconductor device and rinse
JPS58143532A (en) Processing method for insulating film
US4773940A (en) Lead frame preparation for solder dipping
JPS63173331A (en) Manufacture of semiconductor device
JPS594027A (en) Manufacture of semiconductor device
JP2005123494A (en) Manufacturing method and analysis method of semiconductor device
JPH0629647A (en) Peeling method of photo resist
JP2608972B2 (en) Semiconductor device defect detection method
JPH0867993A (en) Production of semiconductor device and method for inspecting semiconductor device
JPH07206474A (en) Treatment of transparent glass substrate
JPH07249607A (en) Manufacture of semiconductor device
JPS61270833A (en) Manufacture of semiconductor device
JPS5923106B2 (en) Manufacturing method of semiconductor device
JPH0475324A (en) Removal method of resist film
CN117806139A (en) Photoresist cleaning solution