JPS58143532A - Processing method for insulating film - Google Patents
Processing method for insulating filmInfo
- Publication number
- JPS58143532A JPS58143532A JP2591482A JP2591482A JPS58143532A JP S58143532 A JPS58143532 A JP S58143532A JP 2591482 A JP2591482 A JP 2591482A JP 2591482 A JP2591482 A JP 2591482A JP S58143532 A JPS58143532 A JP S58143532A
- Authority
- JP
- Japan
- Prior art keywords
- film
- section
- etching
- psg
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000005368 silicate glass Substances 0.000 claims description 2
- 239000005360 phosphosilicate glass Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 16
- 239000000758 substrate Substances 0.000 abstract description 5
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 abstract description 4
- 239000007864 aqueous solution Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract 7
- 239000000377 silicon dioxide Substances 0.000 abstract 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract 7
- 229910052682 stishovite Inorganic materials 0.000 abstract 7
- 229910052905 tridymite Inorganic materials 0.000 abstract 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 25
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 241000218691 Cupressaceae Species 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 235000013372 meat Nutrition 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
発明の嬌する技術分野
この発明は集積回路などに設けられる絶縁膜の一口部の
形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a method for forming a mouth portion of an insulating film provided in an integrated circuit or the like.
従来技術とその問題点、
調えば半導体集積回路の製造において、表面な被憶する
Ｊｌ！ｌ緻属を窓あけし、内部と接続するように表面上
に導電配線を形成する場合に、窓の段差部分でｌｌＦｒ
＊を生ずることを防ぐために絶縁膜の開口部周縁をテー
パー形状に１あけすることが惠費である。従来より、こ
の檜のテーパー形状にする工′ツチング方法が檎々提案
されているが、簡便で充分ＫＩＩＩｌ＃された絶縁展開
口部の形成は未だ満足１４のはない。Prior art and its problems If you look into the manufacturing of semiconductor integrated circuits, Jl! When forming a conductive wiring on the surface to connect with the inside by opening a window in the lFr
In order to prevent * from occurring, it is advantageous to make the periphery of the opening in the insulating film tapered. In the past, many methods have been proposed for making this cypress into a tapered shape, but there is still no satisfactory way to form an insulation expansion opening that is simple and has a sufficient KIIII#.
第１図に示している例はウェットエツチングによってス
ルーホールを形成した断面図で、半導体基板１上に被着
したシリコン酸化ｐＩ４（８４０２） ２にフォトリン
グラフイープロセスを用いてレジストマスク３をパター
ニング形成し、弗＠ （ｗ’）とフッ化アンモニウム（
ＮＨ４Ｆ）とＯｓ合浴溶液よるエツチングでｌＫあけし
、スルーホールの開口１！４４の周縁に傾斜をりけ九も
Ｏであるが、断面を詳細にＩ！察すると、エッ、チンダ
ははぼ岬方的に進行するため、−口部４の上部周縁は鑞
ぽ垂直に切り立つた形状となっている。このよう碌開口
部Ｋｍいて配線を設けると、開口部周縁において断線の
おそれがきわめて強い。基盤加熱しながら１看した金−
を配線に用いた場合には断線の確率は減少するが完全で
はなく、またこのような場合には段差部で配線の厚みが
きわめて薄くなるおそれがある。The example shown in FIG. 1 is a cross-sectional view in which through holes are formed by wet etching, and a resist mask 3 is patterned using a photophosphorographic process on silicon oxide pI4 (8402) 2 deposited on a semiconductor substrate 1. form, fluoride (w') and ammonium fluoride (
A hole was etched by etching with a mixed bath solution of NH4F) and Os, and a slope was cut around the periphery of the through-hole opening 1!44. As you can see, since Chinda progresses in the direction of the cape, the upper periphery of the mouth part 4 has a vertically steep shape. If the wiring is provided in such a way as to be close to the opening Km, there is a very strong possibility that the wiring will break at the periphery of the opening. The money I watched while heating the base.
If this is used for wiring, the probability of wire breakage is reduced, but not completely, and in such a case, the thickness of the wiring may become extremely thin at the stepped portion.
発明の目的
本発明はテーパー形状を有する絶縁Ｊｉ１１開口部を簡
便に形成する方法を提供することを目的とする。OBJECTS OF THE INVENTION It is an object of the present invention to provide a method for easily forming an insulating Ji11 opening having a tapered shape.
発明の概要
本発明はｌ：！ ｉｏ２とり／珪酸ガラス（Ｐ２Ｏ）と
を形成する工程と、これらＰＳＧ膜、ＳｔＯ，膜を選□
択的に鵬次除去する工程と、前記Ｓ！０２＃ｊｊ！を薄
く残すようにする工程と、除去されずに残っていゐＰ２
Ｏ膜と前記１也の薄く残され九ｓｉｏ２ｇとを同時に除
去で色る手段を用いて除去し所望の開口を前記ＳｔＯ。SUMMARY OF THE INVENTION The present invention is l:! The process of forming io2/silicate glass (P2O) and the selection of these PSG films, StO, and films □
selectively removing the S! 02#jj! A process of leaving a thin layer of P2 remaining without being removed.
The O film and the thin remaining 9 sio2g of the above 100% are removed at the same time using a removing means, and the desired opening is formed with the above StO.
膿に形成する絶縁膜の加工方法である。This is a method for processing the insulating film that forms on pus.
発明の効果
本発明によれば、断線の発生しないスルーホールなどの
絶縁膜開口部を簡＠ｌ！に形成できる。Effects of the Invention According to the present invention, insulating film openings such as through holes that do not cause disconnection can be easily formed! can be formed into
発明の実施例
以Ｆ図向を用いて詳細Ｋａ明すると、従来よりＰ８Ｇｉ
＠とｅｔｊ０２膜とを積層してスルーホールを形成する
方法は一部で使用されており、第２図に示すように８ｉ
０．膜５、ＰＳＧ膜６の積層膜上にレジストマスクをパ
ターニング形成し、スルーホール開口Ｗ１部４のＰ８Ｇ
ｌ１６部分をウェットエツチングして、次に［１３図に
示すように８４０２ｇ５部分をウェットエツチングして
いる。このようにして形成され九スルーホールは８ｉｏ
２膜５ｓ分は完全になにらかなテース−形状とすること
ができるが、ｆＰ細に観察するとＰＳＧ膜部分は図の如
く段差を形成し、導電性配線をその上部に形成し九場合
には断崖のおそれが依然としである。とくに導電性配−
の厚みが開口部段差にくらべて薄い場合にはそのおそれ
が大きい。基板がシリコンである場＆には、およそ１０
００℃１度の高温中で熱ｌ６１１を施し、ＰＳＧ膜を流
動状態とせしめることＫ１１ｌＰ８Ｇ膜６段差部に丸み
をつけることが可能である。しかし砒化ガリウ１
ム（ＧａＡｓ）をはじめとする化合物半導体の場合には
、高温熱Ｊ６珊によ参基板構成元素の蒸発等によ抄基板
の変負が起りやすく、と＜ＫＩＩＩＴ紀Ｐ８Ｇを流動状
態とぜしめゐような高温熱処理は実施不ｉ＝Ｊ能である
。From the embodiments of the invention, the details are explained using the F diagram.
The method of forming through holes by laminating @ and etj02 films is used in some cases, and as shown in Figure 2, 8i
0. A resist mask is patterned on the laminated film of the film 5 and the PSG film 6, and P8G of the through-hole opening W1 portion 4 is formed.
The 116 portion was wet-etched, and then the 8402g5 portion was wet-etched as shown in Figure 13. The nine through holes formed in this way are 8io
2 films for 5 seconds can be made into a perfectly smooth tapestry shape, but when observed closely at fP, the PSG film part forms a step as shown in the figure, and conductive wiring is formed on top of it, and in some cases, it forms a cliff. There is still a risk that Especially conductive wiring
If the thickness of the opening is thinner than the step of the opening, there is a high possibility of this happening. If the substrate is silicon, approximately 10
By applying heat 1611 at a high temperature of 00° C. and 1° C. to bring the PSG film into a fluid state, it is possible to round the step portion of the K111P8G film 6. However, in the case of compound semiconductors such as gallium arsenide (GaAs), the strength of the substrate is likely to change due to evaporation of the constituent elements of the substrate due to high-temperature heat. It is impossible to perform high-temperature heat treatment that would interfere with the condition.
第４図ないし第６図は、化合物半導体に用いてと〈Ｋ効
果のある、本発明による絶縁膜の加工方法の一例を示す
工４１１新向図である。基板上に厚さ６０００Ｘ ｏ
５ｉＯｚ ＩＩＩ ａ、厚ｓ ｚｏｏｏＸｏｐｓｏＨ６
をｌ１ｊＫ形成し、レジストパター７７をＶスフとして
まずＰＳＧ膜６ｔｎ択的に除去する。この際、Ｐ８Ｇｊ
ｌ［６のエツチングは弗１１０．４〜ｏ、ａｌと弗化ア
ンモニウム２〜５嚢を含む水溶液を使用するが、Ｐ８Ｇ
ｊ１６のエツチング速度は別０２膜５のエツチング速度
の数分のｌであり、はぼＰ２Ｏのみをエツチングするこ
とができる。この工程を示す断面図は従来例の第２図と
同じである。この後部１ｉ１６９Ｇと弗化アンモニウム
３０優を含む水浴液を使用して別０１１１５の除去を行
うにの際、あらかじめ８ｉ（Ｊ、膜５のエツチング速度
を実験的に計測してエツチング時間の算出をしておき、
８ｉ０１膜５をｓｏｏｔｇ度残存させる、、−′”−’
＜第４図）。次にレジストを１１５図の如く剥離
した友、前記のＰ８Ｇ膜６のエツチング液を再び用いて
、窓部以外の表面に！ｌｌ＆っているＰ２Ｏ３［及び薄
く残存させた８４０！膜６を除去する。８ｉ０２膜５に
くらべてＰ８Ｇ膜６の工、チング速度は数倍であるから
、博く残存させた８ｉ０２ ［Ｉ５を適度完全に除去せ
しめた時点でエツチングの終了点とすれば、ＰＳ（）膜
６も壕九完全に窓部以外の１９ ｉｏ、膜５上から除去
さ−れる。以上の工程によってｓ６図の如く開口窓部の
下縁から上縁まで断面がなにらかなテーパー形状が形成
される。FIGS. 4 to 6 are diagrams of a process 411 showing an example of a method for processing an insulating film according to the present invention, which has a <K effect when used for compound semiconductors. Thickness 6000X o on board
5iOz III a, thickness s zooooXopsoH6
11jK is formed, and the PSG film 6tn is selectively removed using the resist pattern 77 as a V film. At this time, P8Gj
Etching of P8G 6 uses an aqueous solution containing 110.4-o, al and 2-5 capsules of ammonium fluoride.
The etching rate of J16 is a few fractions of the etching rate of Separate 02 film 5, and it is possible to etch only P2O. The cross-sectional view showing this step is the same as FIG. 2 of the conventional example. When removing another 01115 using this rear part 1i169G and a water bath containing 30% ammonium fluoride, the etching time was calculated by experimentally measuring the etching rate of the 8i (J) film 5 in advance. Keep it
8i01 film 5 remains to a sootg degree, -'"-'
<Figure 4). Next, remove the resist as shown in Figure 115 and use the etching solution for the P8G film 6 again to cover the surface other than the window! P2O3 [and a thin remaining 840! Remove membrane 6. The etching speed of the P8G film 6 is several times faster than that of the 8i02 film 5, so if the etching end point is when the remaining 8i02 [I5] is moderately and completely removed, the PS() film 6 is also completely removed from the top of the membrane 5 except for the window part. Through the above steps, a tapered shape with a smooth cross section from the lower edge to the upper edge of the opening window is formed as shown in Figure s6.
以上の説明から明らかなように、本実Ｍ１例によれば、
テーパー形状をもつ絶縁展開口部を簡便に開口すること
が可能とな抄、又、開口部のひろがりが少ないので微小
開口部の加工が可能となる。As is clear from the above explanation, according to the actual M1 example,
This makes it possible to easily open a tapered insulation development opening, and since the opening does not spread out much, it is possible to process a minute opening.
発明の他の実施例
本発明は上記実施例にとられれることなく、例えばＰ２
Ｏ膜と８＆０３腺の除去につ、エツト壬ツテングを用い
九が、リアクティブイオンエツチングのようなドライブ
エツチングを用いて奄よい。輩は薄く残存させた引０諺
膜を適度除去開口した段階で表面□Ｐ８０＠がほとんど
無くなっている状態であればよい。Other Embodiments of the Invention The present invention is not limited to the above-mentioned embodiments; for example, P2
For removal of the O membrane and the 8&03 gland, it is possible to use an etching method or a drive etching method such as reactive ion etching. It is sufficient if the surface □P80@ is almost completely removed when the thin remaining thin film is removed and opened.
ｗＩｒ肉図１講４凶ないし第６図は本発明の一実施例の
工程＃肉図である。Figures 1 to 6 are process # meat diagrams of an embodiment of the present invention.
ｌ・・・牛導体基板 ２．５・・・８ｉ０２ ６・・・ＰＥＧ ３．７・・レジストマスク ４・・・スルーホールの開口窓部 代理人 弁理士 則 近 憲 佑 （ほか１名） 第１図 第２図 第３図 第４図 第５図 第６図 ぐl...Cow conductor board 2.5...8i02 6...PEG 3.7...Resist mask 4...Through hole opening window Agent Patent Attorney Noriyuki Chika (1 other person) Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 ingredient
Claims (1)
これらリン珪酸ガラス膜及びシリコン酸化膜を選択的に
１拳次除去すゐ工１と、前記シリコン酸化膜を＊＜＊す
ようにする１根と、除去されずＶＣ′残されたリン珪酸
ガラス膜と前記工程で残された薄いシリコン酸化膜とを
同時に除去できる手段を用いて除去し所望の開口を前記
シリコン酸化膜に形成する１根とを含むことを特徴とす
る絶縁膜の加工方法。A step of forming a silicon oxide film and a silicate glass film,
Step 1 to selectively remove these phosphosilicate glass films and silicon oxide films, step 1 to make the silicon oxide film 1. A method for processing an insulating film, comprising: removing the film and a thin silicon oxide film left in the step using a means capable of simultaneously removing the film and forming a desired opening in the silicon oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2591482A JPS58143532A (en) | 1982-02-22 | 1982-02-22 | Processing method for insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2591482A JPS58143532A (en) | 1982-02-22 | 1982-02-22 | Processing method for insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58143532A true JPS58143532A (en) | 1983-08-26 |
Family
ID=12179040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2591482A Pending JPS58143532A (en) | 1982-02-22 | 1982-02-22 | Processing method for insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58143532A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5965465A (en) * | 1997-09-18 | 1999-10-12 | International Business Machines Corporation | Etching of silicon nitride |
| US6033996A (en) * | 1997-11-13 | 2000-03-07 | International Business Machines Corporation | Process for removing etching residues, etching mask and silicon nitride and/or silicon dioxide |
| US6117796A (en) * | 1998-08-13 | 2000-09-12 | International Business Machines Corporation | Removal of silicon oxide |
| US6150282A (en) * | 1997-11-13 | 2000-11-21 | International Business Machines Corporation | Selective removal of etching residues |
| US6200891B1 (en) | 1998-08-13 | 2001-03-13 | International Business Machines Corporation | Removal of dielectric oxides |
-
1982
- 1982-02-22 JP JP2591482A patent/JPS58143532A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5965465A (en) * | 1997-09-18 | 1999-10-12 | International Business Machines Corporation | Etching of silicon nitride |
| US6066267A (en) * | 1997-09-18 | 2000-05-23 | International Business Machines Corporation | Etching of silicon nitride |
| US6033996A (en) * | 1997-11-13 | 2000-03-07 | International Business Machines Corporation | Process for removing etching residues, etching mask and silicon nitride and/or silicon dioxide |
| US6150282A (en) * | 1997-11-13 | 2000-11-21 | International Business Machines Corporation | Selective removal of etching residues |
| US6117796A (en) * | 1998-08-13 | 2000-09-12 | International Business Machines Corporation | Removal of silicon oxide |
| US6200891B1 (en) | 1998-08-13 | 2001-03-13 | International Business Machines Corporation | Removal of dielectric oxides |
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| JPH02152258A (en) | Manufacture of intermediate oxide film for lsi |