JPS5812607B2 - Kanshiyouseigiyomeireihoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control command scheme for controlling interference in commonly accessible memory devices in a multi-processing system.

Multi-processing is an effective solution when a single central control unit cannot handle the required amount of processing.

FIG. 1 is a block diagram showing an example of a multi-processing type electronic exchange.

In the figure, M is a common memory device, CPUO, CPU
1 is two control devices, and SP is a communication path system (SP system) as a controlled object.

The processing by the control unit CPU of an electronic exchange is started periodically and consists of control processing (high-level processing H/SHI) of the speech line system (SP system) that strictly requires real-time performance, and other internal processing (low-level processing). level processing).

High-level processing with a high priority is dialing.
There are pulse counting, transmission, communication path control, billing pulse control, etc., and low-level processing with low priority includes analysis of received digits, selection of communication path, etc.

Switching between both processes is done using a constant cycle interrupt CLOC from the outside.
It is usually based on K.INRP.

That is, the control unit CPU has an interrupt function, and if a clock interrupt occurs while low-level processing is being executed, the processing being executed is interrupted, high-level processing is performed first, and then low-level processing is started from the interruption point. - Level processing is restarted.

FIG. 2 is a detailed block diagram of FIG. 1, and FIG. 3 is an instruction flowchart when accessing the common memory device in FIG.

In FIG. 2, HLP is high level processing, LLP is low level processing, CLOCK-INRPI is an external clock interrupt, M is a common memory device, COM-RSC is a common resource, and Queue is a queue.

Both control devices CPUO and CPU1 in FIG. 2 each perform a high-level process HLP activated by a periodic external clock interrupt CLOCK/INRP, and after executing the high-level process, control is passed from these to the Memory device M
Low level processing LI, P is performed to process each call using the resources COM RSC, samurai matrix, etc.

Here, the common data in the memo IJM in FIG.
Samurai matrix Queue etc. are both control devices CPUO, CPU1.
It is accessed from both levels HL and LL.

This gives rise to the following problem.

l) Conflict due to simultaneous access from both control units CPUO and CPU1, which is unique to multi-processing systems.

:i) Interference due to accesses from high level HL and low level LL in each control unit CPUO or CPUI.

Specifically, the problem 1) is as follows.

When accessing an area in the common memory device M (common source, queue, etc.) that may be accessed by both CPU0 and CPU1, the CPUO with the highest priority first reads it once in one memory cycle, and then The next memory cycle is used to write new information, resulting in a total of two memory cycles to be written.

However, after the CPUO reads the information in the first memory cycle, the CPU 1 regards the address as empty and reads the same information in the next memory cycle.

Then, after the CPUO rewrites the address, the CPU1 further rewrites the address in the next memory cycle, and as a result, the information written by the CPUO is destroyed.

A known technique for preventing this is the use of the Test & Set instruction.

That is, when accessing the common memory device M, a test and set (Test&Set) instruction is issued before the access is made.

When accessing from CPUO, first read the contents of the usage display area of the corresponding address using the test and set command, and after confirming that it is not being used by CPU1,
This involves accessing the storage area and canceling the right to use it after the access is completed.

That is, in the test-and-set instruction, information is read and written at the same time in one memory cycle, so the display of usage rights is not destroyed.

Specifically, the problem with 1:) is as follows.

That is, when the low level processing LLP accesses the common resource COM RSC or queue Queue in the memory device M that may be accessed from different levels within the same CPU, the partner control device CPUO or CP
In addition to the collision caused by simultaneous access with the low level LL of U1, there is also interference with the high level of the local control device.

In other words, if there is a storage area that is simultaneously referenced by both the high level processing HLP program and the low level processing LLP program, while the low level reads information first and performs processing such as addition, Clock interrupt CLOCK/INRP occurs and high level processing HL
After transitioning to P, reading the information in the corresponding area, performing processing such as subtraction, and writing the result, if the interrupt ends and the process returns to low level processing LIP, processing will continue from the point of interruption. If the process is restarted, the result of the previous process will be written to the corresponding area, and the information will be destroyed.

In order to prevent such interference between levels, prevention processing has heretofore been taken in which clock interrupts are inhibited only for short steps.

Of course, it is also possible to prevent inter-level interference by test and set in connection with ]), but this
This is not practical because the interference prevention period may become unnecessarily long or deadlock may occur between levels.

As described above, conventionally, in a multi-processing system, a common memory device M is used in a low-level processing LLP.
When accessing the
It was necessary to perform both instruction and clock interrupt disabling processing.

In the low-level processing LLP, first, clock interrupts are disabled and the mask flip-flop is set, and then a test and set is performed.
t) Issue an instruction, and if it is not busy at that time, access the common memory, read the data, process it, write it, clear the test and set, and release the clock interrupt prohibition. Let's do it.

To clear the test and set, simply write an empty pattern to the corresponding address in the memory, and to cancel the interrupt prohibition, simply reset the mask flip-flop.

However, increasing the number of instruction steps like this requires
This has disadvantages of increasing overhead time and complicating the program.

The present invention provides a means to overcome the above-mentioned conventional drawbacks, and its purpose is to provide an interference control command scheme for a multi-processing system that simplifies programming and reduces overhead time. There is a particular thing.

The above object is to provide a special instruction combining test-and-set function and clock interrupt disable function in a multi-processing system including a plurality of control devices and a commonly accessible memory device according to the present invention. By setting in the instruction register, interference caused by simultaneous access from two or more control devices and interference caused by access from high level and low level within each control device to the corresponding address of the memory device can be prevented. This is achieved by simultaneously preventing

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a block diagram of a control command system showing one embodiment of the present invention.

In the figure, IR is an instruction register, ODR is an instruction section, and A
DR is the address part, ODR-TREE is the instruction expansion circuit (
decoder), ARU is an arithmetic circuit, MEM is a common memory device, and Mask F/F is a mask flip-flop.

In the present invention, test and set (Tes
A special instruction A that combines the functions of the t&Set) instruction and the clock interrupt disable instruction is created as an instruction for interference control, and is stored in the program memory.

Note that the special command A is an interference control command in low-level processing, and is unnecessary for high-level processing.

Therefore, in high-level processing, there is no need to disable interrupts, so the conventional Test & Set instruction can be used as is.

In addition, the test flag is reset (test f
lag reset) only writes an empty pattern to the corresponding address? Although this can be executed with a single store instruction, it is also possible to provide a special instruction C that combines this with canceling interrupt inhibition.

FIG. 5 is a flow chart of the interference control command execution operation in FIG. 4.

．． The operations shown in FIGS. 2 and 4 will be explained below with reference to FIG. 5.

When a special instruction A that combines the functions of a test-and-set instruction and a clock interrupt disable instruction is read from the program memory and set in the instruction register IR shown in FIG. -TR. It is decoded by EE and determined to be special instruction A.

Since control circuits for both functions are connected to the leg corresponding to the special command A of the expansion circuit ODFt-TFtEE, the test-and-set command sequence control circuit and the mask flip-flop Mas for disabling clock interrupts are connected to the leg corresponding to the special command A of the expansion circuit ODFt-TFtEE.
k-F/F are activated at the same time.

As shown in the flow chart of FIG. 5, when the special instruction A is first determined, the arithmetic circuit AR determines which address should be read in order to execute the test and set.
After calculating in U, the address and test
The AND set (T&S) is specified, and the mask flip-flop Mask F/F is set to disable clock interrupts.

The read result from the memory is set in a register, and condition codes C and C are set accordingly.

In the memory, an in-use display, for example, all 1, is automatically written in the in-use display area.

High-level processing HLP is performed by issuing an interrupt at regular intervals (for example, 4 ms) from a clock counter located inside or outside the control units CPUO and CPU1, so if a mask is set for the source of the clock interrupt, ,．． After that period, no interrupts can be made.

When processing including writing to the relevant memory is completed, test and. This can be done at the same time using a special instruction C that combines the set bit clearing function and the clock interrupt disable canceling function, or it can be used to reset the test flag and reset the mask flip-flop MaskF/F separately. It can also be done by command.

As described above, the present invention provides a method for storing one special instruction in an instruction register to prevent collisions caused by simultaneous accesses to a memory device from multiple control devices and interference caused by accesses from different levels within the control device. This function sets the mask flip-flop to disable clock interrupts and decodes it to operate the test and set function, reducing the number of processing steps for access instructions to the memory device. This has the advantage of simplifying the program and reducing overhead time.

The invention can be applied not only to the electronic exchange control device of the above-described embodiment but also to other multi-processing systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a multi-processing type electronic exchange, FIG. 2 is a detailed block diagram of FIG. 1, and FIG. 3 is a flow chart when accessing the common memory device in FIG. FIG. 4 is a block diagram of a control command method showing an embodiment of the present invention, and FIG. 5 is a flow chart of the execution operation of the interference control command in FIG. In the figure, IR is an instruction register, ODR is an instruction section, and A
DR is the address section, ODR TREE is the instruction expansion circuit,
AFtU is an arithmetic circuit, MEM is a common memory device R (M)
, Mask F/F is mask flip-flop, S
P is the communication path system (target to be controlled), HLP and LLP are high
level processing and low level processing.

Claims (1)

[Claims] 1. In a multi-processing system that includes multiple control devices and a memory device that can be accessed in common, the test and set function and mask flip
It has a clock interrupt prohibition function consisting of a flop, and prevents collisions caused by simultaneous accesses to the memory device from multiple control devices and accesses from different levels within the control device. A special instruction to prevent interference is set in the instruction register, and by decoding the special instruction, the test and set function is activated, and the mask flip-flop is set to disable clock interrupts. An interference control command method characterized by: