JP3381080B2 - Exclusive control method that can interrupt processing - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing unit for a processing unit.
To divide and execute the process (task) to be executed by the server
Data that each process (task) accesses in parallel
Exclusive control method for performing data consistency assurance control
Things. 2. Description of the Related Art A plurality of processing units (hereinafter referred to as processing units)
Task is called alternately)
In the method, common data that each task accesses in common
When reading and rewriting data,
Inconsistencies may occur between For example, task A
The value stored by task B at address X in the main memory
Consider adding 10 and 100 to "x" respectively.
You. Originally, the processing of task A and task B
Then, the value of the address X becomes “x + 110”. Only
Then, after task A reads the value “x” of address X,
Before writing the value “x + 10” to the address X, the processing unit
When the task executed by the task switches to task B,
Task B reads the value “x” at address X, and task B
Rewrite address X to “x + 100”, and task A
When opened, the address X is rewritten to "x + 10". This
In the past, to avoid inconsistencies like
Acquire access rights to common data before accessing
Release access right after access to common data
I am trying to do it. In this case, the access right is
Provided for each task, and access to only one task at a time.
Access rights. As described above, in multitasking,
In exclusive control, before accessing common data,
Access to common data from other tasks.
Access and release access right after the end of access
Exclusive control, or while accessing common data
A system that suppresses switching of tasks that are being executed by processing units
I need you. Generally, in exclusive control, target data
Data is managed in the following three states. Read lock status: read by one or more tasks
Is in progress and suppresses rewrite access from other tasks
State that needs to be. Write locked state: rewriting by one task
Yes, read access and rewrite from other tasks
A state in which access must be suppressed. Unlocked: All accesses from any task
State where is possible. [0004] In the above method, the task
Access rights for common data accessed in parallel
Therefore, the following disadvantages arise. (1) All common data accessed by each task in parallel
To secure / release access right before and after access to
It becomes complicated because it is necessary to incorporate the logic in advance. (2) Despite the low probability of contradictions,
Access rights before and after accessing common data
Processing to perform / release processing is required.
The effective processing capacity of the knit decreases. (3) Conventionally, parallel processing is performed by newly added processing.
Unaccessed data is accessed in parallel between multiple tasks.
If it becomes common data to be accessed,
Processing to secure / release access rights to the data
Need to be added. Conventionally, in order to solve the above problem, parallel
Do not strictly separate data that does not access the data from common data
To secure / release access rights to multiple common data
Secure / release access rights
A technique to reduce the number of times was adopted. But multiple common
Secure / release access rights to data collectively
And common data that has no access request
Unnecessary exclusive control is performed until the
Since the securing period becomes longer than necessary,
The probability that the execution of processing that can be arranged is hindered is increased
Disadvantages arise. [0006] In addition, the control for suppressing the task switching is performed.
Perform tasks that frequently access common data
Is prioritized (depending on the task, it is switched from start to end)
Switching will not be performed)
Task allocation with a limited number of processing units.
And assign the processing unit to a higher priority task.
The freedom to use
Processing time by switching disks
Control of multitasking system to achieve uniform
There is a disadvantage that the [0007] Further, the inventors of the present invention have previously filed a special application.
No. 4-287245 "In a multiprocessor system
Exclusion control method required between multiple processing units
(1) through (3) above
The point is solved, but the processing in each processing unit
(Task) interruption is not allowed and exclusive control between tasks
It does not make it possible. The object of the present invention is to
It is an object of the present invention to provide an exclusive control method that solves the disadvantage of the above. [0008] The present invention solves the above disadvantages.
To erase, the task is accessed first,
Process blocks containing data to be accessed by the end
Managed as an intermediate state in the cache memory in the logical unit
And the status of the access source for the block
Manages the identification information of the
If an access that requires suppression of the lock occurs,
The task that is running or the task that locked the block
Control by suspending or invalidating (stopping)
Is what you do. According to the present invention, by providing the above means,
When tasks are executed in a divided manner, each task is
Secure / release processing of access right to common data to be accessed
In the processing unit due to an increase in the amount of processing to perform
And no new processing performance.
Data that became common data by adding disks
Change the conventional processing to perform exclusive control on
Without the need for control to suppress task switching.
You. FIG. 1 shows information for explaining an embodiment of the present invention.
It is a block diagram of a processing apparatus. In FIG. 1, 1 to 3
A processing unit, 4 is a system bus, 5 is a main memory,
6 is a bus master controller, 10, 20, and 30 are
Processors 11, 21 and 31 are cache memos
, 41 is an address bus, 42 is a data bus, 43 is a
Read / write bus, 44 is an access type bus, and 45 is
Send response bus, 46 is inconsistent response bus, 100, 200 and
And 300 are processor buses, 1001, 2001 and
Reference numeral 3001 denotes a task identification information bus. The task identification information buses 1001, 2001 and
And 3001 are composed of a plurality of signal lines, and each signal line has
Tasks executed in parallel in the processing unit will not overlap
Assigned in advance, and
Tasks are allocated when accessing cache memory
The value "1" is output only to the signal line
Output the value "0". The main memory 5 is divided into the same size,
Block between the cache memories 11, 21 and 31.
Transfers memory contents on a per-block basis. Cache memory
As shown in FIG.
.., Entry #e.
Has been established. FIG. 2 shows only the internal configuration of entry # 1.
Although shown in detail, other entries # 2,..., #E
Also have the same configuration. Entry # 1, ...
Entry #e (detailed internal configuration is omitted)
Address information section 211 for storing the address of the
. 2e1 (not shown), a block for storing a block
2e2 (not shown), each process
Unit task identification buses 1001, 2001, 300
It has the same number of bits as one signal line and is accessed.
Bit corresponding to the signal line from which the task output value "1"
Task identification information section 213 for setting a value “1” to
-2e3 (not shown), execution terminated in processing unit
(A confirmation instruction was output)
State information storing an intermediate state (value “1”) indicating
2e4 (not shown) in section 214,.
The stored contents are valid (value "1") or invalid (value
Valid portion 215,..., 2 indicating whether “0”)
e5 (not shown), the contents of the main memory 5 are not rewritten
Only the contents of the block data section of the cache memory
Modifying unit 21 indicating that replacement has been performed (value “1”)
6,..., 2e6 (not shown) of each address information part
A comparator 217 for comparing the content with the content of the signal line 2A;
..2e7 (not shown), contents of each task identification information section
, 218,.
2e8 (not shown), comparators 217,..., 2e7
(Not shown), a match signal is output from the
When the content is “1 (valid)”, the signal line 21B,.
-An amplifier that outputs an "ON" signal to 2 eB (not shown)
2e9 (not shown)
Is done. Note that the task identification information section, intermediate state information section,
The lid section and the modify section show the state of the block.
These are called a block status information part. Determination is instructed from determination instruction signal 2E.
, And gate 21E,..., 2eE (not shown)
Is the contents of the task identification information section and the
The result of comparison with the task identification information and the modification part
Input, and the AND output outputs the value of the intermediate state part.
It is set to “0”. Invalidation is specified via the invalidation instruction signal 2D.
As shown, AND gates 21D,..., 2eD (FIG.
(Not shown) indicates the contents of the task identification information section and the
Signal of the comparison result with the task identification information of the
Enter the contents and the contents of the modify section, and
The valid part is set to “0 (invalid)” by the output. Here, a finger is designated by the address a of the main memory 5.
The block containing the data to be defined is defined as Ba, and the processor
Implementation of the invention when 10 accesses block Ba
The operation of the example will be described with reference to FIGS. No Figure 3
FIG. 5 shows a cache when accessed from its own processor.
Access to the processing in the flash memory from the processor 10
The processing of the cache memory 11 when the
This is a flowchart that explains each part of the process.
Can be executed simultaneously and in parallel by using a circuit.
it can. Referring to FIG. 3, a processor 10
The data specified by the address “a” via the
Request to read or rewrite data (step
51), the processor 1 is connected to the task identification information bus 1001.
Task identification information assigned in advance to the task being executed at 0
Output information. Cache memory 11 of processing unit 1
Represents the address information a output from the processor 10 on a signal line.
2A, input the task identification information to the signal line 2B (step
52), in step 53, the cache memory 1
1 is designated by the address information a output from the processor 10.
Block Ba containing the data to be stored (signal line 21B,
... When the output of 2 eB (not shown) is turned on
Is determined) or not. Cash memo
When the block Ba does not exist in the memory 11, the following (A)
The block Ba exists in the cache memory 11
To do so, the following process (b) is performed. (A) Block B in the cache memory 11
a does not exist (signal lines 21B,..., 2 eB (not shown).
) Is not `` ON ''.
Case: The cache memory 11 stores the block Ba.
Secure the entry by the following method. Cache memory 11
Indicates that the valid part is “0 (invalid)” or the intermediate state part 21
4,..., 2e4 (not shown) are “0 (determined state)”
From an entry that is a predetermined procedure (for example,
LRU algorithm to select the least recently used
Entry, etc.)
E, and the entry E is the address information section 2 × 1,
Data section 2x2, task identification information section 2x3, intermediate status
State information part 2x4, valid part 2x5, modify part 2
x6, ...) is selected.
Step 54). In the next step 55, the entry E
The module part 2x5 is "1 (valid)" and the modifier part 2x
6 is "1 (Ba of the block data portion and B of the main memory)
(a does not match). " check
As a result, YES, that is, the valid part 2x of the entry E
5 is “1 (valid)” and the modifying part 2 × 6 is “1 (valid)”.
(Ba in the block data section is inconsistent with Ba in the main memory.
"), The cache memory 11 is connected to the signal line 101.
Requests the use of the system bus 4 via the bus master controller.
Inform roller 6. The bus master controller 6
One cash memo according to the prescribed procedure
Only the system bus 4 is permitted to use the system bus 4. Signal line 1
02, the use permission of the system bus 4 is
When given to memory 11, address on address bus 41
Output the address stored in the address information section 2x1,
A rewrite instruction is output to the read / write bus 43, and the data is
It is stored in the tab data 42 in the block data section 2 × 2.
Output the block. The main memory 5 has an address bus 4
In the block specified by the address output to 1
Rewrite the contents to the contents output to the data bus 42
(Step 56). If the result of the check in step 55 is NO,
That is, the valid part 2 × 5 of the entry E is “1 (valid)”
And the modifying unit 2 × 6 is “1 (the block data
Ba and Ba in the main memory do not match)
Or when the process of step 56 is completed
The cache memory 11 stores the block Ba in the entry E
In the following way. The cache memory 11 has a signal
A request to use the system bus 4 is sent to the bus
To the controller 6. Bus master controller
6 is one cache according to a predetermined procedure.
The use permission of the system bus 4 is given only to the flash memory.
The permission to use the system bus 4 is received via the signal line 102.
When given to the flash memory 11, the address bus 41
The address a is output to the top and read to the read / write bus 43.
And outputs a read instruction to the access type bus 44.
Access type (read or rewrite)
(Step 57). At this time, the cache memory of another processor is
The operation of the memories 21 and 31 is shown in FIG. FIG.
Is the access that other processing units output to the system bus 4.
FIG. 7 is a diagram for explaining a process of checking
Each part of the processing is simultaneously paralleled by using logic circuits
Can be implemented When there is one processing unit
Does not require this processing. In FIG. 7, the cache
The memories 21 and 31 are output to the address bus 41
Enter the address a (step 82)
The block Ba including the data of a is stored therein.
Entry (let this entry be e, entry e is the address
Information section 2y1, block data section 2y2, task identification
Information part 2y3, intermediate state information part 2y4, valid part 2y
5, the modification unit 2y6,...
Exist) and the valid part 2y5 of the entry e is
It is checked whether it is "1" (step 83). As a result of the check in step 83, N
If it is O, the following process (a) is performed, and if YES,
For example, in step 84, the entry e is
Check whether the value of 2y4 is "1 (intermediate state)"
As a result, if YES, the following (A-b)
If so, the following process (a-c) is performed. (A) Cache memories 21 and 3
When 1 does not store a valid block Ba inside:
The cache memories 21 and 31 end without doing anything.
The main memory 5 outputs the block Ba to the data bus 42
To the cache memory 11 via the transfer response bus 45.
Notify that a response has been output (not shown). (Eb) Cache memory 21 or 3
An entry e in which 1 stores the block Ba exists, and
Intermediate state information section 2y of the entry storing block Ba
When 4 is "1 (intermediate state)": Store block Ba
The modifying section 2y6 of the entry to be entered is "1 (block
(Ba in the data section does not match Ba in the main memory.) "
85) or the cache memory 11 has the address type
If the rewrite has been output to the bus 44 (step 8
6), via the contradiction response bus 46 to the cache memory 11
Is notified that a contradiction has occurred (step 87). At this time, the cache memory 11
Conflict response bar from unit 2 or 3 cache memory
Notification that the contradiction has occurred via the server 46 (FIG. 4).
Step 58) and the inconsistency resolution processing (step
Step 64) is performed. Main memory 5 is a cache memo
The conflict has occurred in the conflict response bus 46 for the resource 21 or 31.
If no signal to the effect is output, block Ba is connected to data bus 4
2 and a cache memo via the transfer response bus 45.
Notify the client 11 that the response has been output (not shown). (A-c) Cache memory 21 or 3
An entry e in which 1 stores the block Ba exists, and
The intermediate state part of the entry storing the block Ba is “0”.
(Determined state) ": an entry for storing the block Ba
The modification part 2y6 of the file is "1 (the block data part
Ba does not match Ba in the main memory).
Check (step 88 in FIG. 7). In step 88
If the result of the check is YES, the process proceeds to step 89.
If NO, the process proceeds to step 91. If yes
Means that the latest content of the block Ba is the cache memory 21
Or 31 (hereinafter referred to as cache memory 21).
It is assumed that there is a cache memory 2)
1 outputs the block Ba to the data bus 42,
A response is output to the cache memory 11 via the bus 45
Is notified (step 89), and the
"0 (Ba of the block data portion and Ba of the main memory are
Match) "(step 90). At this time,
The memory 5 is output from the cache memory 21 to the data bus 42
Received block Ba together with the cache memory 11
The contents stored in the main memory 5 to the latest contents
(Not shown). The processing of steps 89 and 90
End or as a result of the check in step 88, N
O, that is, the modality of the entry storing the block Ba
The file part is "0 (Ba of the block data part and the main memo)
If Ba of the data matches), the following processing is performed. Cap
Memory 11 is rewritten to access type bus 44
Is output (step 91), the block Ba
The valid part 2y5 of the entry to be stored is set to "0 (invalid)"
To invalidate the entry (step 92).
Complete. This allows the blocks from processor 10
If the access to Ba is rewriting,
The content no longer exists in other cache memory
Data consistency. Note that the cache memory
11 outputs “rewrite” to the access type bus 44
If not (step 91), the process ends. Returning to FIG. 4, the description will be continued. Cash
As described above, the memory 11 is a key for another processing unit.
Cache memory (21, 31) or main memory 5
The block requested by the block transfer response bus 45.
Data Ba is output on the data bus 42,
The block Ba output on the data bus 42 to the entry E
Stored in the block data section 2x2 of the
Is stored in the address information section 2x1, and the validity of the entry E is
2x5 is set to "1 (valid)", and the intermediate state unit 2x4 is set to "1".
(Intermediate state) ", the task identification information section 2x3 identifies the task
Store the value output to the bus 1001 (step
59). In step 60, the processor 10
The access type for these blocks Ba is rewritten or read
Judgment is made. Block B from processor 10
If the access type for a is rewritten, entry E
Of the modified part 2 × 6 of “1 (B of the block data part)
a and Ba in the main memory do not match).
Instructed by the processor 10 via the processor bus 100
Stored in the block data section 2x2 of entry E
Data specified by the address a of the block Ba
The data is rewritten (step 61). From processor 10
The access type for the block Ba is read
If it is stored in the block data section 2x2 of the entry E
The data specified by the address a of the block Ba
The data is transferred to the processor 10 (step 62). Cash
The memory 11 uses the system bus 4 via the signal line 101.
Is notified to the bus master controller 6
(Step 63). (B) An effective end for storing the block Ba
The bird E exists in the cache memory 11 (signal line 21
B,..., 2 eB (not shown) output is “ON”
(See FIG. 5): In this case,
The theory is divided into a fixed state (b-a) and an intermediate state (b).
(Step 65). (B-a) The intermediate state part 2 × 4 of the entry E is “0 (determined)
State) ": Modification of entry E in step 66
The main part is "1 (Ba of the block data part and the main memory)
Are not matched). " as a result,
NO, that is, when the modify part is "0 (block data
Section Ba and the main memory Ba match) "
The intermediate state part of the bird E is set to “1 (intermediate state)” (step
67), the task identification information section 2 × 3 has the task identification bus 1
001 is set to the task identification information output to
68), the cache memory 11 is connected via the signal line 101.
Request to use the system bus 4 by the bus master controller
Inform La6. The bus master controller 6 has a predetermined
System to only one cache memory according to the
A request to use the bus 4 is given. Via the signal line 102.
The permission to use the stem bus 4 is given to the cache memory 11.
Output address a on address bus 41
And outputs a read instruction to the read / write bus 43,
Processor 10 outputs to access type bus 44
The access type is output (step 76 in FIG. 6).
Answer Unless an output indicating that a contradiction has occurred is made on the bus 46
(Step 77), the cache memory 11
A signal to the effect that a response has been output is output to the
Stop data transfer from in-memory 5 (step
78; Block Ba already exists in cache memory 11
Need to read the block from the main memory 5
No). The access type output by the processor 10 is
In the case of "reading", the modification part 2 of the entry E
x6 is set to "0 (Ba of the block data portion and
Ba matches) ", the block data portion 2x of the entry E
2 designated by the address a of the block Ba stored in
Is transferred to the processor 10 (step of FIG. 4).
62). For the block Ba from the processor 10
If the access type is “rewrite”, the entry E
Defining section 2x6 is changed to "1 (Ba of block data section)
(Ba in main memory does not match.) "
Commanded by the processor 10 via the processor bus 100
The contents are stored in the block data section 2x2 of the entry E.
The data specified by the address a of the block Ba
Rewrite (step 61) via the processor bus 100
To notify the processor that access has been completed,
That the use of the system bus 4 via the
Is notified to the bus master controller 6 (step 6).
3). As a result of the check in step 66 in FIG.
ES, that is, when the modification part of the entry E is “1 (B
Ba in the lock data section is inconsistent with Ba in the main memory.
"), The cache memory 11 is connected to the signal line 101.
Requests the use of the system bus 4 via the bus master controller.
Inform roller 6. The bus master controller 6
According to the prescribed procedure.
Only the use permission of the system bus 4 is given. Signal line 102
Permission to use the system bus 4 via the cache memory 1
1, the address a on the address bus 41
And issues a rewrite instruction to the read / write bus 43.
To the data bus 42, the block data portion of the entry E.
The block Ba stored in 2 × 2 is output and
The block Ba of the memory 5 is output to the data bus 42.
The content is updated with the contents (step 69). The intermediate state part 2 × 4 of the entry E is changed to “1 (medium
In the task identification information section 2x3 of the entry E
The task identification output to the task identification information bus 1001
Access type output by the processor 10 by setting separate information
If another (step 70) is "read", enter
The modifying section 2 × 6 of E is set to “0 (block data section).
(Ba coincides with Ba in the main memory). "
71), stored in the block data section 2 × 2 of the entry E
Data specified by the address a of the block Ba
Is transferred to the processor 10 (step 62 in FIG. 4),
Proceed to step 63. Block B from processor 10
If the access type (step 70) for “a” is “rewrite
If "E", the modifying section 2x6 of the entry E
"1 (Ba of the block data part and Ba of the main memory are
And the processor 10
The entry E is blocked with the contents specified through the subbass 100.
Of the block Ba stored in the lock data section 2x2
Rewrite the data specified by address a (see FIG.
Step 61); proceed to Step 63. In step 63
The cache memory 11 is connected via the processor bus 100
Notifying the processor 10 that the access has been completed,
That the use of the system bus 4 via the
Is notified to the bus master controller 6. (B-b) Intermediate state part 2 × 4 of entry E
Is “1 (intermediate state)” (see FIG. 6): Step 7
3, the value of the task identification information section 2 × 3 of the entry E is the task
Matches with the value output to the identification bus 1001 (signal line 2
Check if the output of xC is "ON"). The result
As a result, NO, that is, the task identification information section 2x of the entry E
3 is the value output to the task identification bus 1001 and
When there is no match (output of signal line 2xC is "OFF"),
The access type for the block Ba from the processor 10 is
"Rewrite" (step 79) or processor 10
The access type for block Ba from
And the modifying section 2x6 of the entry E is "1 (B
Ba in the lock data section is inconsistent with Ba in the main memory.
If (")" (step 80), the cache memory 1
1 performs the inconsistency resolution processing shown in (c) below, and
The processing being executed in 10 is interrupted or invalidated (aborted),
Tasks selected for execution in a predetermined way
The task is performed. As a result of the check in step 73, YES
That is, the value of the task identification information section 2x3 of the entry E is
Match the value output to the disk identification bus 1001 (signal
When the output of line 2xC is "on"), the processor
The access type for the block Ba from 10 is “write”
Change (step 74) and modify entry E
Section 2x6 is "0 (the main memory of the block data section)
If Ba matches) (step 75), the cache
The memory 11 uses the system bus 4 via the signal line 101.
Request to the bus master controller 6. Basma
The star controller 6 performs 1 according to a predetermined procedure.
Permission to use system bus 4 for only one cache memory
give. Use of system bus 4 via signal line 102
When permission is given to the cache memory 11, the address
The address a is output on the bus 41 and the read / write
The read instruction is output to the access 43
Access type “rewrite” output by the processor 10
Is output (step 76). The cache memories 21 and 31 store
Input the address a output to the
A block Ba containing data of the dress a is stored therein.
The flow chart shown in FIG.
Inconsistent when the state of step 87 is reached
A notification that an inconsistency has occurred is output via the response bus 46.
You. The cache memory 11 stores the processing unit 2 or 3
Inconsistent from the cache memory via the inconsistency response bus 46
Is notified (step 77) that the
The inconsistency resolution processing shown in (c) is performed. An inconsistency has occurred via the inconsistency response bus 46.
If there is no notification to that effect, the cache memory 11
Output a signal to the effect that a response has been output to the transfer response bus 45
Then, the data transfer from the main memory 5 is stopped (step
Step 78: Block Ba is already in cache memory 11
Reads the block from the main memory 5 because it exists
(It is not necessary.) Returning to FIG. 4, in this case, rewriting
From step 60 to step 61, entry E
Of the modified part 2 × 6 of “1 (B of the block data part)
a and Ba of the main memory do not match) "
Contents instructed from the processor 10 via the processor bus 100
Is stored in the block data section 2x2 of the entry E.
The data specified by the address a of the block Ba
In other words, the access via the processor bus 100 is completed.
Is notified to the processor 10 via the signal line 101.
That the use of system bus 4 has been terminated
The controller 6 is notified (step 63). The value of the task identification information section 2 × 3 of the entry E
Does not match the value output to the task identification bus 1001
When the output of the signal line 2 × C is “OFF”, the processor
10 to the block Ba from FIG.
Step 79) is “read” and entry E mod
The phi part 2x6 is "0 (Ba of the block data part and
(Ba of the memory matches) "(step 80),
The value of the task identification information section 2x3 in the task identification information section 2x3
And the value output to the task identification information bus 1001
The logical sum is set (Step 81: For example, the task identification information
The value “01101010” is set in the
The value “00000100” is stored in the task identification bus 1001.
Is output in the task identification information section 2x3.
“01101110” is set), and the data is read.
From step 60 in FIG.
Of the block Ba stored in the block data section 2x2
Transfer the data specified by the
(Step 62), access via the processor bus 100
The completion of the access is notified to the processor 10 by a signal line 101.
That the use of the system bus 4 has been terminated via
Notify the star controller 6 (step 63). For the block Ba from the processor 10,
Access type is “rewrite” or the model of entry E
The verifying section 2x6 indicates “1 (Ba and block data
(Ba of in-memory does not match.) "
The memory 11 performs the inconsistency resolution processing shown in (c) below, and
Processing being executed by the processor 10 is interrupted or invalidated (canceled)
Selected from tasks waiting to be executed in a predetermined manner
The specified task is executed. (C) Inconsistent response bus from another processing unit
46 when a notification that a contradiction has occurred is received via
Or an inconsistency has occurred for access from the processor 10.
Case: the cache memory 11 is
Cancels the running task and rewrites the running task.
The state before the task started executing the contents of the in-memory
In this case, the invalidation instruction signal 2C in FIG.
Then, the value “1” is stored in the intermediate state information section of the cache memory 11.
(Intermediate state) is set and the modify information section
Of all entries for which the value “1” is set
The data information part is set to “0 (invalid)”, and then the
Between the states of the cache memory 2
Intermediate state set by the task that performed the access
Cancel. As a result, the processor 10 is rewritten.
The contents of the block that was interrupted when the execution of the interrupted task started
It becomes the contents of the point and the read lock state (intermediate state,
The state where the modifying section is "0") is also released. Ki
The cache memory 11 is a task executed by the processor 10.
And via the processor bus 100
The processor 10 is notified that inconsistency has occurred. Professional
The task being executed by the processor 10 is invalidated (aborted), and the
Tasks selected in a predetermined manner from tasks waiting for a line
The task is executed. In the above, the access source when inconsistency occurs
Described how to abort a running task.
Interrupt the task in progress and a predetermined time has elapsed
There is also a method to resume from the interruption point later. All accesses from the cache memory 11
Other processing units notify the
For all accesses from processor 10
No inconsistency occurs, and the processing being executed by the processor 10 is normal
At the end of the process,
The determination instruction signal 2D of FIG.
The value “1 (intermediate state)” is stored in the intermediate state information section of the memory 11.
Is set and the value "1" is set in the modify information section.
The intermediate state information section of all entries that have been
Fixed state), and then the intermediate state solution shown in (d) below.
From the cache memory 2
Cancel the intermediate state set by the disk. This
Therefore, it is confirmed that the task executed by the processor 10 is rewritten.
And the task executed by the processor 10 has accessed
All blocks are processed from other processors
Reading and rewriting become possible. (D) Intermediate state release processing Instruction of processor 10 or inconsistency from processor 10
When the access is performed, the cache memory 11
Is the task identification information of the task that releases the intermediate state (this
Information is provided via a task identification information bus 1001.
The following processing. Cash memo
The lock 11 performs the lock release process shown in FIG. here,
FIG. 8 shows a key in response to an intermediate state release instruction from the processing unit.
FIG. 4 is a diagram for explaining processing in the cache memory.
By using logic circuits, each part of this process can be performed simultaneously.
Can be performed in parallel. Cache memory 11
A counter 25 for sequentially specifying entries in the
Then, the task identification information is input to the signal line 2B. counter
Set the value of 25 to the initial value (here, “1”)
(Step 93), the counter value is stored in the cache memory 2
Until the total number of entries e is reached (this is
Judge), every time the value of the counter 25 is incremented by one,
Repeat the process. Here, the value of the counter 25 is "c"
The entry specified is entry Ec, and entry Ec is
Address information section 2c1, block data section 2c2, task
.. Are assumed to be composed of the identification information sections 2c3,. When the value of the valid part 2c5 of the entry Ec is
"0 (invalid)" (step 94) or intermediate state information section
When the value of 2c4 is “0 (determined state)” (step 95)
In this case, the value of the counter 25 is incremented by 1 (step 100).
The value of the valid part 2c5 of the entry Ec is "1 (valid)"
(Step 94) When the value of the intermediate state information section 2c4 is “1”
(Intermediate state) ”(step 95), the task identification information
The value and the intermediate state of the task identification information section 2x3 are
Logic of the task identification information to be released with the value obtained by inverting 0/1
The product (for example, the value “01101” is stored in the task identification information unit 2 × 3
110 "is set, and the
If the disk identification information is “0000100100”, the task
The value “01101010” is set in the ID information section 2x3
Is done. The fact that there is one bit in this means that
(Meaning that there is a task that does not release the status)
(Step 96), and as a result, the task identification information section 2x
All three bits are “0” (ie, “000000”
00 ”), the value is stored in the intermediate state information section 2 × 4.
"0 (determined state)" is set (step 98),
The value of the data 25 is incremented by 1 (step 99). Step 99
, The value of the counter 25 is equal to the number of entries e.
If not, the process returns to step 94, and the number of entries becomes e.
Then, the intermediate state release processing ends. Thus, the processing unit is divided and executed.
Tasks and each processing unit are activated in parallel.
For securing / releasing access rights to the block to be accessed
Need to be embedded in the processing executed by each processor in advance.
Tasks that are executed separately by the processing unit
And multiple processors in parallel on the same block
Exclusive control is performed to guarantee consistency when accessing
It is. As described above, the present invention can be applied to various processes.
Tasks that are divided and executed by the
Access rights when accessing common data
Reserve / release processing is reserved for processing executed by each processing unit.
Installation is no longer necessary, ensuring access rights and
There is no processing unit overhead due to release, and new
Data that became common data by adding processing to
The conventional processing to perform exclusive control on the data
Effective performance in the processing unit because it is not necessary
Process to be executed by the processing unit
To greatly improve the productivity of program descriptions
Becomes possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram for explaining a configuration diagram of an entry of a cache memory according to the present invention; FIG. 3 is a flowchart (part 1) for explaining the operation of the cache memory in response to access from the processor according to the present invention; FIG. 4 is a flowchart (part 2) for explaining the operation of the cache memory in response to access from the processor according to the present invention; FIG. 5 is a flowchart (part 3) for explaining the operation of the cache memory in response to access from the processor according to the present invention; FIG. 6 is a flowchart (part 4) for explaining the operation of the cache memory in response to access from the processor according to the present invention; FIG. 7 is a flowchart for checking access by another processing unit of the present invention. FIG. 8 is a flowchart illustrating a process of canceling an intermediate state according to the present invention. DESCRIPTION OF SYMBOLS 1, 2, and 3 Processing unit 4 System bus 5 Main memory 6 Bus master controllers 10, 20, and 30 Processors 11, 21, and 31 Cache memory 41 Address bus 42 Data bus 43 Read / write bus 44 Access type bus 45 Transfer response bus 46 Conflict response buses 100, 200 and 300 Processor buses 101, 102, 201, 202, 301 and 302
Signal lines 1001, 2001 and 3001 Task identification information bus

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/08 G06F 9/46 G06F 12/00 G06F 15/16-15/177

Claims (1)

(57) [Claim 1] Information comprising one or more processing units, a main memory and a system bus, wherein the processing units and the main memory are mutually connected by the system bus. In the processing device, the address space of the main memory is divided into a plurality of blocks, the processing unit includes a processor and a cache memory, and the cache memory includes a plurality of entries each including a block data section and a block state information section. The processor has means for outputting task identification information, which is information for identifying a process (task) being executed by the processor, when accessing the block, and the cache memory is used for accessing the block from the processor. On the other hand, the corresponding block is stored in the block data section. Means for setting the information indicating the intermediate state, the state according to the access from the processor, and the task identification information in the block state information section of the entry to be stored in the block state information section of the entry according to an instruction from the processor. Means for canceling the intermediate state being set, and when the processor accesses the block, information indicating that the block specified by the address is stored in the block state information portion of the entry indicating the intermediate state. Is set, and when the state and task identification information set in the block state information section of the entry and the access type and task identification information output by the processor are a predetermined combination, an access is performed. Notifies the processor that an intermediate block has been accessed Exclusive control method capable of interruption of the process according to claim Rukoto.