JPH0635866A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To provide a multiprocessor system for which the overhead of processing units for securing and releasing access rights is not generated and the instantaneous processing performance of the processing units is improved. CONSTITUTION:This multiprocessor system is constituted of the processing units 1, 2 and 3, a system bus 4, a main memory 5 and a bus master controller 6. When the cashe memory of a certain processing unit outputs an address and the kind of the access to the system bus 4, the cashe memories of the other processing units inform e-4 the processing unit as the address output source of that a block to which exclusive control information is set is made access when the exclusive control information is set at the lock state part of an entry where the block specified by the address is stored and further, the exclusive control information and the kind of the access outputted to the system bus 4 by the processing unit are predetermined combination.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a plurality of processing units, a main memory, and a system bus connecting the plurality of processing units and the main memory. The processing unit comprises a processor and a cache memory. The address space is divided into a plurality of blocks, and the cache memory relates to a multiprocessor system including a plurality of entries.

[0002]

2. Description of the Related Art Conventionally, in this type of multiprocessor system, when each processing unit reads and rewrites common data, a contradiction may occur with another processing unit. For example, consider a case where the processing unit A and the processing unit B add 1 to the value “x” stored in the address X of the main memory. Originally, if the processes of the processing units A and B are performed without contradiction, the value of the address X becomes "x + 2". However, if the processing unit B reads the value "x" of the address X and then the value "x + 1" of the address X is written by the processing unit B, the processing unit B also reads the value "x" of the address X. Will be rewritten to "x + 1".

In order to prevent such a contradiction, an access right to the common data is acquired before accessing the common data, and if the access right is successfully acquired, the common data is accessed to access the common data. The access right is released after the access is completed. The access right is provided for each common data, and is controlled so that the access right is given to only one processor at the same time.

As described above, in the exclusive control in the multiprocessor system, the access right is acquired before accessing the common data, the access to the common data from other processing units is suppressed, and after the access is completed. Exclusive control to release the access right is required.

However, in the conventional method, each processing unit needs to perform processing for securing / releasing the access right for each common data accessed in parallel at the same time, which has a drawback that the processing amount for this purpose increases.

[0006]

Conventionally, in order to solve the above problem, the access right is secured / released collectively for a plurality of common data without strictly separating the data that is not accessed in parallel and the common data. Then, a method of reducing the number of times of securing / releasing the access right has been adopted.
However, if the access rights are collectively secured / released for a plurality of common data, unnecessary exclusive control is performed for the common data, and the access right securing period becomes long. There is a drawback that the probability that the execution of processing that can be performed in parallel in a unit is hindered increases.

An object of the present invention is to prevent an overhead of a processing unit for securing and releasing an access right,
It is an object of the present invention to provide a multiprocessor system in which the effective processing performance of a processing unit is improved.

[0008]

According to the multiprocessor system of the present invention, each entry of the cache memory has a block address, an address information section in which the block is stored, a block data section, and the block data. Lock state section in which exclusive control information for prohibiting reading or rewriting of existing data is set, and each processor sets exclusive control information in the lock state section of the entry in the cache memory of its own processing unit. And exclusive control information reset means for resetting exclusive control information, and when the cache memory of a certain processing unit outputs an address and an access type to the system bus, the cache memory of another processing unit is designated by the address. Lock state part of the entry in which the block is stored Exclusive control information has been set,
Furthermore, when the exclusive control information and the access type output to the system bus by the processing unit are a predetermined combination, it is determined by the address output source that the block in which the exclusive control information is set is accessed. Notify the unit.

[0009]

According to the present invention, when the process being executed in the processor accesses the common data, the information (address and access type) for accessing the data is locked together with the lock (replacement or read prohibition) of the data. Outputs exclusive control information to instruct, the cache memory manages the block containing the data as a locked state, and if an access to the block in the locked state occurs from another processing unit, the processing being executed in the other processing unit Alternatively, exclusive control information for the common data is provided by interrupting or invalidating (stopping) the process being executed in the own processing unit.

As a result, the effective processing performance of the processing units does not decrease due to an increase in the processing amount for securing / releasing the common data access right for each processing unit to access in parallel at the same time.

It should be noted that the cache memory that has output the address to the system bus has accessed the block in which the exclusive control information has been set for that address, not the processing unit that issued the address, but the processor of its own processing unit. Notifying the system reduces the amount of system bus hardware.

Further, a priority register for writing the processing priority is provided in the cache memory, and when the priority of the self processor is lower than the priority output to the system bus,
By stopping the process being executed by the own processor, the process with high priority is executed.

Further, when the cache memory does not require exclusive control over common data for the process being executed by the processor in the processing unit of the cache memory, exclusion of lock state parts of all entries in the cache memory is performed. By resetting the control information (to the unlocked state),
The access count from the processing unit for unlocking is deleted.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a multiprocessor system showing an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of entries in the cache memories 11, 21, 31.

The multiprocessor system of this embodiment is
The processing units 1, 2, and 3, the main memory 5, the bus master controller 6, and the system bus 4 (the address bus 4 that connects the processing units 1, 2, and 3 with the main memory 5).
1, a data bus 42, a read / write bus 43, an access type (read or rewrite) bus 44, a priority bus 45 that outputs a priority, a transfer response bus 46 that outputs a response, and a notification that an inconsistency has occurred (Consisting of an inconsistency response bus 47). Processing unit 1
Comprises a processor 10, a cache memory 11 and a processor bus 12, and signal lines 13 and 14 are connected between the bus master controller 6 and the cache memory 11. The processing unit 2 includes a processor 20, a cache memory 21, and a processor bus 22, and a signal line 2 is provided between the bus master controller 6 and the cache memory 21.
3, 24 are connected. The processing unit 3 includes a processor 30, a cache memory 31, and a processor bus 32, and signal lines 33 and 34 are connected between the bus master controller 6 and the cache memory.

The main memory 5 is divided into a plurality of blocks of the same size, and data is transferred in block units with the cache memories 11, 21, 31. Each of the cache memories 11, 21 and 31 is made up of a plurality of entries. As shown in FIG. 2, each entry includes an address information section 61 in which a block address is stored and a block data section 62 in which block data is stored. , "2" is set when prohibiting (locking) the rewriting of the data in the block data section 62, "1" is set when prohibiting (locking) the reading, and "0" is set when neither rewriting nor reading is prohibited (unlocked). Lock state section 63, a valid section 64 in which "1" is set when the content stored in the entry is valid, and "0" is set when the entry is invalid, a block in the block data section 62, and a block in the main memory 5. The modification unit 65 is configured to set "1" when they do not match and "0" when they do match.

FIGS. 3 and 4 are flowcharts of the processing performed by the cache memory 11 when the processor 10 of the processing unit 1 accesses the block Ba containing the data designated by the address a of the main memory 5, and FIG. FIG. 6 is a flow chart of processing in which the other processing units 2 and 3 check the access output to the system bus 4. Each process in FIGS. 3 to 6 can be executed in parallel by using a logic circuit. The processing of FIGS. 5 and 6 is executed within a predetermined time after the other processing units 2 and 3 output to the system bus 4.

When the processor 10 outputs the address a, the type of read or rewrite, the lock or unlock instruction, and the rewrite data (only in the case of rewrite) to the processor bus 12, the entry E storing the block Ba is stored in the cache memory 11. Exists and the valid portion 64 of the entry E is "1" (valid) (step 101). (1) When the cache memory 11 does not have a valid entry for storing the block Ba, the cache memory 11 notifies the bus master controller 6 of a request for using the system bus 4 via the signal line 13 (step 102). The bus master controller 6 gives permission to use the system bus 4 to only one cache memory according to a predetermined procedure. The permission to use the system bus 4 is given to the cache memory 11 via the signal line 14.
Is given to the read / write bus 43, the cache memory 11 outputs the address a on the address bus 41.
To the access type bus 44, and the access type (read or rewrite) output by the processor 10 is output to the access type bus 44 (step 103). The cache memories 21 and 31 receive the address a output to the address bus 41 (step 201) and check whether the block Ba including the data of the address a is stored inside (step 202). . (1-a) When the cache memories 21 and 31 do not store the block B _a inside The predetermined time (the cache memories 21 and 31)
Is longer than the time required to perform the processing shown in FIGS. 5 and 6) and the cache memories 21 and 3
If 1 does not output a signal to the transfer response bus 46 or the inconsistency response bus 47, the latest block exists in the main memory 5 and is locked in the cache memory 21 or 3
1 does not exist, the main memory 5 outputs the block B _a to the data bus 42, and notifies the cache memory 11 via the transfer response bus 46 that the response (data) has been output. (1-b) a cache memory 21 or 31 is locked portion 63 of the entry e stored if block B _a storing block B _a therein "0" (unlocked) whether examined (step 203). Here, there are generally the following two cases of combinations of lock states for which it is necessary to guarantee unpredictability in performing exclusive control. Rewrite access or read access is newly performed to a block in the rewrite lock state (“2”) in another cache memory (the content of the block is not updated during the lock period because another processor rewrites the block. Indeterminate from other processors). Rewrite access is performed to a block in the locked state (“1” or “2”) in another cache memory (other processors do not rewrite the block, but if the self processor rewrites the block, the block is read. Despite being locked, the contents of the block will be undefined from other processors). Therefore, the lock state part 63 of the entry e in which the block B _a is stored is “2” (rewrite lock), or the cache memory 11 is “rewrite” to the access type bus 44.
Is output, the fact that a contradiction has occurred is notified to the cache memory 11 via the contradiction response bus 47 (steps 204, 205, 206). When the cache memory 11 receives a notification from the cache memory 21 or 31 of the processing unit 2 or 3 via the contradiction response bus 47 that a contradiction has occurred, the cache memory 11 performs the contradiction resolution process shown in (3) below. The lock state part 63 of the entry e is not “2” (rewrite lock), and the cache memory 11 “rewrites” the access type bus 44.
If is not output, the modification unit 6 of the entry e
5 is "1" (B _a block B _a and the main memory 5 of the block data section 62 mismatch) whether examined (step 204,205,207). If the modification unit 65 is “1”, the cache memory 21 or 31 outputs the block B _a stored in the block data unit 62 of the entry e to the data bus 42, and the transfer response bus 46.
The cache memory 11 is notified that the response has been output via (step 208), and the modification unit 65 “0” of the entry e (B _{a of the} block data unit 62).
And B _{a of the} main memory 5 match (step 20).
9). At this time, the main memory 5 receives the block B _a output from the cache memory 21 on the data bus 42 together with the cache memory 11 and updates the contents stored in the main memory 5 to the latest contents. When the lock state part 63 of the entry e is “0” (unlocked state), the modification part 65 of the entry e in which the block B _a is stored is stored.
There "1" (B _a and B _a main memory 5 of the block data section 62 mismatch) whether examined (step 21
0). If modifier unit 65 is "1" entry e to store the block B _a (B _a mismatch B _a and the main memory 5 of the block data section 62), the latest contents of the block B _a cache memory 21 or 31 (here, the cache memory 21), the cache memory 21 outputs the block B _a to the data bus 42 and notifies the cache memory 11 that a response has been output via the transfer response bus 46. (Step 211),
The modifier unit 65 "0" (B _a and B _a main memory 5 of the block data section 62 matches) (step 212). At this time, the main memory 5 receives the block B _a output from the cache memory 21 on the data bus 42 together with the cache memory 11 and updates the contents stored in the main memory 5 to the latest contents. If the cache memory 11 outputs "rewrite" to the access type bus 44, the valid portion 64 of the entry e in which the block B _a is stored is set to "0" (invalid) and invalidated (steps 213 and 214). . As a result, the processor 1
When the access from 0 to the block B _a is “rewrite”, the content before rewrite does not exist in the other cache memory 21 or 31, and the data consistency is guaranteed.

The cache memory 11 uses the conflict response bus 4
Receive notification of inconsistency (“on”) via 5
Otherwise, the block requested via transfer response bus 46
B _a Is output to the data bus 42, and the data bus 42
Block B output above_aLock state part 63
Predetermined from the entry that is “0” (unlocked state)
The selected entry (selected entry
Block data portion 62)
The address information is stored in the address information section 61.
Then, the valid portion 64 is set to "1" (valid) (step
104, 105). Processor 10 is the processor bus
12 access types "read" and "lock finger"
Is output, the lock state part 63 of the entry E is output.
Is set to "1" (read lock state) (steps 105 to 105).
107), the processor 10 accesses the processor bus 12.
If "Rewrite" is output as the process type, the
The modification unit 65 of the bird E is set to "1" (step 1
09), when "lock instruction" is output Locked state
The part 63 is set to "2" (rewrite lock state) (step
110, 111).

[0021] The modifier unit 65 of the access type for the block B _a is equal to "rewrite" entry E from the processor 10 to "1" (block B _a mismatch block B _a and the main memory 5 of the block data section 62)
From the processor 10 to the processor bus 12
The data designated by the address a of the block B _a stored in the block data portion 62 of the entry E is rewritten with the content instructed via the entry E, and the access type from the processor 10 to the block B _a is “read”. For example, the data designated by the address a of the block B _a stored in the block data section 62 of the entry E is read and transferred to the processor 10 (step 122). The cache memory 11 informs the bus master controller 6 via the signal line 13 that the use of the system bus 4 has been completed. (2) When there is a valid entry E in the cache memory 11 for storing the block B _a containing the data at the address a requested by the processor 10 via the processor bus 12, the processor 10 is outputting to the processor bus 12. When the access type is "rewrite" and the modification unit 65 of the entry E is "0" (block B of the block data unit 62)
_a and the block B _a of the main memory 5 match),
The cache memory 11 informs the bus master controller 6 of a request to use the system bus 4 via the signal line 13,
When the bus master controller 6 gives permission to use the system bus 4 to the cache memory 11 via the signal line 14 according to a predetermined procedure, the cache memory 1
1 outputs the address a on the address bus 41, outputs "read" to the read / write bus 43, and outputs "rewrite", which is the access type output by the processor 10, to the access type bus 44 (step 112, 11
3). At this time, when the notification that the contradiction has occurred is received from the cache memory 21 or 31 of the processing unit 2 or 3 via the contradiction response bus 47, the cache memory 11
Performs the contradiction resolution process shown in (3) below (steps 114 and 124). If the cache memory 21 or 31 does not output the signal indicating that the contradiction occurs on the contradiction response bus 47, the cache memory 11 outputs a signal indicating that a response is output to the transfer response bus 46, and the block from the main memory 5 is output. The transfer of B _a is suppressed (block transfer is unnecessary because the block B _a already exists in the cache memory 11), and the bus master controller 6 is notified via the signal line 13 that the use of the system bus 4 has been completed. (Step 116). The cache memory 11 performs the following processing regardless of the access type that the processor 10 outputs to the processor bus 12 and the value of the modification unit 65 of the entry E. (2-a) When the lock state part 63 of the entry E is “0” (unlocked state) When the processor 10 outputs “read” and “lock instruction given” to the processor bus 12 as the access type, the entry When the lock state unit 63 of E is set to "1" (read lock state) (steps 106 to 108) and the processor 10 outputs "rewrite" and "lock instruction present" as the access type to the processor bus 12,
The lock state part 63 of the entry E is set to "2" (rewrite lock state) (steps 106, 109 to 111).

Block B from processor 10_a Against
If the access type to be rewritten is “rewrite”, the entry E
The define section 65 is set to "1" (B in the block data section 62).
_a And B of main memory 5_a Disagreement) and
(Step 120), processor 10 to processor
Block of entry E with contents instructed via page 12
Block B stored in the data section 62_a Address
Rewrite the data specified by the
Block B_a Access type is "read"
If it exists, it is stored in the block data section 62 of the entry E.
Block B _a Data specified by the address a of
Transfer to the processor 10 (step 123). (2-b) The lock state part 63 of the entry E is "1" (read
Output lock state) or "2" (rewrite lock state)
When the access type from the processor 10 is “read” and
If there is no lock instruction, the locked state of entry E
The part 63 is set to “0” (unlocked state) (step 11
7 to 119), the block data portion 62 of the entry E
Paid, block B_a Specified by address a
Transfer the data to the processor 10 (step 12)
3). The access type from the processor 10 is “rewrite
If it is “E”, the modification section 65 of the entry E is set to “1”.
(B of the block data section 62_a And B of main memory 5_a 
And (steps 117 and 12)
0), if there is a lock instruction, entry E is locked
The state part 63 is set to "2" (rewrite lock state) (step
121, 122), if "no lock instruction",
The lock state part 63 of the entry E is set to "0" (unlocked state).
State) (step 119), and the processor 10
The contents of the entry E of the contents instructed via the sessa bus 12
Block B stored in the block data section 62_a 
Rewrite the data specified by the address a of
123). (3) Conflict response bus 47 from other processing units 2 and 3
When a notification indicating that a contradiction has occurred is received via the cache memory 11, the process being executed by the processor 10 is executed.
Process and restart the process after a predetermined time has elapsed.
The main memo opened or rewritten by the process being executed
A process for restoring the contents of item 5 to the state before the process started executing
A predetermined period of time after processing
After the lapse of time, the process is executed from the beginning (step 12).
4).

As described above, the processing of securing / releasing the access right of the common data which the processing units 1, 2 and 3 simultaneously access in parallel is performed at the same time as the processing of the processing units 1, 2 and 3 accessing the common data. Therefore, each processing unit 1, 2,
It is possible to prevent the effective processing performance of the processing units 1, 2 and 3 from decreasing without increasing the processing amount in the processing unit 3.

Next, an embodiment of claim 2 will be described below.
In this embodiment, the contradiction response bus 47 of the system bus 4 in FIG. 1 is deleted, and “contradiction response bus 47 is on?” (Steps 104 and 114) and contradiction resolution processing (step 124) in FIG. 3 are deleted. , Step 206 of FIG.
Is changed to "contradiction resolution processing". 7 and 8 are flowcharts showing the processing of the cache memory 11 when the processor 10 accesses the block B _a in this embodiment, and FIGS. 9 and 10 show that the other processing units 21 and 31 output to the system bus 4. It is a flowchart of the process which checks the made access.

In the present embodiment, when a shield is generated, the shield is not notified to the cache memory of the processing unit of the access source, but the shield is canceled by the shield detecting source (processing is stopped).
Do. As a result, the amount of hardware is reduced by the amount of the conflict response bus 47.

Next, an embodiment of claim 3 will be described below. In the present embodiment, the processor 10, the cache memories 11, 21, 31 of the respective processing units 1, 2, 3,
20 and 30 are provided with rewritable priority registers, and the processors 10, 20, and 30 write the priority of processing to be executed in the priority registers at the start of execution.

The cache memory 11 which obtains the use permission of the system bus 4 from the bus master controller 6 and outputs the address to the system bus 4 outputs the priority written in the priority register to the priority bus 45. When a contradiction occurs in the process of checking the access output to the system bus 4 by the other processing units 2 and 3 (step 206 in FIG. 6), the cache memory of the processing unit that has detected the contradiction is assigned to the priority bus 45. Compare the output priority with the priority written in the priority register,
The priority written in the priority register is the priority bus 4
If the priority is higher than or equal to the priority output to No. 5, the signal indicating that the inconsistency has occurred on the inconsistency response bus 47 is output and written in the priority register, as shown in the embodiment of claim 1 above. When the incorporated priority is lower than the priority output to the priority bus 45, the processing being executed by the own processor is stopped as shown in the embodiment of the second aspect.

As described above, among the processes for accessing the common data in parallel at the same time, there are a process having a high priority and a process having a high priority and a process having a low priority which are to be executed with priority over other processes. In the meantime, when a conflict occurs with the common data, the process with the low priority is stopped and the process with the high priority is executed with priority. The priority register may be provided in the processor 10, 20, 30.

Next, an embodiment of claim 4 will be described below. In the present embodiment, when the process being executed by the processor 10 does not need the exclusive control of the common data in the locked state, the processor 10 causes the cache memory 11 to operate.
Is notified to the lock release. When the cache memory 11 receives this notification, as shown in FIG. 2, the lock state reset instruction signal 66 (reset means) is turned on, and the values of the lock state parts 63 of all the entries in the cache memory are set to "0". To do.

As a result, when it becomes unnecessary to access the common data in the locked state in the process executed by the processor, the access for releasing the lock (the block is accessed without issuing the lock instruction). It is not necessary to perform (access) for each block storing common data, and the number of accesses from the processing unit for unlocking can be reduced. In particular, it is effective in releasing the locked state for the conflict resolution processing.

[0031]

As described above, the present invention has the following effects. (1) According to the invention of claim 1, when the exclusive control information and the access type output to the system bus by the processing unit are a predetermined combination that causes a prediction of processing, the exclusive control information is set. By notifying the processing unit of the address output source that the access to the existing block has been performed, the processing of securing / releasing the access right can be performed when the processing units access the common data accessed in parallel at the same time. It becomes possible to execute the access at the same time as the access executed in each processing unit, the overhead of the processing unit for securing and releasing the access right does not occur, and the effective performance in the processing unit can be improved. (2) The invention of claim 2 notifies the processor of its own processing unit that the cache memory that has output an address to the system bus has accessed a block in which exclusive control information is set for the address. By doing so, the amount of hardware of the system bus is reduced. (3) According to the invention of claim 3, a priority register in which the priority of processing is written is provided in the processing unit, the priority is output to the system bus, and when a shield comes out when accessing the common data, Causes a process with a high priority to be executed by suspending or canceling a process with a low priority. (4) According to the invention of claim 4, when the process being executed by the processor does not need to access the common data, the lock state part of all the entries is reset (in the unlock state) to release the lock. The number of accesses from the processing unit is deleted.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiprocessor system showing an embodiment of claim 1 of the present invention.

FIG. 2 is a diagram showing a configuration of entries in cache memories 11, 21, 31 in FIG.

3 is a flowchart showing an operation of a cache memory 11 in response to an access from a processor 10 in the embodiment of FIG.

4 is a flowchart showing an operation of a cache memory 11 in response to an access from a processor 10 in the embodiment shown in FIG.

5 shows another processing unit 2 in the embodiment of FIG.
6 is a flowchart showing an operation of checking access according to No. 3;

FIG. 6 is another processing unit 2 in the embodiment of FIG.
6 is a flowchart showing an operation of checking access according to No. 3;

FIG. 7 shows a processor 1 according to an embodiment of claim 2 of the present invention.
6 is a flowchart showing an operation of the cache memory 11 with respect to access from 0.

FIG. 8 is a processor 1 according to an embodiment of claim 2 of the present invention.
6 is a flowchart showing an operation of the cache memory 11 with respect to access from 0.

FIG. 9 is a flowchart showing an operation of checking access by other processing units 2 and 3 according to the second embodiment of the present invention.

FIG. 10 is a flowchart showing an operation of checking access by other processing units 2 and 3 according to the second embodiment of the present invention.

[Explanation of symbols]

 1, 2, 3 processing unit 4 system bus 5 main memory 11, 21, 31 cache memory 12, 22, 32 processor bus 13, 14, 23, 24, 33, 34 signal line 41 address bus 42 data bus 43 read / write Bus 44 Access type bus 45 Priority bus 46 Transfer response bus 47 Contradiction response bus 61 Address information part 62 Block data part 63 Lock status part 64 Valid part 65 Modify part 66 Lock status reset instruction 101-125, 201-207 Steps

Claims (4)

[Claims] 1. A plurality of processing units, a main memory, and a system bus that connects the plurality of processing units to the main memory, the processing unit including a processor and a cache memory, and an address space of the main memory. Is divided into a plurality of blocks, and the cache memory is composed of a plurality of entries. In each of the entries, an address of the block, an address information section in which the block is stored, a block data section, and the block data section And a lock state part in which exclusive control information for prohibiting reading or rewriting of data stored in is set, wherein each processor sets exclusive control information in the lock state part of the entry of the cache memory of its own processing unit. Exclusive control information setting means and exclusive When a cache memory of a processing unit outputs an address and an access type to the system bus, the cache memory of another processing unit has a block designated by the address. If the exclusive control information is set in the lock state part of the entry that stores, and the exclusive control information and the access type output to the system bus by the processing unit are a predetermined combination, the exclusive control information A multiprocessor system characterized by notifying a processing unit of an address output source that an access has been made to a block in which is set. 2. A processing unit as an address output source indicates that the cache memory that has output an address to the system bus has accessed a block in which exclusive control information is set for the address output to the system bus. The multiprocessor system according to claim 1, wherein the processor of the self processing unit is notified instead of the above. 3. Each processing unit is provided with a priority register which is rewritable by the processor and which writes the priority of processing executed by the processor at the start of execution, and the cache memory of the processing unit stores the priority register together with access information. To the system bus, and the cache memory of another processing unit accesses the block in which the exclusive control information is set for the address output to the system bus. Compare the priority of its own processor with the priority output to the system bus, notify the processing unit of the address output source when the former is higher than the latter or equal to the latter, and when the former is lower than the latter, The multiprocessor system according to claim 1, wherein processing being executed by the processor is stopped. 4. The exclusive control of the lock state part of all entries in the cache memory when the processing being executed by the processor in the processing unit of the cache memory does not require the exclusive control of the common data. 4. The multiprocessor system according to claim 1, further comprising reset means for resetting information.