JPS58125146A - Arithmetic device of microprogram system - Google Patents

Abstract

PURPOSE:To control many function blocks without increasing the capacity of a microprogram storage memory by deciding on whether a format requires a jump address or not. CONSTITUTION:Through an texternal input terminal 31, NRZI data from a digital audio disk is supplied to a demodulation part 32. This demodulation part 32 generates a PLL clock of, for example, 2.16MHz from an input data string. The data demodulated by this demodulation part 32, i.e. 2.16M-bit/sec NRZ data and the PLL clock are supplied to a trailing decoding part 33, which decodes previously error corrected and encoded data. Then, deinterleaving and error correction are performed. The data decoded by this decoding part 33 is supplied to a speaker 35 through a D/A converter 34.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a microprogram type arithmetic unit K(d), which enables efficient use of memory for storing microprograms.

When the content of arithmetic processing is complex, it is conceivable that K parallelizes each functional block that shares the arithmetic processing and controls these using a horizontal microprogram system. In this way, each functional block performs arithmetic processing in parallel, so more arithmetic processing can be performed in a shorter time.

In such a system, it is desirable to control more functional blocks simultaneously. If so, it would be possible to perform calculation processing more efficiently.

However, in order to control more functional blocks, 1
The number of step bits must be increased, which increases the capacity of a memory for storing microprograms, such as a ROM (read only memory).

The present invention has been made in consideration of these circumstances, and it is an object of the present invention to provide a microprogram-based arithmetic device that can control more functional blocks without significantly increasing the capacity of memory for storing microprograms. It is an object.

In this invention, the format of the microprogram is devised in order to achieve this purpose. That is, some microinstructions require a jump address and others do not. Determine the things and conditions that cause an unconditional jump, and jump according to the results! A jump address is required for those that perform this. On the other hand, if an instruction can be skipped by simply incrementing the program counter by one and then executing the next microinstruction, the jump address is unnecessary. In the present invention, a branch field is provided in a format so that it can be determined whether the format requires a jump address or not. In formats that require jump addresses, part of the control field is used as a jump address field, and in formats that do not require jump addresses, control contents can be stored in all of the control fields, allowing more arithmetic processing. That's what I do.

An embodiment in which the present invention is applied to error correction noodle making will be explained below, but before that, an error correction code and a transmission system to which this embodiment can be applied will be explained.

When describing error correction codes, a cyclic group representation is used instead of a vector representation. First, consider an irreducible m-th degree polynomial F(ri) on G F (2).

A field G F (2) where only the elements 10″ and @1′a exist
On , the irreducible polynomial F has no roots. Then consider a virtual root α that satisfies (F(x)=O) in ζ.

At this time, 2m different elements 0. α, α2. α3...αm-I
Fl, constitutes the extended body G F (2m”), G
F (2ffl) Fi is a polynomial polynomial of degree m over GF(2) modulo F(2).G F (2
′! The origin of I) is 1. α-(X).

(12-(X2) *・・”” aαyn-1, (xr
n-1) can be scraped off by a ship-like connection. That is, aO+a 1(x) + a2(x 2) +
−”= , a, , −1(x !I″−' ) lo
Hatake0+11α+a2α +・・・・・・ 10 ~-1α
! -1 or (radius-1; "m-71...*
a2. al, a(1) where 1. aoImlm”
"" e l, -,6GF(p) O-As an example, considering GF (2'), (rnodsF(x)
= x +x +x +x +1), and all 8-bit data is &7X +JX +a, x +a4! +Ih5X +
a2X +alX+1() or Fi(a7116.as1
14Ia5#a2, 11. ao), so for example, Otori is assigned M S B ll'l s 1'6 to LsBfIll. au, GF(2)
Since it belongs to , it is either 0 or 1.

The following product I sequence T of (mXm) is derived from the Makai polynomial F(,).

Sen's 5i! 1-Currently, there is a method using a cyclic group.

This takes advantage of the fact that the remaining elements, excluding 07C, form a multiplicative group of rank 2rr+-1.If we express the elements of GF(2m) using a cyclic group, 0.1 (=α2′″-1), a, c12. a5.
,・The song becomes α2m-2.

Now, in one example of the present invention, m bits are one word, and n
When creating one block in Word, use the following +
Check words are generated based on the IJT check matrix H.

Similarly, the parity check matrix is expressed by the matrix T,
! is the identity matrix of (rnxm).

As described above, both the expression using the root α and the expression using the generator matrix T are significantly the same.

Furthermore, four (k-4) check words are used.

One block of received data is expressed as a column vector V-(Vi, -4
Jn-2+ "..." +Qr1+gold. ) (Idanshi W
i = W 1 + @ 1, .: error pattern), four syndromes occur on the receiving side So # 81
``'2'sS''. This error correction code can correct up to 2 word errors in one error correction block, and when the error location is known, it can correct 3 word errors or Fi4 word errors.

4 check words (p””W5*q) in 1 block
``'lF2 sr-wlel town.'' is included.

This check-4 If we omit the calculation process and only show the results, becomes. In this way check word p#Q.

What forms r81 is the output of the encoder provided on the transmitting side.

Next, we will discuss the basic Alprism that prevents errors fJ when data containing a check word formed as described above is transmitted and received.152F! A.

[1] If not x 5-: 8o-S, -1-8
2-S, M O [2] 1 word error (The error pattern is @1, and when I is changed sequentially, it is determined whether there is a 1 word error or not based on whether the above relationship holds. Alternatively, it becomes 5O82SSI s, s, s2, and the error location L can be found by comparing the .7 turns of α with those stored in the ROM in advance.

This is exactly 1 of the Toki's syndrome St/error pattern.

[3] In the case of 2-word error (J - sj) If the above equation is transformed, it is determined that it is a 2-word error, and the error pattern is as follows. This will be explained with reference to FIGS. 1 to 5. This transmission system is audio PCM
(This is the No. 1 recording and reproducing thread, and more specifically, it can be considered as a tokiomari reproducing device or a rotating disk device.

Ki1shiI shows the error correction encoder installed in the recording thread as a whole, and an audio PC is connected to the input side of the error correction encoder.
An M signal is provided. For audio PCM signals, each of the left and right stereo signals is sampled at a sampling frequency hf (for example, 44.1 (kHz)), and then
It is formed by converting the sample into one word (16 bits in two's complement code). Therefore, for the left channel audio (s+-), (Lo
+ Ll + R2......) and PCM data where each word is Ah is obtained, and the right channel audio signal is also (ROr R1e R2...)
PCM data in which each word is continuous is obtained.The left and right channel PCM data are divided into 6 channels each, and a total of 12 channels of PCM data series are input. At a predetermined timing,' (L6n
'R6n'' ``6n+1 'Rbn+1' L6
r++2'Rbn+2 1L6yl+! S ° R6
n+5'"6n+4' R6n+41L
6n+5'R6n+5) 12 words are input. In this example, one word is divided into upper 8 bits and lower 8 bits, and 12 channels are further processed as 24 channels. For simplicity, one word of PCM data is
Id, wlm with respect to the upper 8 bits
, and a suffix of A is added, and for the lower 8 bits, a suffix of "ff1IB and B is added to distinguish 0. For example, IdL6n is W12H, A and W, 2n9
．． It will be divided into two parts.

This 24-channel PCM data sequence is first supplied to an even-odd interleaver (1). (fi WO
, 1, 2...), then L611 (=W, 2n, A
1"11+a,l)% R6n(-"12m+1.A
% Wttt4-+, m) % "6n+2("
"12m+4.A '"12m+4.1)
'R6n+2 (-=12n+4.A'
W12+++4.1) ・R6n+2(=”12
m+5. M-W12+++5, B)'
L6n+4' ” ”+211 +-8, ^'
W12n+8. m) %R6n+4 (-W12+s+
9,1%w121(-9,B) are even-numbered words, and the other words are odd-numbered words. Each of the PCM data series consisting of even-numbered words is processed by the 19-delay circuit (2A) (2B) of the even-odd interleaver (1).
(3A) (3B) (4A) (4B) (5A) (5B) (
6A) (6B) (7AX7g) K: Therefore, it is delayed by one word. Of course, a larger number than one word, for example eight words, may be delayed. Furthermore, in the even-odd interleaver (1), 12 data sequences consisting of even-numbered words occupy the 1st to 12th transmission channels, and 12 data sequences consisting of odd i=th words occupy the 1st to 12th transmission channels. It is converted to occupy the 13th to 24th transmission channels.

The even-odd interleaver (1) is a sixth interleaver that prevents two or more consecutive words from becoming 1 in each of the left and right stereo signals, but this error becomes uncorrectable. For example, if we consider (Li-1# Ll + L1+1) and the three words that follow the divine sequence, if Ll is wrong and this error cannot be corrected, then L, or, or +, is correct. is desired. When correcting incorrect data L1, hold the previous correct word L, -1 for 1ili (previous value hold) or % L, -1
This is to interpolate the average value of i+1.Delay circuit (2A) (2) of even-odd interleaver (1)
B) to (7A) (7B) Fi, Wk are provided so that adjacent words are included in different WA small correction blocks. Also, the reason why transmission channels are grouped into data sequences consisting of even-numbered words and data sequences consisting of odd-numbered words is that when interleaving, adjacent even-numbered words and odd-numbered words This is to make the distance between recording positions as large as possible.

The output of the even-odd interleaver (1) contains the PCM data series of 24 channels in the first arrangement state. One word is extracted from each channel and supplied to the encoder (8), and the first Checkword Q12naQ1$41
"12n+2" +2!1+5 is formed. 1st
The first error correction block including check words of (w12B-12,A % W12B-12,1'
"'12n+1-12.A %"0m+1-12. ”
m'"12n+12.mu~"12yl+4-12.
m, W12n+5-12. M% W12i+5-12
．． 1% "12n+8-12μm"+2n+8-1
2. m% ”Bn+9-12.m%”12fi+9
-12.1%"12y1+2.A'"121-
)2-~ ”'12m+3.x %”12　Ll
5W12n+6. A% ”12n+6.m%
”12n+7.At W12n+7+l.

”+2n+10.A% W12n+10j%
"12n-Hl, Mu'121+11.s % Q12
n% Q12B+14 Q12B+2s Q12n+!
l). In the first encoder (8), the number of words in one block: (n - 28), the number of pitches in one word: (I
1-8), and the number of check words is (k-4).

These 24 PCM data sequences and 4 checkword sequences are supplied to an interleave (9).

The interleaver (9) changes the position of the transmission channel so that a check word sequence is interposed between the PCM data sequence consisting of even-numbered words and the PCM data sequence output from odd-numbered words, and then performs interleaving. Delay processing is being performed for this purpose.

This delay process excludes the first transmission channel ID,
2D, 31), 4D,...---, 26D,
This is accomplished by inserting a delay circuit with a delay t of 27 D (where D is a unit delay amount, for example, 4 words).

At the output of the interleaver (9), 28 data sequences in the second arrangement state appear, one word is extracted from each of these data sequences and supplied to the encoder OQ,
Second check word P, 2ml.

P12n+1 ” 1211+2 ”12144 is formed ・32 is formed including the second check word
The second error correction block of words is:

(vBn-'Lm%"'12ns12(D+1), 1
1 12n+ S -12(2o+1), A %"
121←2(5D-i-1), s%”12n+4-12
(4 leaves 1), 5% ”'12fi+4-12 (5 leaves 1)
, 1%"12n+5-12 (6 leaves 1), A' = 12
n+5-12(7D+1), m%Q12n-12(+2
D)% Q121+1-12(130)” 12n+2
-12(14D)'Q12fi+5-12(150), "j2fi+1O-12(24D), Muichi"'12n
+1O-12(25n), m'''12n+1l-
12 (24D), mu 1”12yl+1l-12(27n
)'m'P12n% Pj2n+1%
P12n+2 "12n-14) The first
An interleaver (1υ) is provided in which a 1-word delay (b) path is inserted for even-numbered transmission channels among 32 data sequences including the second check word and the second check word. An inverter (121 (13) (141 (151) is inserted for the check word sequence of There is.

In addition, all data in one block is @θ due to dropout during transmission from inverter 02 to asFi.
This is provided to prevent 814!III production, which would identify this as the correct one for plum silk.For the same purpose, an inverter is also inserted for the first check word series. You can do it like this.

Therefore, the 3 data extracted from each of the 24 dynamically obtained PCM data sequences and the 8 checkword sequences are
Each two words are serialized, and as shown in FIG. 2, a 16-bit synchronization signal is added to the end of each word to form one transmission block and then transmitted.

In FIG. 2, for simplicity of illustration, one word extracted from the first transmission channel is displayed as ut.

The above-mentioned encoder (8) Fi relates to the error correction code as mentioned above, and is (n-28, -4 for m = 8. k-4
).

The reproduced data is applied to the input of the error correction decoder I shown in FIG. 3 every 32 words of one transmission block. Since this is playback data, it may contain errors. If there were no errors, the 32 words added to the input of this decoder would result in 32 words appearing at the output of the error correction encoder.
Matches the word. In the error prevention decoder, a dinterleave process corresponding to the interleave process in the encoder is performed to restore the data order and then perform frame correction.

First, a dinterleaf 4UL in which a 1-word delay circuit is inserted is provided for the odd-numbered transmission channel, and an inverter C+ is provided for the check word sequence.
7) QFO(1!J (20) is inserted and supplied to the Q output of the first-stage rear encoder. In the rear encoder, as shown in Fig. 4, the parity check matrix Hc and the input 32 words are (■
T) and Syndrome S. +811 +81
2 eSl is generated, and based on this, the error correction as described above is performed. α is (F(x) = x
+x +x +x2+1) is an element of G F (28). From the decoder (c), 24 PCM-f-event sequences and 4 check word sequences can be seen, and each word of this data sequence has at least a 1-bit pointer (:J) indicating the presence or absence of an error. - Fi′″1″ is added when there is an error, and 60′″ when there is not. It is simply expressed as Wl.

The output data series of this post-signal unit Qv is the dinter leaver e
4. The dinterleaver @ is jlL made by the interleaver (9) in the erroneous side-stop encoder.
This is for canceling the processing, and is applied to each of the transmission channels from the first transmission channel to the 27th transmission channel (27D, 260.25D, etc.).

Delay circuits with different delay amounts are inserted. The output of the dinter leaf 4 (2) is supplied to the next stage (sequel generator). In the decoder, as shown in FIG.
A syndrome 820' S211 S221 S25 is generated from the parity check matrix HC2 and the 28 input words, and error correction is performed based on this.

The data sequence appearing at the output of the subsequent encoder (to) is supplied to the even-odd interleaver (c). In the even-odd dinter riba (goods), the PC consisting of the even-numbered words
The M data series and the PCM data series consisting of odd-numbered words are returned to positions on different transmission channels, and a one-word delay circuit is inserted for the PCM data series consisting of odd-numbered words. ing. At the output of this even-odd dinterleaver (c), a PCM data sequence having exactly the same arrangement and predetermined number of transmission channels as that supplied to the input of the error correction encoder is obtained. Although not shown in Figure 3,
A correction circuit is provided next to the even-odd dinter leaver, and correction, such as average value interpolation, is performed to make errors that could not be completely corrected by the post encoder (21) (c) less noticeable.

This completes the explanation of the error correction code and transmission system used in the embodiment of the present invention.

An embodiment in which the present invention is applied to an error correction device will be described below with reference to FIGS. 6 to 15.

FIG. 6 shows the whole of this embodiment, in which 0υ
indicates an external input terminal, and NRZ I data from, for example, a digital audio disc is supplied to the demodulator 0 through this external input terminal. This post-tuning section ohs data modulated using a modulation method suitable for the 02Fi digital audio disc.

ElleV! This demodulates modulated data using 8-bit to 14-bit block coding. Also, this post-tone part 0■ is, for example, 2, 16 M from the input data series.
Forms a Hz PLL clock. After this, some data is demodulated with 0 bits, for example, NR of 2.16 Mbit/See.
The Z data and the above-mentioned PLL output are decoded by the subsequent decoding unit (toward).
K supply. This decoding section (to) decodes data that has been error correction encoded in advance.

That is, it performs dinterleaving and error correction. Then, the data decoded by this decoding section (to) is D
/A converter ■ to the speaker (c). Note that (to) is an oscillator that generates a clinical clock.

T! Figure 47 shows the decoding unit (to) of #'i No. 61\1 in detail; in this Figure 7, the decoding unit (c) is
It consists of a (random access memory), a write address generator, a read address generator, an error correction circuit, and an interpolation circuit. In this case, the demodulated data from demodulator 0 → (Figure 6) is sent to the data input terminal (
6), buffer (42m) and data bus (/43m)
The data is sent to the RAM (Of) via the write address generator (of) and written based on the write address of the write address generator (of). Then, based on the read address of the read address generator (to), the data written in the RAM u'h is read out and sent via the data bus (6), the interpolation circuit θ, and the data output terminal. Later stage D/A converter (b) (
Figure 6). And like this RAM Of
), the data is rearranged, ie, dinterleaved, by writing and reading data.

Note that (60) is a PLL clock input terminal, (61) is a PLL frame synchronization signal input terminal, (62) is a Fi crystal clock input terminal, and (63) is a Vi crystal frame synchronization @month input terminal.

Furthermore, during the writing and reading of this data, errors are corrected and the contents of RAM p7) are read based on the read address from 1st path 00, specifically the decode address V of the #'i decode address generator, and an error occurs. The 11th test will be held. Note that (/4 is a priority control circuit and +tAMO
'h access priority read address generator 9@
, write address generator (to) and error correction, 1st path...1 is determined in this order. Further, 0η is a multiplexer.

In this example, a horizontal microprogram method is adopted for the error correction circuit (6). That is, one step of the microprogram can cause multiple functional blocks to execute instructions.

This error correction circuit is converted into a program counter (,4→,
ROM (Read Only Memory) 4, 1 word correction calculation circuit, ? It consists of an ink adding circuit (51x52), a decode address generator, etc.

ROM Q → is for storing the microphone quadrogram, and each field of this ROM (6) is specifically used as a fii control signal/jump address generator (53).
, C1 decode/C2 decode address generator (54)
It serves as a % error position address generator (55).

CI decoding corresponds to decoder Q1) in FIG. 3, and C2 decoding corresponds to decoder Q1).

Note that the program counter () is driven by the functional clock from the priority control circuit (see terminal (2)), so that the correction operation is performed at a timing other than the dinterleave operation in the RAM p''I).

In this case, the C1 decode/C25' code address 17 is sent to the decode address generator via the logical OR circuit (56). The decode address generator uses this address signal to specify the pointer to the RAM (
371 'i access. As a result, C1 decoding -
The bits of the address signal of the C2 decode address generator (54) are made small. The data thus calculated based on both address generators fi (54) is transferred to the one-word correction calculation circuit 6) via the data path. On the other hand, the control signal from the control 141 block/jump address generator (53) is sent to the 1-word correction settlement circuit member via the Happatufa register (57), and based on this control signal, each word is Error correction operations are performed. At this time, the word with the error correction, that is, the error position, is also determined by this one-word correction calculation circuit, and based on this determination signal, the error position address generator (55) is activated to detect whether the word with the error has been booted or not. Generates an error location address indicating where it is inside.

And this error position address is the logical off circuit (5
6) The error word is sent to the RAM (3'I) via the decode address generator and multiplexer, and a pointer of "1" is attached to the error word via the register (58), and the other words are sent to the RAM (3'I). (59) through “
0" pointer is added.

To help understand this error correction circuit (6), we will explain its C1 with reference to the flowchart shown in FIG.
The 7' need mode and the C2-yh code mode will be explained. The algorithm of this CI decoding mode and C2 decoding mode is the first error correction code c
The process begins by determining whether there is an error in 1. Clear the ViCI pointer if there are no errors (
(set to "0").

On the other hand, if there is an error, it is determined whether it is a one-word error or a count word error, and if it is a count word error, C1/inter is placed on the word with the error and the board "1" is written.
), and when the error is a one-word error, K
a Correct it, then add Cl to the word with the error.
Put up a pointer.

In this way, the C1 decode mode is performed.

Continuing with the stiffness (C2 decoding mode, 1) First, determine whether there is an error in the second error subtraction code, and if there is no error, clear the Fic2i inter.If there is an error, further Determines whether or not it is a one-word error, and then if there are multiple word errors in one block, set C2/ink to the corresponding word while monitoring the KitC1i interface.On the other hand, if there is a one-word error, that word Determines whether or not is the same as the word that set the CIf ink.If it is the same, an error is canceled and the C2 pointer is cleared.On the other hand, C
If the word to which the 1 pointer has been added differs from the error word, this is determined to be an erroneous detection and all word KC2 pointers in the block are set. In this way, the C2 decode mode is ended.

The C2 pointer set at each word by VC is monitored in this manner, and the word is complemented in the interpolation cycle j121+-. For example, pre-interpolation and intermediate interpolation are performed.

Next Pc: The specific format of the microprogram stored in the ROM will be explained with reference to section 99.

In this format, one step consists of 23 bits, each consisting of a 2-bit branch field, a 13-bit control field, and an 8-bit RAM address field. It is divided into two types depending on its purpose. These two formats are distinguished by the content of the branch field.

When the content of the branch field is "00", a format indicating Fi 9th entry A is used. This format is a no-operation, ie, the next step is executed in the next cycle. In this case 13
Of the control field of pit F, 8 bits indicated by A-H are used. The contents of the A-H commands will be described later.

On the other hand, when the branch field is "rlOJroIJrll", the format shown in FIG. 9B for t= is adopted. In this format, of the 13-bit control field, 5 bits at A-E'i are used as true control bits, and the remaining 8 bits are used as a jungle address. When the content of the branch field is "10", the process moves to the step specified by the jump address. That is, the contents of the Janshi address are transferred to the program counter. Also Blanchfield or “01”
and when it is "11", rlJ corresponding to the state of Ka'an
The rOJ is determined and a step jump is performed.

Next, the contents of the command of each bit A to H of the control field will be explained.

The instructions executed by the microprograms stored in the ROM can be broadly divided into: ■Syndrome operations and ■Syndrome S. -8, are all "0", that is, there is no error, (2) error correction and pointer addition. The syndrome calculation can be determined based on K whether So-8, -82-85 is satisfied.

When this formula is satisfied, no error occurs. Actually Fi(So■S, ■S2■s, )■s.

is calculated, and if the result of this calculation is rOJ, it is determined that there is no error. Here, ■ is addition mod 2.

Error correction begins by determining the location of the error.

This decision So-α-1B, -α-21S2-α-4$l.

It is good to find i that determines. Then, according to this error position 1, the amount of W is ``Ws + S.

Error correction can be done by executing .

As shown in Table 1, the control contents of each pin A to H in the control field of the microprogram described above correspond to instructions for performing syndrome calculation, error determination, and error 1 correction.

Table 1 To help understand the above format, an example of a format for performing syndrome calculations on a predetermined data block in the C1 decoding mode will be explained E7 with reference to FIG.

In the format example shown in FIG. 10, the content of the branch field is "00", indicating that there is no operation. The contents of the 8 bits of A-H in the other field are all rooloollJ, and from this control content, first, the syndrome operation jL (A-0) and the judgment of S-O (B-0
), RAM @ read mode (C-O), syndrome calculation possible (D-1), syndrome calculation (E-0),
It can be seen that the other operations result in no operation (F, G, H-0). And in the RAM address field, each content is 3F, 3E, 3D, 3C...30...
・2F...23, and each of the 32 words of the block is read out. However, the RAM address field Fi is expressed in hexadecimal notation.

The format of the microprogram in this example employs two formats using branch fields, and when a jungle address is not required, the entire control field can be assigned to a control signal. Therefore, in steps that do not require branching, more functional blocks can execute the instructions, and in this case, the bit V of one step can be made smaller.

In addition, determination of the content of the above branch field K Fi@,
The circuit shown in FIG. 11 can be used. In FIG. 11, the input terminal (64) is supplied with the LSB of the data signal, and (65) indicates an arithmetic circuit that executes a predetermined arithmetic operation. Then, a control signal is obtained from the control input terminal (66), for example, by using one bit of the microprogram to switch between the signal from the input terminal (64) and the signal from the arithmetic circuit (65). The signal SENS is physically stored in the condition determination circuit (67). This condition determination circuit (67) Fi is a combinational circuit that realizes the truth table shown in Table 2, and input terminals (68×69) are supplied with the two pins (BT and BT2) of the fidget branch field. The output of the condition judgment circuit (67) is supplied to the load spore (70) r(m) of the glogram counter (48), and the condition judgment is performed. ) Transfer K↓
I'm doing it. "O" means no operation.

Table 2 As is well known, from such a truth table it is possible to obtain the example shown in FIG. #'i Kinmei would not approve of this.

Next, what is the specifics of the 1-word correction viX circuit (50) used in this example? Let's explain about lIK with reference to Fig. 13. This one-word correction calculation circuit (1 circuit) consists of circuit units (71) (72) (73) (74), and these circuit units ( n X72X73X74) and syndrome S, respectively. ,S.

821 S, 'f shadow formation. And circuit unit a
2).

Syndrome 81 + 8 in (73) and (74)
2 a 85 is multiplied by α-, α-, and α-51, respectively.

In the case of 1, each word of the block Via is sent via the next data selector (75) (76) (77) and directly to the adder (78X79X80X81)K. Words that could not be sent to the adder (78) are returned to the adder (78) via the latch (82). As a result, this circuit unit (71) causes syndrome S. is obtained. On the other hand, the word sent to the adder (79) of the other circuit unit (72) is sent to the adder (79) via the α multiplier data selector (84) and the latch (85). ) will be returned. As a result, this circuit unit (7
In 2), syndrome S is obtained. Similarly, the circuit units) (73X74) each have syndrome 82.
+ Ss can be obtained. Station 811 will not be happy about this.

Syndrome S obtained in this way. From -8° (s, C) S, ■S2■S, ■S4)■S.

is obtained. That is, the syndrome S is supplied via the data selector (77) to the adder (80) K, where it is added to the syndrome S2 by 8. Further, the sum of 11 (85.times.S2) thus added is sent to another adder (79) via the data selector (76), where it is added to the syndrome S. Then, (s, 520S3) obtained here is sent to the adder (78) via the data selector (75), where the syndrome S. is added. And this is how I got it (so
■S, eS2■S3) is additionally beneficial (86) and syndrome s. Don't add it to (so■S, ■S2■s, )■S.

is obtained. The result of this calculation is judged to determine whether there is an error. This calculation result is derived via a terminal (93).

To determine the error location, use the thin line obtained as described above.
Drome So-S, α- and α-, respectively.

Sequentially dividing by α-5, that is, the syndrome S, is circulated through the α-3 power generator (87), the data selector (wing), and the latch (89). Then, if it is cycled i times, S, α-31 can be obtained.

Similarly, other circuit units) (71X72X73) are S. , S, α-B2(1-21) and thus obtained S., S, α-, S2α-21 and S3α
-51 Determine the error position while monitoring whether there is an abnormal flea.

Note that an error position counter counts up in response to one such cycle, and the error position address is determined based on the contents of this counter. For example, a ROM may be used to generate this error position address, and by specifying a sending pointer to the above-mentioned decode address generator (45), R
AM (37) can be accessed.

After performing syndrome calculation and error location address generation in this manner, K performs one-word error correction. That is, the error word is read out based on the error word address and transferred to the latch (90). Then, the error word command of this latch (90) and the syndrome S of the other latch (82).

are added by an adder (91). This means w1←w, (
fys.

, and error correction is performed by this addition.

This error-corrected word w1 is then stored in the buffer (
92) and the RAM (
37).

In addition, in the circuit unit (71) in Fig. 13, (9
4) Fi data selector, circuit unit (72
), (95) is an α-1 multiplier, in the circuit unit (73), (96) is an α2 multiplier, (97) is an α-2 multiplier; 98) Fiα3 multiplier.

In this example, a multiplier (83
X96) and (98) are constructed as shown in FIG. 14A, B, and C, respectively. Also in this Figure 15, ■1r
It shows the addition of rod2, and specifically consists of an exclusive OR. α11α2 and α5 are lower body GF
(28) Corresponds to changing the location of each data by 1°2.3 sinuts in the above, and the generator polynomial is X8+X'
+X' +X2+ 1. Maewa can easily understand these things.

α-1, α-2 and α-3 power equipment (excluding 311L equipment)
(95), (97), and (87) are shown in Figure 15 A and B.
, as shown in C, is similar to that of Kirin.

According to this embodiment, instead of configuring the decoding section with random logic as in the past, a microgram system is adopted. As a result, the ROM can be used extensively and the internal poles of the chip can be kept small. And, L
This facilitates design when converting to SI. It is possible to easily determine which one of the flodrams loaded in the ROM is optimal.

The use of a switched common bus makes logic easier to see and design more reliable.

In addition, since readout of the RAM, falsification or dinterleaving, and error correction are executed in parallel with the priority hole 1) cycle #8Q*, decoding becomes less efficient. Moreover, since each functional circuit is parallelized and controlled by a horizontal microprogram method, each instruction can be executed simultaneously, making decoding more efficient.

Furthermore, a branch field is added to the microprogram format, making it possible to distinguish between those that support branching and those that do not. For those that require a branch, a jump address is included, and for those that do not require a branch, the 51' control bits can be expanded by the bits allocated to the jump address. Therefore, more instructions can be executed with fewer ROMs.

As described above, according to the present invention, a branch field is added to the microprogram format, thereby making it possible to distinguish between instructions that cause a branch and instructions that do not require a branch. The format of instructions that do not require a branch includes a jump address, while the format of instructions that do not require a branch allows for expansion of control bits for dividing the bits allocated to jump addresses. . Therefore, more arithmetic processing can be performed with less memory capacity, and as a result, arithmetic processing can be performed efficiently.

Note that the present invention is not limited to the above-mentioned embodiments,
It is possible to be calm and cheerful within the scope of not deviating from the idea.

[Brief explanation of the drawing]

Both Figures 1 to 5 are used to explain the present invention.
FIG. 6: A block diagram showing the entire embodiment of the present invention applied to error correction equipment, FIG. 7, FIG. A flowchart for explaining the operation of the rear part Q. Figure 9 is a line 1 showing the format of the microprogram stored in ROM 4 of the rear part Q of Figure 7. Figure 10 is the format of Figure 9. Figures 1, 11 and 12 show an example of
Both figures are block diagrams to explain the format of the 9th ty+, silver, 13th and 1st! Figure 7'4 JI No. 1 part (
Block diagram showing a specific example of the 1-word correction calculation circuit phrase in 2), Figure 14 #1113I\1 Adjust α in Example 1 (83)
, a diagram showing an example of the configuration of an α-squared 1j4 unit (96) and an α3 multiplier (98), Fig. 15.
5), an α-multiplier (97), and a diagram showing a configuration example of an α″″ multiplier (87). C9 is the decoding unit, (b) is the RAM of the data series dinterleave river, (g) is the write address generation gain, g4#
'i read address generator, 4 ROM which stores the microprogram%-Fil word correction calculation circuit, (
51), (52) is the pointer addition step 5, Figure 9:... Figure x x x x'x'x'
x'x'xqx' xta x 4
x 3 s'x'x'x'
X'X5X'X3X'X'X'X X
X X X3X1×0 1st rv diagram

Claims (1)

[Claims] In a microprogram type arithmetic device that causes a functional block to execute a microinstruction regarding data stored in a random access memory based on a microprogram, the format of the microprogram includes a branch field, a control field, and a random access memory address field; A microprogram type arithmetic device, characterized in that the branch field specifies the presence or absence and conditions of a jump, and in a format in which a jump is possible, a part of the control field becomes a jump address.