KR920010184B1 - Circuit for calculating finite fields - Google Patents

Abstract

No content.

Description

[Name of invention]

Finite Field Computation Circuit

[Brief Description of Drawings]

1 is a block diagram of one embodiment of the present invention.

2 and 3 are flowcharts and schematic diagrams for explaining the multiplication operation of this embodiment.

4 and 5 are flowcharts and schematic diagrams for explaining the division operation of this embodiment.

6 is a block diagram of another embodiment of the present invention.

7 and 8 are schematic diagrams for explaining a table of another embodiment.

9 is a flowchart for explaining the multiplication operation of another embodiment.

10 is a flowchart art for explaining a division operation of another embodiment.

11 is a block diagram of a reproduction circuit of a digital audio disc to which the present invention can be applied.

12 is a schematic diagram for explaining the reproduction data of a digital audio disc.

13 and 14 are time difference art and block diagrams for explaining the error correction circuit.

* Explanation of symbols for the main parts of the drawings

1: Memory 2: Aerator and Compute

3: control unit 10: aerator

11: adder of (mod.2) 21: rom

22: RAM 23: CPU

24,25,26: Memory area 28: Index register

29: calculator 50: buffer memory

51: error correction circuit

Detailed description of the invention

The present invention relates to a finite field calculation circuit applied to an encoder of an error correcting code and a decoder.

[Technology Background]

When recording and reproducing a digital video signal, a digital audio signal, or the like, adjacent codes, lead solomon codes, and the like have been put into practical use as error correcting codes. In the encoders of these error correcting codes, parity data (redundant data) is generated, and in the decoder, a credibility is generated from a destination word including parity data, and error correction is performed using this credibility. As hardware of this parity generation circuit, syndrome generation circuit, and error correction circuit, a finite field calculation circuit is used. A finite sieve is a sieve with pm circles guided by a primitive polynomial P (x) of order m, and (P = 2) is important for error correcting codes. Therefore, this invention is applied to the finite body of (P = 2).

As a finite field arithmetic circuit used for an encoder and a decoder, multiplying any circle α ⁱ on a finite field by the wall square of α is used. For this multiplication, α ⁱ was input into the ROM to obtain the dimension i. For this reason, ROM is required and the circuit size becomes large. Moreover, in the case of order m, the judgment of mod. ( ^2m- 1) is required with respect to the exponent, and there is a drawback that it is complicated because the judgment is not a power of two.

The lead solomon code is used as an error correcting code for the main channel of a digital audio disc (called compact disc), and the decoding circuit has a hardware configuration using a TTL circuit. In recent years, the operation speed of the microprocessor and the increase of the storage capacity are remarkable, and if the error correction circuit can be configured by the microprocessor which is usually used, there is no need to design a new LSI, thereby reducing the cost. In particular, the sub-coating signal of the above-mentioned digital audio disc has a lower data rate than the main channel, and when recording digital data such as video data using the digital audio disc, temporary burring of the reproduction data is possible. This can be realized by a microprocessor which normally uses a decoder of error correction code.

Accordingly, it is an object of the present invention to provide a finite body of arithmetic circuit with a reduced amount of memory, such as a ROM, a register, and the like.

Another object of the present invention is to provide a finite field circuit for reducing the number of steps by reducing the required number of memories and for speeding up the processing.

It is another object of the present invention to provide a finite field computation circuit capable of multiplying or dividing arbitrary two circles on a finite field by a program store method.

Another object of the present invention is to provide a finite field calculation circuit suitable for an encoder and an decoder of an error correcting code.

[Initiation of invention]

The present invention according to a predetermined circle on the finite field α ⁱ and α of a finite field for the multiplication or division of the (where, α is a root of the primitive polynomial of the finite field) operation circuit, for storing a predetermined circle α ⁱ A finite body having an accumulator, an adder for adding the contents of the aerator and the vector representation of the primitive polynomial (mod. 2), and a control unit for program controlling the operation of the abiter's bit shift and adder. Is the operation circuit of.

In the present invention, in the finite field computation circuit for multiplication or division of two circles α ⁱ and α ^j (where α is the root of the finite polynomial), A first table for generating, a second table for generating a finite circle in the exponent, a binary operator for adding and subtracting the exponent, a data conversion consisting of the first and second tables, and 2 It is a finite field computation circuit having a control unit for program control of the operation of the true operand.

Best Mode for Carrying Out the Invention

An embodiment of the present invention will be described with reference to FIG. In FIG. 1, (1) shows a storage part, (2) an aerator and a calculation part, and (3) shows a control part. This example uses (P (x) = x ⁷ + x + 1) on GF (2 ⁶ ) as a primitive polynomial. Each circle is represented by a ₅ x ⁵ + a ₄ x ⁴ + a ₃ x ³ + a ₁ x + a ₀ , and multiplying this circle by α gives a ₅ x ⁶ + a ₄ x ⁵ + a ₃ x ⁴ + a ₂ x ³ + a ₁ x ² + a ₀ x (a ₅ = 0), then a ₄ x ⁵ + a ₃ x ⁴ + a ₂ x ³ + a ₁ x ² + a ₀ x (a ₅ = Since x ⁶ = x + 1 when 1), a ₄ x ⁵ + a ₃ x ⁴ + a ₂ x ³ + a ₁ x ² + (a ₀ +1) x + 1. According to the vector representation, when (a ₀ = 0) (a ₄ , a ₃ , a ₂ , a ₁ , a ₀ , 0) when (a ₅ = 1) (a ₄ , a ₃ , a ₂ , a ₁ , a ₀ +1,1). In the register 4 of the storage unit 1, the vector representation of the primitive polynomial P (x) is stored, and 0 is added to the upper level (01000011).

The storage unit 1 is provided with a program ROM 5, a RAM 6, and a determination circuit 7. The program ROM 5 is supplied with an address from an address generator (not shown) to which the determination output of the determination circuit 7 is supplied, and instructions are generated in the program ROM 5 in a predetermined order. This command is supplied to the control unit 3 to generate a control signal for controlling each of the path 8, the path 9, the aerator and the calculation unit 2 in the control unit 3.

The attenuator and arithmetic unit 2 adds the contents of the aerator 10 and the aerator 10 and the mod. 2 which is the contents of the register 4 through the path 8, and amplifies the addition output. It has the adder 11 supplied to the radar 10. The attenuator 10 performs one-bit left shift or one-bit right shift operation in response to a control signal from the control unit 3, and at the time of this shift operation, the bit at the end portion of the register 12 is moved. The output is 0. The attenuator 10 is set with data from the RAM 6 via a pass 9, and arithmetic output is supplied to the RAM 6 via a pass 9.

In the above-described embodiment of the present invention, the operation of multiplying arbitrary circles α ⁱ and α on GF 2 ⁶ will be described based on FIG. 2 and FIG. 3.

Initially, 6 bits of the vector representation of α ⁱ are read out from the RAM 6 and stored in the aerator 10 via a path 9. If 8 bits of the attenuator 10 are referred to as bit 0 to bit 7, as shown in Fig. 3, the six bits of the vector representation of α ⁱ from bit 0 to bit 5 (a ₅ , a ₄ , a ₃ , a) ₂ , a ₁ , a ₀ ) are stored.

As a next step, the agitator 10 is shifted 1 bit to the left. 3B shows a state shifted 1 bit to the left. Then, the bit 6 of aekyum concentrator 10 by the decision circuit 7, i.e., a ₅ that is irradiated is to whether the zero. When (a ₅ = 0), the six bits (a ₄ , a ₃ , a ₂ , a ₁ , a ₀ , 0) from bits 0 to 5 of the attenuator 10 are multiplied by (α ⁱ × α). It becomes an output, and the RAM 6 is output from the aerator 10 through the path 9.

When (a ₅ = 1), the contents of the aerator 10 (FIG. 3B) and the contents of the register 4 of the storage unit 1 (FIG. 3C) are added to the adder 11 of (mod. 2). It is added by. The six bits from bit 0 to bit 5 of this sum output become (a ₄ , a ₃ , a ₂ , a ₁ , a ₀ , 1 + 1) and this sum output is a multiplication output of (α ⁱ × α). The path 9 is output from the aerator 10 to the RAM 6.

Expression vector at the time of a muscle α to the primitive polynomial ^{(P (x) = x 6} + x + 1) will be specifically shown below. However, for the sake of simplicity, (α ° to α ¹² ) are shown.

α ⁰ = (000001)

α ¹ = (000010)

α ² = (000100)

α ³ = (001000)

α ⁴ = (010000)

α ⁵ = (100000)

α ⁶ = (000011)

α ⁷ = (000110)

α ⁸ = (001100)

α ⁹ = (011001)

α ¹⁰ = (110001)

α ¹¹ = (100011)

α ¹² = (000101)

As an example, when the present invention is applied to the multiplication of (α ¹¹ × α) (a ₅ = 1), the addition operation is performed (000101), that is, the multiplication output of α ¹² can be obtained.

In this embodiment, (α ⁱ + α) can be divided. 4 shows a flowchart art in the division operation. Initially, the vectored six bits (a ₅ to a ₀ ) of α ⁱ through the path 9 in the RAM 6 are stored in bits 0 to 5 of the aerator 10 as shown in FIG. 5A. Next, the judgment circuit 7 checks whether the bit 0, i.e., a ₀ is zero. When (a ₀ = 0), the attenuator 10 is shifted to the right by one bit, and the state of Fig. 5b is reached. Then, bits 0 to 5 of the attenuator 10 are supplied to the RAM 6 as a division output through the path 9 and stored in the RAM 6.

When (a ₀ = 1), the contents of the aerator 10 shown in FIG. 5A and the contents of the register 4 shown in FIG. 5C through the path 8 are added to the adder 11 of (mod. 2). It is added by. This addition output is shifted right by one bit and supplied to the RAM 6 through the path 9 as a division output from bit 0 to bit 5 of the attenuator 10 and stored in the RAM 6.

As a specific example, in the division of (α ⁶ + α) (α ⁶ = 000011) is stored in the aerator 10, and the addition operation is performed because of (a ₀ = 1). The content of the attenuator 10 in which the addition output is stored is (01000000), and the content (100000 = alpha ⁵ ) from bit 0 to bit 5 after being shifted right by one bit becomes a division output.

The multiplication of (α ⁱ × α ⁿ ) or the division of (α + ⁱ α ⁿ ) may be repeated n times of the above-described calculation steps.

6 shows another embodiment of the present invention. Another embodiment applies the present invention to an arithmetic circuit for multiplying or dividing any two circles α ⁱ and α ^j on a finite field.

In Fig. 6, 21 represents a ROM, 22 represents a RAM, and 23 represents a CPU. The RAM 21 has a memory area 24 in which a program command is written, a memory area 25 in which a first table for data conversion is written, and a memory area 26 in which a second table is written. If the primitive polynomial is (P (x) = x ⁶ + x + 1) on GF (2 ⁶ ), for example, the root of the primitive polynomial is α, and α ⁰ to α ⁶² and 64 circles of ^zero circle exist.

The table of the memory area 25 of the ROM 21 has an address of n to n (+63), as shown in FIG. 7, and the circle α ⁱ on the vector-expressed GF 2 ⁶ is supplied as this address. The index i is output as data. When the vector expression of α ⁱ is corrected in the order of increasing by one expression from (α ⁰ = 00000001), it becomes (α ¹ , α ⁶ , α ² .... α ⁵⁹ , α ⁵⁷ , α ⁵⁸ ). Since the ROM 21 uses an 8-bit unit, the data in the table is 8 bits, and the upper 2 bits of each are all 0, and the vector representation of 3 ⁱ is 0 in the upper 6 bits. 8 bits are added. No data is written in the address n corresponding to the zero source in which alpha ⁱ is zero.

The table of the memory area 26 of the ROM 21 has an address of m to (m + 63), as shown in FIG. 8, an index i of 0 to 62 is supplied as this address, and α ⁱ as data. To print. This data is a vector representation of i ⁱ , with two bits added to the top of six bits. Since the address m + 63 becomes (α ⁶³ = α ⁰ ), this address is not actually used.

The CPU 23 is provided with an operation unit 29 including a control unit 27, an indes register 28, and an aerator. The index register 28 is coupled to the RAM 22 through a path 30, and the calculation unit 29 is coupled to the RAM 22 through a path 32.

The contents of the index register 28 become addresses for the memory area 25 and the memory area 26 of the ROM 21 via the path 31 and are supplied to the calculation unit 29 through the path 34. . The data output from the memory area 25 and the memory area 26 of the ROM 21 is supplied to the calculation unit 29 through the path 33. The control unit 27 receives a command read from the memory area 24 of the ROM 21 and receives the index register 28, the calculation unit 29, and the paths 30, 31, 32, 33, Generate a control signal to control 34. Although not shown, the output of the address counter is supplied to the memory area 24.

In another embodiment of the present invention described above, an operation when multiplying (α ⁱ × α ^j ) of any two circles α ⁱ and α ^j on the GF 2 ⁶ will be described.

In FIG. 9, the index register 28 is shown as Ir, and the aerator of the calculating part 29 is shown as ACC.

Initially, the vectorized data of α ⁱ in the RAM 22 is transferred to the index register 28 via the pass 30. It is checked whether alpha ⁱ stored in this indes register 28 is a zero source. Since the multiplication output is naturally zero when it is zero, the associative operation is terminated by transmitting the zero source to the emulator of the calculating unit 29 through the pass 34.

When α ⁱ is not zero one, n added to the contents of the index register 28 is supplied as an address to the ROM 21 through the piece 31, and is stored in the ROM 21 by a table in the memory area 25. The index i is accessed and the index i is stored in the aerator of the calculating part 29 via the path 33.

Next, α ⁱ is read from the RAM 22, stored in the index register 28 through the path 30, and it is checked whether or not this α ^j is a zero source. When? ^j is a zero source, the multiplication output is naturally zero, so the zero source is stored in the aerator of the calculating unit 29 via the pass 34 and the multiplication operation is completed.

When α ^j is not zero, the addition of n to the contents of the index register 28 is supplied as an address to the ROM 21 through the path 31, and is stored in the ROM 21 by a table in the memory area 25. The exponent j is accessed and the exponent j is supplied to the calculation unit 29 through the pass 33. In the calculating section, addition of (i + j) is performed, and the addition result is stored in the aerator of the calculating section 29. The calculation unit 29 calculates (i + j) of (mod. 63), and the value of (i + j) (mod. 63) passes through the path 34 and is stored in the index register 28.

The addition of m to the contents of the index register 28 is supplied as an address of the ROM 21 via the path 31, and the vector expression value of α ^{i ± j} is accessed by the table of the memory area 26. It is stored in the accumulator of the calculating part 29 through the path 33. This vector representation value (α ⁱ × α ^j ) is returned to the RAM 22 via the path 32 as necessary.

In another embodiment of the present invention, the operation when dividing (α ⁱ + α _P ) of any two circles α ⁱ and α ^j on GF 2 ⁶ will be described based on FIG. 10.

Initially, the vectored data of α ₀ in the RAM 22 is transferred to the index register 28 through the pass 30. It is checked whether alpha ⁱ stored in the index resist 28 is a zero source, and when it is a zero source, the division output is naturally 0, so that the zero source is stored in the aerator of the calculating unit 29 through the pass 34.

When α ⁱ is not zero, the addition of n to the contents of the index register 28 is supplied as an address to the ROM 21 via the path 31, and the ROM 21 is supplied by the table in the memory area 25. The index i is accessed at, and the index i is stored in the aerator of the calculation unit 29 via the pass 33.

Next, α ^j is read out from the RAM 22, stored in the index register 28 through the path 30, and it is checked whether or not α ^j is a zero source. When alpha _P is zero, no division is possible, and thus a flag (i.e. girl flag) indicating that an abnormality is generated is generated and the operation is terminated. When α _P is not zero, the addition of n to the contents of the index register 28 is supplied as an address to the ROM 21 through the path 31, and the ROM 21 is supplied by the table of the memory area 25. The index j is accessed at This exponent j is supplied to the calculating part 29 via the path 33, the subtraction of (ij) is performed in the calculating part 29, and the subtraction result is stored in the aerator of the calculating part 29. The operation output of this (ij) is in the form of (mod.63), and the value of this (ij) (mod.63) is stored in the index register 28 via the path 34.

Through the contents of that path (31) m is added to the index register 28, it is supplied to the address of the ROM (21), a memory region 26 Table α _O ^← _P vector representation value and access by the Then, the path 33 is stored in the aerator of the calculation unit 29. This vector expression value α ⁱ + α _P is returned to the RAM 22 via the path 32 as necessary.

The finite field calculation circuit to which the present invention described above is applied is used for an error correcting code, for example, a decoder of a lead solomon code. This error correcting code is used for the sub-coding signal included in the reproduction signal of the digital audio disc.

11 shows the configuration of a reproduction circuit of an optical digital audio disc (so-called compact disc), wherein a reproduction signal read by the science head from the disc is input to the input terminal indicated by (41). Is supplied. The digital signal recorded on the disk is EFM modulated. EFM modulation is a method of block converting 8-bit data into a 14-bit desirable pattern (i.e., 14-bit modulated signal has a minimum minimum inversion time and a low frequency component thereof).

The digital audio signal returned by the EFM demodulation circuit 42 as 8-bit data is supplied to the error correction circuit 43, thereby performing error correction. The digital audio signal of one channel of the stereo audio signal output from the error correction circuit 43 is supplied to the D / A converter 44, converted into an analog signal, and output through the low pass filter 45 to the output terminal 46. Taken out). The digital audio signal of the other channel output from the error correction circuit 43 is supplied to the D / A converter 47, converted into an analog signal, and taken out to the output terminal 49 through the low pass filter 48. .

The reproduction signal from the disc includes, in addition to the stereo audio signal, a digital signal for control or display called a sub-coding signal. The sub-coding signal contains 8 bits per frame of the recording data, and is repeated every 98 frames, and the synchronization signal of the sub-coding signal is inserted in the first two frames of each 98 frames. The eight bits of the subcoding signal are distinguished from (P, Q, R, S, T, U, V, W). The P-channel is for distinguishing the recording section and the pose section of the music signal of the disc. The Q channel is a music number assigned to each of the disc's music signals, an index for subdividing each piece of music, a timecode that increases in the music section and decreases in the poise section, a timecode that changes sequentially from the beginning of the program area of the disc, It consists of a control bit indicating the presence or absence of pre-operation or the like. As for the Q channel, an CRC code for error detection is inserted into 16 frames on the end of 98 frames. By using the sub-coding signals of the P channel and the Q channel, it becomes possible to put out the specified music or the like.

The R channel to W channel are used to display or narrate the writer, composer, commentary, poem, etc. of a song recorded on the disc.

Among the sub-coded signals (8 bits x 98 frames), 96 frames of data except for the sync pattern, the P channel, and the Q channel are packaged. As shown in FIG. 12, the (6x96) bit kit is further divided into four packs of 24 symbols. The first symbol of each pack is the command, the next 19 symbols are data, and the remaining 4 symbols are the parity of the error correction code of each pack. This command is 6 bits with 3 bits of mode and 3 bits of item. Types of data (graphic data, still picture data, sound data, etc.) are displayed by three bits of the mode, and information of more detailed operation modes of each mode is displayed by three bits of this item.

The above-described subcoding signals are separated by the EFM demodulation circuit 42, stored in the buffer memory 50, and the subcoding signals of the R to W channels are error corrected by the error correction signal 51. Among the sub-coding signals, the data of the P channel Q channel are supplied to the system controller although not shown. The sub-coding signals of the R to W channels output from the error correction circuit 51 are written to the buffer memory 52 in the case of graphic data or still picture data, and the data read out from the buffer memory 52 is displayed in the display control circuit ( 53, and displayed on a display device 54 such as a CRT display.

When the subcoding signals of the R to W channels are sound data, they are taken out to the output terminal 57 through the D / A converter 55 and the low pass filter 56.

FIG. 13A shows the symbol clock (7.35 kHz) of the sub-coded signal in the reproduction data, and FIG. 13B shows the input symbol. In the error correction circuit 51, error correction is performed one pack at a time, as shown in FIG. 13C, and a pack already decoded during this error correction operation is output as shown in FIG. 13D.

The error correction circuit 51 has a CPU 61, a ROM 62 in which a program is written, and a RAM area RAM 63, as shown in FIG.

The error correction circuit 51 calculates an error and calculates an error location by using an input operation in which one pack of 24 symbols is written to the RAM 63 in the buffer memory 50, and data read from the RAM 63. The error correction operation for error correction and the output operation for outputting the data after error correction from the RAM 63 are performed under the control of the CPU 61.

As an error correcting code for a (6x24) bit pack, the (24, 20) lead solomon code is used. This Lidsolomon code is of primitive polynomial (P (x) = x ⁶ + x + 1) on GF (2 ⁶ ). Parity check matrix H _P ,

Is used, and the reliability is calculated from the matrix representation of one pack of sub-coded signals V _P and the parity check matrix H _P. Representing a reproduced symbol as W _i , synthism S ₀ , S ₁ , S ₂ , S ₃

을 뜻한다. 윗식에서 구해지는 신드로움에 의해 에러의 크기가 체크된다.It becomes only,

It means. The magnitude of the error is checked by the simplicity obtained from the above equation.

Without error: S ₀ = 0, S ₃ = 0

A = B = C = 0

1 symbol error: S ₀ ≠ 0, S ₃ ≠ 0

A = B = C = 0

2 symbol error: A ≠ O, B ≠ 0, C ≠ 0 However, (A = S ₀ S ₁ + S ₁ ² , B = S ₁ S ₂ + S ₀ S ₃ , C = S ₁ S ₃ + S ₂ ² ).

In each case of the above-mentioned one symbol error and two symbol errors, an error location is obtained.

1 symbol error (called location i)

: α ⁱ = S ₁ / S ₀

e _i = S ₀

I = Log (S ₁ / S ₀ ).

2 symbol error (error location is called i, j)

: α ⁱ = D / X

α ^j = D / Y

e _i = S ₀ / Y + S ₁ / D

e _j = S ₀ / X + S ₁ / D

However, D = B / A. X and Y are set to E = C / A, and X is obtained by (D ² / E → X), where D ² / E = α ^{← a} + α ^a , X = 1 + α ^a : a = ji = 1 to 23), Y is obtained by Y = D ² / E + X.

Correction of both 1 symbol error and 2 symbol error is performed by adding the error pattern (mod. 2) obtained by the reproduced error symbol.

In the error correction operation described above, the finite field calculation circuit according to the present invention is applied.

Particularly, when multiplying and dividing a circle on the vector-expressed GF 2 ⁶ is performed when the error state is struck or the error pattern is calculated, the present invention is suitable.

The subcoding signal of the digital disk has a slower data transfer rate compared to the data of the main channel, and the error correction circuit 51 of the subcoding signal can be configured using a microcomputer that is commonly used by applying the present invention. do.

According to the present invention, ROM is not used as the vector representation of a circle on a finite body, and furthermore, it does not require determination of (mod.2 ^m −1) of an exponent, and it is a finite field multiplication (α ⁱ × α) and division ( α ^j + α). Therefore, the size of the hardware can be reduced, and the number of steps for calculation can be greatly reduced. When the present invention is applied to a decoder of the lead solomon code, the hardware of the decoder can be simplified and the decoding time can be shortened.

In addition, according to the present invention, two arbitrary circles can be multiplied or divided in a vector representation of a circle on a finite body, and a microcomputer normally used as hardware can be used. Therefore, hardware can be realized at low cost.

Claims (2)

Arbitrary circles α ⁱ and α in a finite body phase, where α is the operation of a finite body to multiply or divide with the roots of the primitive polynomials of the finite body. A circuit comprising: an aerator for storing the arbitrary circle α ⁱ , an adder for adding (mod. 2) the content of the aerator and the vector representation of the primitive polynomial, and the And a control unit for program control of bit shift and operation of the adder. In a finite field calculation circuit for multiplying or dividing two circles α ⁱ and α ^j (where α is the root of the primitive polynomial of the finite body), the exponent A first table for generating a), a second table for generating a fortune of the finite body at the index, a binary operator for adding and subtracting the index, and a first table and a second table. Data conversion performed by a finite field calculation circuit comprising a control unit for program control of the operation of the binary operation.

Images