JPS62254540A - Error correction device - Google Patents

Abstract

PURPOSE:To attain sure error correction without increasing the number of storage circuits by using a flag so as to discrimiante whether or not a data word is interpolated in reading information from the storage circuit and applying the interpolation depending on the result of discrimination. CONSTITUTION:The correction state flag of the 1st decoder 5 is stored in the 1st check word area, the correction state flag in the 2nd decoder 4 is stored in the 2nd check word area, the correction state flag is loaded in outputting a data word by an interpolation circuit 6 and whether or not the interpolation is to be executed is decided depending on the state of the flag of the both. Thus, the error correction is ensured to either a burst error or a random error without increasing the capacity of the storage circuit 7 and the possibility of error detection overlook or mis-correction is precluded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides an error detection function and an error detection function for digital information used in a digital audio tape recorder or the like. Ti
'E'9! '＋'e f! This invention relates to an error correction device having an error correction device.

[Prior art and its problems] When using a recording medium with many errors, such as O-stape, double error correction codes are sometimes used.

According to this, each of the first and second check words constitutes a separate error correction block, so even if an error cannot be corrected with any one of the check words, the error can be corrected with the other check word. can be corrected, thus improving error correction capability. By the way, if even one bit in one word is wrong, the whole word is treated as wrong, so when dealing with received data that has a lot of random errors, the error correction ability is not necessarily sufficient. I can't say that there is.

Therefore, if you can correct up to, for example, a 2-word error within one block, and the error location is known, f! For example, when performing the next stage of decoding for an error correction block using an error correction code with a high correction ability of a distance of 5, which can correct even a 4-word error of 1, an error occurs even though there is an error in the first stage of decoding. If an error detection is missed or an incorrect correction occurs, such as when it is determined that there is no error, this missed error or incorrect correction becomes a cause for new missed nines or incorrect corrections in the next stage of equalization, and when viewed as a whole, There is a strong possibility that malfunction will occur.

In order to correct this, for example, 1-word errors and 2-word errors are corrected, and at the same time, for example, if a word of 3 or more words is erroneous, it is detected in the first stage decoding, and 1-word error is corrected. When it is corrected as an error, when it is corrected as a 2-word error, when it is corrected as an error of 3 or more words. 3.
It is thought that by distributing one pointer and determining the state of this pointer in the next stage of decoding and making corrections, it is possible to prevent the possibility of oversight or erroneous correction in the next stage of decoding. There is. According to this, it is possible to reduce the risk of oversight or incorrect correction during error detection and correction, and to solve the problem of abnormal noises caused by incorrect correction when transmitting an audio PCM signal, for example. However, since it is necessary to store the pointer state for each word, a large amount of storage elements are required. For example, for 8 words of data, the pointer requires 1 bit each, but 8 bits are also required.
It has the disadvantage of high cost.

[Object of the Invention] The present invention has been made in view of the above points, and is capable of reliably correcting both burst errors and random errors without increasing the capacity of a storage circuit.
Moreover, it is an object of the present invention to provide an error correction device that is less likely to miss error detection or make erroneous corrections.

[Summary of the Invention] The present invention provides correction state flags F in the first decoder.
? Stored in the check word area of i 1, the correction letter in the second decoder! t3 flag F4. j is stored in the second check word area, and when the interpolation circuit outputs the data word W, the correction state flags F,..., 1j Fq+jf are loaded, and it is determined whether or not to interpolate based on the state of both flags. This is a book written like this.

[Embodiments of the Invention] First, an error correction code used in an embodiment of the present invention will be described. When describing an error correction code, a vector representation or a cyclic group representation is used. However, -
As an example, the generator polynomial rF(X)=X8+X'+X'+X
Considering rGF' (28) J where the root of 2+I J is α, when using 4 check words with "1 block = 32 words", the parity check matrix HFi becomes as follows.

Then, when the transmission data is W, W=(WO, Wl, . . . , Wl0.W31) In the encoder, v'=.

4 check words that satisfy W28%W29, Wl
0, W31 is added. This error correction code can correct up to 2-word errors in one error correction block, and can correct 3-word errors or 4-word errors when the error location is known.

Then, when data including the above four check words is transmitted and received, error detection and error correction are performed as follows.

■ Syndrome S due to lack of received data. , Sl, S2,
Calculate S3.

■ Data for error determination A-E'ji syndrome 5o
Calculate from −83.

A=SoS2+S.

B=S, S2+5oS3 C=S, S3+82 D=B/A “E
=C/A ■ Perform error detection.

(a) 5o=81=82=8. = 0, there is no error and the data is not corrected, (b) 5o(0,51)o, 82':o%s3"
5゜When A=O1C=0, it is a one word error and the error location l
is calculated by l=log(S1/so), and △ Wz = Wt + S.

Error correction is performed by

(e) A(o, Boo, C”40 throat eid
2'7-)" or more error, and the error position is l,
Then, for all combinations of l and k that satisfy t+=zog(1, calculate the combination tn of l and k when α1+α1=D. If this relationship does not hold, 3 The error is one word or more, and it is not corrected at this time, and when it is collected, it is a two-word error. Find e1=(aSo+S,)/Dek=(αkSo+81)/D, and △ w = w. Correct by +e△%=Wk+ek.

Next, an embodiment of the present invention will be described with reference to the drawings. First, a code circuit having a code creation function will be explained. FIG. 1 is a block diagram of the code circuit, and FIG. 2 shows the arrangement of the codes.

As shown in FIG. 1, the encoder circuit is composed of a C1 encoder 1, a C2 encoder 2, and a memory circuit 3. Digital information is persistently input to the C7 code "a1" and stored in the memory circuit 3. In this case, the digital signal input to the C4 encoder 1 is ww %w as shown in the S area of FIG.
w...WO,0' 0,1 0.2'
0.3% 0.27%W W,...W
It is 784 words.

1.0- 1,1 27.27 In the C1 encoder l, w, , 0・
w, 1. °°゛W1.27 (however, 1==Q~27) to the check word w shown in area P in Figure 2,...
, w, ,%W1.301Wl,31 is determined and stored in the storage circuit 3. Then, A is stored in this memory circuit 3.
Send the code of 2rS+PJ to C2 encoder 2. In the C2 encoder 2, as in the C1 encoder 1, wO,, wl, j%W2. jl °−w27. j to check word w2B, j, w shown in Q area of Figure 2
l9. j, w, 0. j, w3. j (however, j = 0 to 3
1) Calculate. Therefore, from the C2 encoder 2, [S0P+
The sign of Q J is output.

Next, the decoding circuit will be explained. As shown in FIG. 3, the decoding circuit includes a C2 decoding circuit 4, a C1 decoder 5, a compensating circuit 6,
It consists of a storage circuit 7, and the code to which an error correction word has been added is input to the C2 decoder 4. The C2 decoder 4 sends the input codes to the storage circuit 7, and stores them in a designated array in sequence as shown in FIG. Further, the C2 decoder 4 performs w, , , w, , turtle W2 , j, W3 .
3%””29*j ′”3oej % Wsl, 5% (
However, from j = O ~ 31) □ syndrome S is calculated as described above and double correction is performed.At this time, according to the correction pattern, the current syndrome is calculated using the correction status flag Fqsj' as shown in Table 1 below. check word part of the block (W2B
, j 31. J). In the example shown in Figures 4 to W, the lower 3 bits of the array location of W are written 31,
j As above, the block changes from rj=OJ to rj=3
Once executed in Bt and stored in the correction state flag Fqtj' storage circuit 7, this content is then sent to the C1 decoder 5.

The C decoder 5 receives F −F 17) CM correction letter F
41 Q, OQjl
Although quadruple correction 1 can be performed using two flags, the more corrections are performed, the higher the probability of erroneous corrections will be, so corrections up to 2 word errors are performed while considering the possibility of erroneous corrections. If an error of 3 words or more cannot be corrected, a correction status flag F as shown in Table 2 below is displayed.
1*P is written in the check word portion (W, , 28 to W, , ) of the block currently being corrected.

In the example shown in Figure 21!4, Wi, is stored in the lower 3 bits of the array location of 31.

Table 2 However, in C14 unit 5, the check word of C1 (W
i, 28 to Wij1), if there are up to 2 word errors, correction is performed, and then the check word W, , 3
The lower 3 bits of the ゜ part are the correction status flags F,,p, and ``000J'' is written.

No error → 000 1st revision top → 000 2nd revision pressure → 000 So, when an error of 3 or more words is detected, C2 is applied to each word in the block currently being corrected.
The correction status flag "FQ, j = XXIJ (XX
I is the part with more than one correction in C2) (X can be either rO or 14) When the number M is "M≦4", the locus, nIM error of the word with pQ, j=xxt from each syndrome Then, perform the disappearance calculation.

FlK success fatfr Fi,, J'er O
00J failed r vll, Let J be roolJ.

If “M≧5” and 1! teeth.

rF = X11J (portion with double correction or more in Xll x C2) Q, If the number N of j is N≦4, the word location in this part is deleted and erasure calculation is performed.

If successful, r F,..., J, roooJ If unsuccessful, r
Let vl,, J be roolJ.

If N≧5, and if the number of FoIj=l l 1 (positions that cannot be corrected in C2) is L≦4, then the location of the load of Fo, j=111 is erased and the loss calculation is performed.

When successful, r v,, J is ``000'', when unsuccessful, r
Let F,,pJ be roloJ.

When L≧5 It is impossible to calculate the disappearance, r　Wi9. Let J be "lOO".

Note that when N≧5, 5 cannot be eliminated.

r pJ9. stored in the P and Q areas of the storage circuit 2 as described above. A word with a high probability of erroneous casing is determined from J r v, jJ, and the interpolation circuit 6 interpolates the word.

The interpolation circuit 6 includes, as shown in detail in FIG.
, and a selector 14, and data read from the memory circuit 7 is input to the latch circuit 10.11 and the input terminal A of the selector 14. And latch circuit 10.1
The 3-bit data latched to 1 is sent to the AND circuit 12.
a to 12c and the select signal SE via the OR circuit 13.
It becomes L (correction signal) and is sent to the selector 14. Further, output data of the latch circuit 15 is inputted to the input terminal BK of the selector 14. Said selector 14F1. The input data A, B' (selects and outputs to the latch circuit 15 according to the select signal SEL sent via the OR circuit 13. This latch circuit 15 latches the data selected by the selector 14, and outputs it to the latch circuit 15. input terminal B
At the same time, it is output to the next stage D/A conversion circuit (not shown).

The interpolation circuit 6 configured as described above includes a latch circuit 15.
From the D/A transformation circuit digital signal W. ,.

Before sending out Wo, 3. The correction letter flag F on the C1 side is stored in the lower 3 bits of the C1 side. 9. After full reading, the middle and lower three bits of the 8-bit 0.31 bit data of W sent from the storage circuit 7 are latched into the latch circuit 1o. Next, the C2 side correction state flag F0.0 stored in the lower three pits of W. . is read out, and the lower three pits are similarly latched into the latch circuit 11.

Furthermore, each flag information becomes a select signal SEL via AND circuits 12a to 12e and an OR circuit 13, and is sent to a selector 14. Then, the data of Wo and o are read out and applied to the input terminal A of the selector 14. Here, the select signal SEL is normally ``0'', and becomes 61'' when in the flag state shown in P and 3 below.

Table 3 When the select signal SEL applied via the OR circuit 13 is 10'', the selector 14 selects the input terminal A.
When the select signal SEL is 1'', the data on the input terminal B side is selected and output to the latch circuit 15. That is, the correction state flags Fi, , are latched in the latch circuit 10, and the data on the input terminal B side is selected and outputted to the latch circuit 15. , causes the latch circuit 11 to latch the input terminal 41, the data word Wi*j is applied to the input terminal A of the selector 14, and the select signal SEL becomes '
01 (under conditions other than Table 3 above), Wi and j of input terminal A are output from selector 14 and latch circuit 1
It is latched to 5. The data latched by the latch circuit 15 is sent to the next stage D/A conversion circuit and is also input to the input terminal B of the selector 14.

In addition, the above conditions are satisfied and the select signal SEL is @″1
When #, the input terminal B side of the selector 14 is selected, so the data sent to the D/A converter circuit last time is sent to the D/A converter again.
It will be sent to the A conversion circuit. That is, interpolation is performed by holding the previous value.

As mentioned above, the interpolation circuit 6 converts the data words W,,j into D
When outputting to the /A conversion circuit, C11j, l of Wi,j
The correction status flags F, jt on the C2 side are taken into the latch circuit 10.11 in advance, the reliability of the data word Wt, j is confirmed, and the data word wlI is
Take in j. In this way, when determining whether data words Wt, j can be interpolated, the correction status flags on the C4 side and C2 side stored in the storage area of the memory circuit 2 are used, and both flags are Since the error correction signal is loaded and a correction signal is created by a logic circuit, there is no need for a special circuit to store flags in each word, and an error correction circuit can be easily configured without increasing the number of storage circuits. .

In the above embodiment, interpolation processing is performed by holding the previous value, but interpolation processing using an average value may also be performed.

[Effects of the Invention] As described in detail above, according to the present invention, when a data word error-corrected by the first and second decoders is read out from the memory circuit, the memory circuit The first and second flags stored in the circuit are used to determine whether or not to interpolate the data word, and interpolation is performed based on the determination result, so a flag is specially stored for each word. It is possible to reliably perform error correction for both burst errors and random errors without requiring additional memory circuits, and without increasing the number of memory circuits. This makes it possible to provide fewer error correction devices.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention. FIG. 1 is a block diagram showing the configuration of the code circuit section, FIG. 2 is a diagram showing the code arrangement state in FIG. 1, and FIG. 3 is a block diagram showing the configuration of the code circuit section. A block diagram showing the configuration, FIG. 4 is a diagram showing the code arrangement state at the time of decoding of FIG. 3, and FIG. 5 is a diagram showing the code arrangement state during decoding of FIG. FIG. 4 is a block diagram showing details of the interpolation circuit in FIG. 3; DESCRIPTION OF SYMBOLS 1...C encoder, 2...C2 encoder, 3...Storage circuit, 4...C2 decoder, 5...C1 decoder, 6...
...Interpolation circuit, 7...Memory circuit, 10,11.15.
...Latch circuit, 14...Selector. Applicant's agent Patent attorney Takeshi Suzue 1 Figure r) Name 2 Tomomi ff, [Figure 5 from 1j17

Claims (1)

[Claims] Digital data is divided into a plurality of data word groups, a first error correction code is added to a first series of the data word groups, and a first error correction code is added to a second series of the data word groups. A second error correction code is added to the data word group and the first and second error correction codes are added to a storage circuit having a data word storage area and first and second error correction code storage areas. an error correction device that reads out the stored contents of this storage circuit and stores it in a storage medium, and performs error detection and error correction of a data word group using first and second error correction codes when reproducing this storage medium; Error detection and error correction are performed on the first series of the data word group, and the error correction state is stored as a first flag in the first error correction code storage area of the storage circuit. 1 decoder performs error detection and error correction on a second series of data words, and stores the error correction state as a second flag in a second error correction code storage area of the storage circuit. and a second decoder that corrects errors by the first and second decoders, and when reading the data word error-corrected by the first and second decoders from the storage circuit, the first decoder stored in the storage circuit corresponds to the data word. and an interpolation circuit that determines whether or not to interpolate the data word using the second flag and performs interpolation based on the determination result.