JPS58125129A - Direct memory access controller - Google Patents

Abstract

PURPOSE:To attain memory access with a jump over plural addresses at a high speed by adding data in an address and a temporary register together through an accumulator. CONSTITUTION:At the initial timing T1 of a timing pulse generating circuit 7, the top address Y of the address register 1' is outputted as it is to an address buffer 3' and conversion data in the temporary register 4 is set as the output of the accumulator 5 as it is. At the next timing T2, the data X and Y are added together by an adder 6 and at timing T3, the addition result X+Y is set in the address buffer 3'. At the timing T2, the data X in the temporary register 4 and the data X in the accumulator 5 are added again to obtain data 2X and at the T3, addition 6 is performed to obtain X+2Y and resetting is performed. This operation is repeated to set Y, Y+X, Y+2X, Y+3X... in the address buffer 3' one after another and they are outputted to an address bus. Thus, X- skip access is speeded up and suits to Fourier transformation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a direct memory access control device.

As digital signal processing technology advances, high-speed arithmetic processing is required. Furthermore, since digital signal processing handles a huge amount of data, it is not possible to store the data using a processing arithmetic unit alone. Therefore, it is necessary to store data in an external storage element and perform processing by direct data transfer with an arithmetic unit.

Conventionally, there is a direct memory access control device as shown in FIG. 1 to realize this. In this device, a memory start address is set in an address register 1, and each time a memory access is executed, an incrementer/decrementer 2 increases or decreases the address value, and memory accesses are executed one after another. This indicates that high-speed, continuous data transfer is possible without host processor intervention. However, in digital signal processing, every few pieces of data may be successively extracted and processed. - As an example, [Fast Fourier exchange is a typical example of digital signal processing. For the data that is continuously output to the memory at this stage of calculation, the next calculation often requires every few pieces of data.

Data access at this time cannot be performed by the above-mentioned direct memory access control device. Furthermore, if this data transfer were to be performed via the host processor, it would take more than twice as much time. This can be said to be a major hindrance to digital signal processing, which handles large amounts of data and requires high-speed processing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a direct memory access control device that eliminates the above-mentioned obstacles and improves processing performance.

The present invention provides a direct memory access control device that includes an address register, a conversion circuit that converts address data stored in the address register, and an address buffer that outputs the address data converted by the conversion circuit to an address bus. , the conversion circuit comprises a temporary register for storing address conversion data, an accumulator for accumulating the data of the temporary register, and an adder for adding both the output of the accumulator and the data of the address register. A direct memory access control device characterized by having the following features:

Next, the present invention will be explained in detail using the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

Conventionally, as shown in FIG.
As shown in the figure, in the embodiment of the present invention, instead of the conventional incrementer/decrementer 2, a temporary register 4. It is characterized in that it has a configuration including a cumulative adder 5 and an adder 6.

Next, the operation of this block diagram will be explained. It is assumed that X pieces of conversion data are set in the temporary register 4. Further, a memory access start address ■ is set in the address register 1'. At the first timing T of the timing pulse generation circuit 7, the start address (2) is output as is to the address buffer 3'. At the same time, at the first output timing T1, the converted data ■ of the temporary register 4 is set as is to the output of the accumulator 5. At the next timing T2, the adder 6
The value of the address register 12 and the conversion data cage are added, and at timing T, the value of the address register 12 (2
M] Calculated value (X-4-Y) is set. Also, at timing T, the value of the temporary register 4 and the output ■ of the accumulator 5 are set to accumulator 5 again, and at timing T
3, the cumulative adder 5 adds f, :, (fL2X")
and the value ■ of the address register 1' are set as inputs to the adder 60. By repeating this operation, the address value 31 will continuously take on the following values.

(Y), (Y+X), (Y+2X), (Y+3X),・
...In other words, the above operation shows that the memory address can take consecutive values of X values.

Here, the value of ``Kin'' can be any value (sen), and operations can be performed in arbitrary X numbers. For example, if the value of ``Kin'' is set to 1, it is clear that the conventional function will be achieved.

Further, although an adder is used in this embodiment, it is clear that a subtraction operation can be similarly realized by adding a subtracter.

As described above, according to the present invention, high-speed processing can be realized for multiple memory accesses often used in digital signal processing, etc., and a versatile direct memory access control device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional memory address translation section, and FIG. 2 is a block diagram showing an embodiment of the present invention. In internal causes, l, 1! --- Address register, 2 --- Incrementer/decrementer, 3
．． 3'...Address buffer, 4...
Tempo 2 reregister, 5... Accumulator, 6...
. . . Adder, 7 . . . Timing pulse generation circuit, T+ + 'r, l 'r8. ...Time Jig Pulse. Figure 1 Figure 2

Claims (1)

[Claims] In a direct memory access control device comprising an address register, a conversion circuit that converts address data stored in the address register, and an address buffer that outputs the address data converted by the conversion circuit to an address bus, the conversion circuit has a temporary register for storing address conversion data, an accumulator for accumulating the data in the temporary register, and an adder for adding together both the output of the accumulator and the data in the address register. A direct memory access control device characterized by: