JPH04107731A - Multiplication circuit - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware and to simplify circuit configuration by preparing a multiplication result in a memory device, and providing a function to switch a multiplicand and a multiplier based on the comparison result of the size of the addresses of the multiplicand and the multiplier when comprising the address with the multiplicand and the multiplier. CONSTITUTION:A subtractor 1 performs the size comparison of the multiplicand 2 and the multiplier 3. Also, data selectors 5a,5b select the multiplicand 3 and either a high-order address 6 or a low-order address 7 by a borrow signal 4 by the result of substraction, and the content of the memory device 8 designated by the address is outputted as the multiplication result 9. In other words, the correspondence of the content of the memory device 8 and the address is performed by setting the number of cells to 1/2 by comparing the multiplicand 2 with the multiplier 3 by the subtractor 1 and switching the multiplicand 2 with the multiplier 3 at a data selector 5 when the multiplicand 2 is less than the multiplier 3. Thereby, it is possible to reduce the quantity of hardware and to simplify the circuit configuration.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a multiplication circuit.

[Conventional technology]

As shown in Fig. 2, the conventional multiplier circuit has a combinational circuit type multiplier circuit, which includes AND gates 21 to 36 for the number of multiplicand bits x the number of bits of the multiplier (16), and the multiplier bit minus one stage ( The configuration consisted of parallel adders 11 to 13 (3 stages).

[Problem to be solved by the invention]

The above-mentioned conventional multiplication circuit has the disadvantage that the AND gate and the adder require a large amount of hardware, making the circuit configuration complicated.

An object of the present invention is to eliminate such drawbacks, reduce the amount of hardware, and provide a multiplication circuit with a simple circuit configuration.

[Means to solve the problem]

The configuration of the multiplier circuit of the present invention includes a storage device that outputs the contents indicated by the addresses as a multiplication result, using the multiplicand and the multiplier as upper addresses and lower addresses when performing multiplication, and comparing the magnitude of the multiplicand and the multiplier. and a data selector that exchanges the upper address and the lower address using the output of the subtracter, and the output of the storage device is used as the multiplication output. The present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a multiplication circuit showing one embodiment of the present invention. In this figure, the subtracter l compares the magnitude of the multiplicand 2 and the multiplier 3. Further, the data selector 5 selects whether the multiplicand 2 and the multiplier 3 should be set to the upper address 6 or the lower address 7 by the borrow signal 4 resulting from the subtraction, and the contents of the storage device 8 specified by the address are The multiplication result 9 is output.

The correspondence between the contents of this storage device 8 and addresses is as follows when the multiplicand is fixed as an upper address and the multiplier is fixed as a lower address.
As shown in Table 1, even if the multiplicand and the multiplier are exchanged, the multiplication results are the same, so the subtracter 1 compares the multiplicand 2 and the multiplier 3, and if the multiplicand 2 is smaller than the multiplier 3, the data By exchanging multiplicand 2 and multiplier 3 in selector 5, the number of memory cells can be increased to 172 as shown in Table 2.

[Effects of the Invention] As explained above, the present invention has a function of preparing the multiplication result in the storage device and exchanging the multiplicand and the multiplier based on the result of comparing the magnitude of the multiplicand and the multiplier, thereby reducing the amount of hardware. This has the advantage that a multiplication circuit can be realized with a simple circuit configuration, and the processing speed does not depend on the number of bits of the multiplicand and the multiplier.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional 4-bit, 4-bit combination type multiplication circuit. 1... Subtractor, 2... Multiplicand, 3...
... Multiplier, 4 ... Borrow signal, 5 ...
...Data selector, 6... Upper address, 7
...Lower address 1,8...Storage device, 9...Multiplication result, 11-13...Adder, 21-36...・AND gate. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A storage device that uses a multiplicand and a multiplier when performing multiplication as an upper address and a lower address and outputs the contents indicated by the addresses as a multiplication result, a subtractor that compares the magnitude of the multiplicand and the multiplier, and the output of this subtractor. 1. A multiplication circuit comprising: a data selector for exchanging the upper address and the lower address; and an output of the storage device is used as a multiplication output.