KR100389082B1 - Multiplier using combination of adder and subtracter for rgb matrix generating algorithm of digital camera signal processing ic - Google Patents

Abstract

PURPOSE: A multiplier using combination of an adder and a subtracter for an RGB matrix generating algorithm of a digital camera signal processing IC is provided to simplify hardware by implementing a circuit for multiplying factors with the adder and the subtracter in case that the multiplying factor is fixed to a constant value. CONSTITUTION: The first shift register(DEF1) performs a 2-bit shift-right function by receiving data of upper 6 bits from 8-bit data signal input as lower 6 bits and receiving a logical 0 signal as upper 2 bits. The second shift register(DEF2) performs a 4-bit shift-right function by receiving the data of the upper 4 bits from the 8-bit data signal input as lower 4 bits and receiving the logical 0 signal as the upper 4 bits. The third shift register(DEF3) performs a 6-bit shift-right function by receiving the data of the upper 3 bits from the 8-bit data signal input as the lower 2 bits and receiving the logical 0 signal as the upper 6 bits. The subtracter(20) performs subtraction by receiving output of the first and the second shift register, and output a result. The adder(30) performs addition by receiving the output of the subtracter and the third shift register, and outputs the result.

Description

Multiplier using a combination of adder and subtractor

The present invention relates to a multiplier using a combination of an adder and a subtractor. More specifically, in order to hardware-implement an algorithm for generating an Algibi (hereinafter referred to as RGB) matrix in a signal processing integrated circuit for a conventional camera, When the multiplication factor is set to a constant value when the multiplication circuit is implemented, it relates to a multiplier using a combination of an adder and a subtractor which contributes to hardware simplification by implementing only the adder and the subtractor.

Hereinafter, an algorithm for generating an RGB matrix from a single CD in a conventional signal processing integrated circuit for a camera and a multiplier for realizing it in hardware will be described with reference to the accompanying drawings.

1 is a partial configuration diagram of a color filter array used in a single CD of a signal processing integrated circuit for a conventional camera.

2 is a block diagram of a multiplier for multiplying a conventional specific coefficient.

As shown in FIG. 1, a portion of a color filter array used in a single CD of a signal processing integrated circuit for a conventional camera is described.

In the horizontal direction, the first line is green (G), magenta (Mg), green (G), and magenta (Mg), and the second line is cyan, yellow (Ye), cyan (Cy) and yellow ( Ye), the third line is magenta (Mg), green (G), magenta (Mg), green (G), and the fourth line is cyan (Cy), yellow (Ye), cyan (Cy), The color filters are configured in the order of yellow (Ye).

In the vertical direction, the color filter signal S1 of the first and third lines and the color filter signal S2 of the second and fourth lines are divided.

First, an algorithm for generating an RGB matrix in a conventional camera signal processing integrated circuit will be described.

The CD signal, which is quantized by an external A / D converter, is input to the camera signal processing integrated circuit and then, through the built-in 2II delay line, 3 signals of H0D, H1D, and H2D The image signal of the line is synchronized and input to the luminance signal Y1 processing system and the chroma signal processing system.

At this time, the input signal calculates the difference components of S1 and S2 from the signals of three lines of H0D, H1D, and H2D to make Cr (2R-G) and Cb (| 2B-G |) repeated for each line. After passing through each low pass filter, the matrix circuit generates an R / GB signal. Here, Cr (2R-G) means a color component with a strong red component, and Cb (| 2B-G |) means a color component with a strong blue component.

Next, a (R-G) / (B-G) signal is generated to generate a color difference signal matrix (R-Y) (B-Y) signal through a Hue / Gain operation.

In the conventional matrix circuit, a signal processing method generates R, G, and B signals by the difference between S1 and S2, that is, the signal S1-S2. The order of signal processing is as follows.

Since the color filter array used in the single CD is scanned two lines at a time, the components of the S2 signal of the color filter array are represented by magenta and yellow (Mg) of the first and second lines, as expressed in Equation (1). + Ye) color, and the components of the S1 signal include green and cyan (G + Cy) colors.

As a result, Cr color having a strong red component is produced through the difference S2-S1 of the first S1 and S2 components (G, Cy, Mg, and Ye). The four dots G, Cy, Mg, and Ye constitute one pixel having a strong red component.

Next, as represented by the above expression (2), the components of the S1 signal of the color filter array are magenta and cyan (Mg + Cy) colors of the third and fourth lines, and the components of the S2 signal are green and yellow ( G + Ye) color is included, and C1 color with strong blue component is produced through calculation of S1-S2. The four dots Mg, Cy, G, and Ye also constitute one pixel having a strong blue component, and if the line including the pixel Cr of the red component is N, the previous line N-1 and the next line It is repeatedly arranged at (N + 1).

As represented by the above formula (3), the sum of the S1 signal and the S2 signal produces a luminance signal Y1 in which the three primary colors R, G, and B colors are combined.

That is, the signals of Cr, Cb, and Yl colors can be produced through the above-described process, and R, G, and R are expressed as shown in Equations (4), (5) and (6) using the matrix of these three signals. You can create a B signal.

As described above, the color reproducibility can be adjusted by generating the R, G, and B signals and gain control of the green (G) and luminance (Yl) signals.

Therefore, there is a process of multiplying the luminance signal Yl and the green color signal G by the coefficient 0.2 in the above-described process of generating the R, G, and B signals. Is to use a multiplier.

That is, as shown in FIG. 2, multiplication is performed by receiving an 8-bit color input signal IN <7: 0> as a multiplier and an 8-bit coefficient signal COEFFICIENT <7: 0> as a multiplier. Through the 8x8 multiplier 10 that outputs a 16-bit long color signal (OUT1 <15: 0>), and after multiplying, the upper 8 bits (OUT1 <15: 0>) of the 16-bit result (OUT1 <15: 0>) <15: 8>) takes only the effect of multiplying by 0.2.

Such a conventional technology has a problem in that the hardware becomes complicated because a multiplier must be used, which makes it difficult to construct a circuit or to design and control the multiplier.

Accordingly, an object of the present invention is to solve the above-described problems, and in hardware implementation of an algorithm for generating R, G, and B matrices in a conventional signal processing integrated circuit for cameras, When the multiplication factor is determined at a given value, the multiplier is implemented by combining an adder and a subtractor, thereby providing a multiplier using a combination of only an adder and a subtractor, which contributes to simplifying the hardware.

The configuration of the present invention for achieving the above object,

The first 6-bit data input of the 8-bit data signal input to the lower 6 bits of its own, and the logic '0' signal to the upper 2 bits of its own to perform a 2-bit shift right function and output the first A shift register;

A second shift register configured to output a 4-bit shift write function by receiving the upper 4 bits of the 8-bit data signal as its lower 4 bits and the logic '0' signal as its upper 4 bits; Wow;

A third shift register configured to perform a 6-bit shift write function by receiving upper 2 bits of data of the 8 bit data signal as its lower 2 bits and receiving a logic '0' signal as its upper 6 bits and outputting a 6 bit shift write function; Wow;

A subtractor for receiving the outputs of the first and second shift registers of the shift registers as a subtracted input and a subtracted input, respectively, performing subtraction and outputting a result;

And an adder for receiving the output of the subtractor and the output of the third shift register, respectively, as an addee input and a mantissa input, performing an addition and outputting a result.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention in detail.

3 is a block diagram of a multiplier using a combination of an adder and a subtractor according to an embodiment of the present invention.

As shown in FIG. 3, the constitution of a multiplier using a combination of an adder and a subtractor according to an embodiment of the present invention,

Among the 8-bit data signal inputs (IN <7: 0>), the upper 6-bit data (IN <7: 2>) is input to its lower 6 bits (DFF1 <5: 0>), and the logic '0' A de-flip flop DFF1 for performing a 2-bit shift write function by receiving the signal Vss as its upper two bits DFF1 (7: 6>) and outputting the same;

The upper 4 bits of the 8-bit data signal input IN <7: 0> 1 are input to their lower 4 bits DFF2 <3: 0>, and the logic ' A de- flip-flop DFF2 for performing a 4-bit shift write function by receiving the 0 'signal Vss as its upper 4 bits DFF2 <7: 4>;

The upper 2 bits of data (IN <7: 6>) of the 8-bit data signal inputs (IN <7: 0>) are input to its lower 2 bits (DFF3 <1: 0>), and logic '0. A de-flip-flop DFF3 for performing a 6-bit shift write function by receiving the 'signal Vss' as its upper 6 bits DFF3 <7: 2>;

A subtractor 20 which receives the outputs of the two flip-flops DFF1 and DFF2 from the flip-flops DFF1, DFF2, and DFF3 as the subtracted input A and the subtracted input B, respectively, and performs subtraction to output a result )Wow,

The adder 30 receives the output of the subtractor 20 and the output of the de-flip flop DFF3 as the singer input C and the mantissa input D, respectively, and performs an addition to output the result.

The operation of the multiplier using the combination of the adder and the subtractor according to the embodiment of the present invention made as described above is as follows.

First, an algorithm that can implement a multiplication of 0.2 implemented by a multiplier in combination with an adder and a subtractor will be described.

Where G is any signal to be processed.

As can be seen from equation (7) above, the multiplication of 0.2 can be approximated by the addition of the three terms in equation (7). Since the exponential power of 2 is a multiplication calculation, the multiplication coefficient of the ternary term may be implemented by using only an adder and a subtractor after shifting the bits of the signal to be processed (G) without using a multiplier.

Hereinafter, an operation of a shift register for multiplication processing of specific coefficients will be described with reference to the accompanying drawings.

(A), (b), (c), and (d) of FIG. 4 are operation diagrams of a shift register for multiplication processing of specific coefficients according to the present invention.

First, as shown in (a) and (b) of FIG. 4, the first shift register DFF1 selects the upper 6 bits (IN <7: 2>) of the 8-bit input signals IN <7: 0>. Takes the lower 6 bits of DFF1 <5: 0> and fills the remaining 2 bits of it (DFF1 <7: 6>) with the voltage Vss, which is a logic '0', This results in the same effect as multiplying the input by 1/4.

Next, as shown in (c) of FIG. 4, the second shift register DFF2 selects the upper four bits (IN <7: 4>) among the eight bits of the input signal IN <7: 0>. It takes the bits DFF2 <3: 0> and fills the remaining 4 bits of its own (DFF2 <7: 4>) with the voltage Vss, which is a logic '0', to give the effect of 4 bits of shift write. It has the same effect as multiplying the input value by 1/16.

Finally, as shown in (d) of FIG. 4, the third shift register DFF3 selects the upper two bits (IN <7: 6>) of the eight-bit input signal (IN <7: 0>) to its lower two. It takes the bits DFF3 <1: 0> and fills the remaining 6 bits of its own (DFF3 <7: 2>) with the voltage Vss, which is logic '0', to give the effect of 6 bits of shift write. It produces the same effect as multiplying the input by 1/64.

With respect to the outputs of the shift registers DFF1, DFF2, and DFF3 thus obtained, the output of the first shift register (DFF1 <7: 0>) is the subtracted input A of the subtractor, and the output of the second shift register (DFF2 <7). (0>) is sent to the subtractor input (B) of the subtractor to perform operations of 1/4 x IN <7: 0>-1/16 x IN <7: 0>.

Finally, the adder adds the result calculated by the subtractor and 1/64 × IN <7: 0>, so the final result is 1 // 4 × IN <7: 0>-1/16 × IN <7: 0> + 1/64 × IN <7: 0).

Therefore, the effects of the present invention operating as described above are implemented by using only an adder and a subtractor when the coefficient of multiplying the conventional circuit using the multiplier when implementing the circuit for supplying the coefficient is set to a constant value. To contribute to the simplicity of

1 is a partial configuration diagram of a color filter array used in a single CDC of a signal processing integrated circuit for a conventional camera.

2 is a block diagram of a multiplier for multiplying a conventional specific coefficient,

3 is a block diagram of a multiplier using a combination of an adder and a subtractor according to an embodiment of the present invention.

4A to 4D are operation diagrams of a -shift register for multiplication processing of specific coefficients according to the embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

G: Green Mg: Magenta (Complementary Green) Cy: Cyan (Complementary Red)

Ye: Yellow Vss: Voltage with logic '0'

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Claims (3)

It is composed of a circuit having a function of multiplying by a sum of coefficients of exponential power of 2 without using a multiplier in multiplying a specific coefficient, A circuit having a function of multiplying by the sum of the coefficients of the exponential power of 2, Among the 8-bit data signal inputs (IN <7: 0), the upper 6-bit data (IN <7: 2>) is input to its lower 6 bits (DFF1 <5: 0>) and the logic '0' signal A first shift register DFF1 for performing a 2-bit shift write function by receiving (Vss) as its upper two bits DFF1 <7: 6>; The upper 4 bits of the 8-bit data signal input IN <7: 0> are input as their lower 4 bits (DFF2 <2 <3: 0>) and the logic A second shift register DFF2 for performing a 4-bit shift write function by receiving a '0' signal Vss as its upper 4 bits DFF2 <7: 4> and outputting the 4-bit shift write function; The upper two bits of the data bits (IN <7: 0>) of the 8-bit data signal inputs (IN <7: 0>) are input to their lower two bits (DFF3 <1: 0>), and logic '0. A third shift register DFF3 for performing a 6-bit shift write function by receiving the 'signal Vss as its upper 6 bits DFF3 <7: 2>; A subtractor for receiving the outputs of the first and second shift registers DFF1 and DFF2 from the shift registers DFF1, DFF2, and DFF3 as the subtracted input A and the subtracted input B, respectively, performing subtraction, and outputting a result; 20; And an adder 30 which receives the output of the subtractor 20 and the output of the third shift register DFF3 as the singer input C and the mantissa input D, respectively, and performs an addition to output the result. Multiplier using a combination of an adder and a subtractor. The method of claim 1, The shift registers DFF1, DFF2, and DFF3 use the upper N bits (IN <7: 8-N>) of the 8-bit input signals IN <7: 0> to their lower N bits (DFF <N). -1: 0) and fill the remaining upper 8-N bits (DFF <7: N) with the voltage Vss, which is a logic '0', to effect the shift write 8-N bits, eventually A multiplier using a combination of an adder and a subtractor, which has the same effect as multiplying the input value by 1/2 ^(8-N) . The method of claim 2, The upper N bits (IN <7: 8-N>) of the 8-bit input signals IN <7: 0> are taken as their lower N bits (DFF <N-1: 0>), and the logic ' An adder and subtractor comprising a flip-flop characterized in that the circuit effecting the shift-right 8-N bits by filling the remaining V 8-N bits (DFF <7: N>) with a zero-voltage voltage (Vss) Multiplier using and combination.