JPS58124278A - Schottky gate field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain the field effect transistor characterized by excellent high frequency characteristics, high gate inverse withstand voltage, and an excellent yield rate, by providing a constitution wherein a gate electrode and an operating layer directly beneath the electrode are formed at the same position and said operating layer is held between resistance operating layers. CONSTITUTION:A first layer 27 and a second layer 28 for masking are formed on the surface of an semi-insulating substrate 21. Then, a resist pattern 28' is formed. With this as a mask, a Ti pattern of 27' is formed. With this as a mask, ion implantation is performed, and a high impurity layer, which imparts a specified pnch off voltage, i.e. an N<+> region 22', is formed. Then the resist pattern 28' is removed. With only the Ti pattern 27' as a mask, a second ion plantation with a specified dose amount is performed, and the operating layer 22'' is formed. Then an insulating film 26' is formed, the Ti mask 27' is removed, and an insulating film mask 26, whose polarity is inverted with respect to the mask 27', is obtained. With this as a mask, the operating layer 22'' with a specified amount of a dose amount is formed directly below the gate. The implanted element is activated by the annealing. Then, the source electrode, the drain electrode, and th gate electrode are formed at the specified positions on the N<+> layer 22' and the operating layer 22''', respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schottky gate field effect transistor that has good microwave characteristics and is easy to manufacture.

The present invention is not limited in any way to materials, and can be applied to a wide range of general semiconductor materials such as single-element semiconductors such as 81 or compound semiconductors. Among semiconductors, QaAs will be explained in Example 3.

The general structure of a conventional Schottky gate field effect transistor is QaAs, as illustrated in the cross-sectional view of FIG.
An n-type active layer 12 of uniform thickness is formed on the surface of a semi-insulating semiconductor substrate 11 by epitaxial growth or ion implantation.
After forming the active layer, the source electrode 13.1 and the rain electrode 14. A gate electrode 15 is formed thereon. It is known that in a Schottky gate field effect transistor having such a conventional structure, it is difficult to obtain good microwave characteristics, particularly good noise characteristics, because the gate-to-source resistance is large.

It is also inferior in high-speed switching operation. In order to improve the microwave characteristics, it is necessary to lower the gate-source resistance, and to achieve this purpose, as illustrated in FIG. A structure has been proposed in which the thickness of the active layer 12'' near the source electrode is increased while keeping the thickness at a desired value. After forming an operating layer with a uniform thickness, only the portion 12' that should be directly under the gate electrode 15 is thinned by etching or the like, and then the electrodes 13, 14 and 15 are formed.

However, in such a structure, the surface of the active layer is not flat, making it difficult to perform fine photolithography for electrode formation, and the etching control of the active layer 1 is required to be extremely precise, resulting in poor yield. It has the disadvantage that it becomes low.

Furthermore, in order to improve the high frequency characteristics of MESFETs, it is necessary to reduce the gate length as much as possible, which requires extremely fine precision machining in device fabrication. but,
In the conventional manufacturing method for the structure shown in FIG. 2, when forming the pattern of the gate electrode 15 in a resist, a step formed by the source electrode 13 and the drain electrode 14 is formed in the very vicinity of the gate pattern to prevent operation. Because of the presence in addition to the step difference in the region 12, the resolution of the photoresist pattern was lower than that on a flat surface, making it difficult to reliably form a short gate pattern of about 1 μm 5 -. In particular, in compound semiconductors such as QaAs, it is common practice to perform alloy treatment on the source electrode 13 and drain electrode 14 before forming the gate electrode 15 in order to reduce the contact resistance. When alloying is performed at a sufficiently high temperature and for a long time in order to reduce the resistance sufficiently, the source and drain electrode metals tend to aggregate, resulting in extremely large steps, which also deteriorates the resolution of the gate photoresist pattern. It is the cause.

Further, the gate electrode 5 is the source electrode 1 which has already been formed.
3 and the drain 14 with a positional accuracy of ±0.2 μm or less. Furthermore, the distance between the source electrode 3 and the gate electrode 15 is in the electrical characteristics of the MBSFET and directly affects the parasitic resistance and capacitance between the source and gate, so the distance between the two electrodes should be as small as possible and highly accurate. The above-mentioned positional accuracy is also required in terms of the distance between the electrodes. However, it is extremely difficult to form such a fine pattern with a high precision of 6 degrees using conventional techniques, resulting in a problem that the manufacturing yield is extremely low.

Another effective means of reducing the source resistance is to form a high impurity concentration n1 under the source electrode 13, but in order for this method to be sufficiently effective, it is necessary to The spacing must be sufficiently close. However, in conventional lathography technology, the n+ layer and the
1. It was difficult to place the electrodes close to each other within 1 μm.

Therefore, as detailed above, it has been desired to develop a method for effectively reducing the source resistance in order to be able to use the device at a higher frequency or to obtain a larger gain.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide a Schottky gate field effect transistor with good microwave characteristics and good yield.

The details of the present invention will be explained below with reference to Examples.

FIG. 3 is a cross-sectional view of a Schottky gate field effect transistor according to an embodiment of the present invention, in which 21 is a semi-insulating semiconductor substrate such as QaAs, 22 is an n-type active layer, 23 is a source electrode, and 24 is a drain. The electrode 25 is a Schottky gate electrode. As illustrated in FIG. 3, the field effect transistor of the present invention has a flat surface of the active layer, and the number of carriers per unit area of the active layer 22'' between the source and drain, that is, the number of sheet carriers, is The structure is larger than that of the gate electrode 25, and the gate electrode 25 is precisely located in the active layer 22+11 which determines the pinch-off voltage.
There is no direct overlap with .

In addition, the n+ layer 22' is 0.5 mm on both sides of the gate electrode.
Since it is formed in the vicinity of about .mu.m, the source resistance is reduced and it is characterized by good high frequency characteristics.

FIG. 41 is a cross-sectional view showing an example of a method for manufacturing the field effect transistor shown in FIG. 3.

First, as shown in FIG. 4(A), a first layer 27 for a mask is formed on the surface of a GaAs semi-insulating substrate 21. 2nd layer 2
form 8.

For example, a 0.6 .mu.m thick Ti layer is formed by vacuum evaporation as a first layer, and a 1 .mu.m thick photoresist layer is applied thereon as a second layer.

A resist pattern 28' is formed by ordinary photolithography as shown in Figure 4 (B), and using this as a mask, the Ti layer is etched to form a Ti pattern 27'. At this time, the Tl pattern is set back by a predetermined amount from the resist pattern 28' by controlling side etching. Using this two-layer structure pattern as a mask, ion implantation is performed to form a highly concentrated impurity layer, i.e., n+
A region 22' is formed. Next, resist pattern 28
' is removed by 0□ plasma or the like, and a second ion implantation is performed using only the Ti pattern 27' as a mask as shown in Figure 4 (q) to form the active layer 22''. Ion implantation is performed at a sufficiently large dose so that the number of carriers per unit area is sufficiently larger than that of the active layer 22+11, and at a high acceleration voltage so that a conductive layer can be formed at a deep position.This is a gate source. This is to reduce the resistance between the two electrodes, to prevent dielectric breakdown from occurring due to the voltage applied to the gate, and to prevent the gate capacitance from becoming excessive.An example of such implantation conditions , the implantation energy is 200Ke, the implantation amount is I
A value of 1013 doses/crn2 may be selected.

Next, as shown in Figure 4 (c), an insulating film 26' is applied to the entire surface of the sample.
form. For example, it is formed with an inorganic compound film such as 5I02 having a thickness of 0.4 μm by any method. Next, when the T1 mask 27' is removed, an insulating film mask 26 which is reversely reversed from the mask 27' is obtained as shown in FIG. 41 (5).

Using this as a mask, the active layer 22D directly below the gate
Form I. For example, the threshold voltage of a field effect transistor is 0. In order to realize l V , the ion implantation conditions are - for example, an implantation energy of 50 KeV and an implantation dose of 1
．． 5X10”dose/crn2 <However, the activation rate is 1
00%. ) is selected. As is clear from the value of the ion implantation dose, the total number of carriers in the active layer 22'' between the 01 layer 22' and the active layer 22/II is -10-. ' is approximately 7 times larger than the total number of carriers in the active layer 221N, so that the gate-source resistance is reduced to at least one-seventh compared to the case where the active layer 221N is uniformly formed.

On the other hand, the active layer 22'' is formed at a deep position and the carrier concentration at the surface is sufficiently low, so the increase in the dose is due to the decrease in the reverse breakdown voltage of the gate and the increase in the gate cuvacitance. stays in a small amount.

Next, the implanted element is activated by annealing, and n
By forming a source electrode 23, a drain electrode 24, and a gate electrode 25 at predetermined positions on the positive layer 2' and the active layer 221H, a transistor having the structure shown in FIG. 3(G) is completed. The operating layers 22'' and 22LH formed in contact with each other become continuous operating layers due to lateral scattering during ion implantation.

Next, other embodiments will be described. 4. In Figure 4), the insulating film pattern 26 is formed and the third active layer 22'+1 is formed.
4. After forming the active layer 2p, as shown in Figure σD,
A gate electrode 25 larger than tJJI is formed.

Using this gate electrode as a mask, the insulating film is etched by ClIF5 gas plasma to form the structure shown in 4. Figure (I). Thereafter, as shown in FIG. 4 (J), an ohmic electrode is formed to complete a transistor having the structure shown in FIG. 8 σ3). In this structure, the gate electrode 25 is connected to the active layer 22/
/I, which has the effect of ensuring that the gate electrode 25 is formed on 2zlH even if the alignment is slightly deviated.
Furthermore, since the insulating film can be etched and source/drain electrodes can be formed using the same electrode as a mask, highly accurate positioning or self-alignment can be used, and each electrode can be brought close to each other.

In the present invention, the essential element is to selectively form three types of impurity layers using a two-layer structure mask and a pattern obtained by reversing the mask. As long as this is satisfied, the materials 27, 28, and 26 used for the mask are not limited to the examples, and 27 can be selectively etched with respect to 28, and 27 can be selectively removed with respect to 27. Any combination is possible as long as it satisfies the requirements that 27 can be selectively removed with respect to 26. For example, 27 as 2
When using a resin film such as photoresist or polyimide different from 8, 26 is S i 3N.

S+02, A~03. Inorganic compounds such as ZrO,
Furthermore, Aβ.

It is possible to form a metal film such as T i , MO, W, etc. and insulate it by, for example, an anodic oxidation method.

In addition, as 27, the above inorganic compound film is applied along with 26.
It is also possible to select 6.

Further, the crystal is not limited to GaAs, and the present invention can be applied to all materials that can form a Schottky gate field effect transistor.

As is clear from the above explanation, in the present invention, three independent impurity layers and gate, source, and drain electrodes are formed based on the same pattern, so their mutual positional relationship is highly accurate, and especially The gate electrode and the operating layer directly below are
It is characterized in that it is formed at the same position, and that it has a structure in which the above-mentioned active layer is sandwiched between low-resistance active layers.

13- From this, it has good high frequency characteristics, high gate reverse breakdown voltage,
In addition, a Schottky gate field effect transistor with good yield can be realized through a simpler process than in the past.

[Brief explanation of drawings]

Figures 1 and 2 are cross-sectional views of the conventional example, Figure 3 (A), β)
4 is a cross-sectional view of one embodiment of the present invention, and FIGS. 21... Semi-insulating semiconductor substrate, 22... Operating layer, 2
2'...First part of the active layer, 22''...Second part of the active layer, z2+++...Third part of the active layer, 23...Source electrode, 24...Drain Electrode, 25...Gate electrode, 26.26'...Insulating film and its pattern, 27.27'...Mask pattern (lower layer) 28.28'...Mask pattern (
upper layer, e.g. photoresist) -1,4,- to -1351-

Claims (3)

[Claims] (1) A Schottky gate field effect transistor comprising a semi-insulating semiconductor substrate, an active layer formed on the surface of the semiconductor substrate, and a source electrode, a jockey electrode, and a train electrode formed on the active layer; an active layer having an impurity concentration distribution in the depth direction that provides a predetermined pinch-off voltage, and a first portion formed under the gate electrode; and a first portion formed on both sides of the first portion in contact with the first portion. The impurity concentration near the surface of the second active layer' is lower than the impurity concentration near the surface of the first active layer, and The number of impurities per unit area is larger than the number of impurities per unit area of the first active layer, and the doping is formed in a part of the second part and has a high impurity concentration. The gate electrode is formed with an insulating film having an opening at the same position as the first part and has an electrode length equal to or longer than the first part, and the Schottky junction is formed at the first part. A Schottky gate field effect transistor, characterized in that the Schottky gate field effect transistor is formed only in the insulating film opening directly above the part. (2) A step of forming a two-layer mask in which the lower layer mask is smaller than the upper layer mask formed on the surface of the semi-insulating substrate, a step of forming a high concentration impurity layer using this as a mask, and an upper layer mask. a step of forming a deep active layer or a diffusion layer using only the lower layer mask, a step of forming an insulating film pattern that is the reverse of the lower layer mask, and a step of forming a shallow active layer using the insulating film pattern as a mask. Alternatively, a method for manufacturing a Schottky gate field effect transistor, comprising a step of forming a diffusion layer, then a step of forming a source electrode and a drain electrode, and finally a step of forming a gate electrode. (3) A step of forming a two-layered mask on the surface of a semi-insulating substrate in which the lower layer mask is smaller than the upper layer mask, a step of forming a high concentration impurity layer also as a mask, and a step of forming the upper layer mask. A step of removing the mask, a step of forming a deep active layer or a diffusion layer using only the lower layer mask, a step of forming an insulating film that is the reverse of the lower layer mask, and a step of forming a shallow active layer or a diffusion layer using the insulating film as a mask. a step of forming a diffusion layer, and a step of subsequently forming a gate electrode;
1. A method of manufacturing a Schottky gate field effect transistor, comprising the steps of etching the insulating film using the gate electrode as a mask, and finally forming a source electrode and a drain electrode.