JPS58123763A - Protective circuit for gate of semiconductor integrated circuit - Google Patents
Protective circuit for gate of semiconductor integrated circuitInfo
- Publication number
- JPS58123763A JPS58123763A JP57005448A JP544882A JPS58123763A JP S58123763 A JPS58123763 A JP S58123763A JP 57005448 A JP57005448 A JP 57005448A JP 544882 A JP544882 A JP 544882A JP S58123763 A JPS58123763 A JP S58123763A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate
- protective
- circuit
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 28
- 229920005591 polysilicon Polymers 0.000 abstract description 28
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 230000007257 malfunction Effects 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 230000005669 field effect Effects 0.000 description 6
- 230000002238 attenuated effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 210000000988 bone and bone Anatomy 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000283690 Bos taurus Species 0.000 description 1
- 101150111878 Vegfd gene Proteins 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Amplifiers (AREA)
- Protection Of Static Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発＃Ｊは、外部からの入力端子となるボンデイン＼グ
パツドを介して印加される高電圧サージに対するゲート
保護を確実にするとともに高周波サージによる回路の誤
動作防止會確笑にした半導体集積回路、とくに絶縁ゲー
ト型電界効果絶縁ゲート型電界効果トランジスタは絶縁
膜に酸化シリコン（８ｊＯ，）などを用い、そのゲート
構造が金属（ｍｅｔａｌ）−撤化物（Ｏｘｉｄｅ）−半
導体（８ｅｍムｃｏｎｄｕｃｔ・ｒ）の組合せであるこ
とからＭＯ８ＦｉｉＴ とも呼ばれ、高密度集積化が可
能であるために広く用いられている。この絶縁ゲート型
電界効果トランジスタのゲート酸化膜は比較的薄いため
にポンディングパッドなど管介して外部から為電圧プー
ツが印加されることがあり、それによってゲートが絶縁
破壊さｎたシ、高周波サージの場合はシリコン基板上に
形成した回路が誤動作したりすることがある。[Detailed Description of the Invention] This invention #J ensures gate protection against high voltage surges applied through the bonding pad, which serves as an input terminal from the outside, and prevents malfunction of the circuit due to high frequency surges. Semiconductor integrated circuits, especially insulated gate field effect insulated gate field effect transistors, use silicon oxide (8jO, It is also called MO8FiiT because it is a combination of conductive and conductive materials, and is widely used because it allows high-density integration. Since the gate oxide film of this insulated gate field effect transistor is relatively thin, voltage may be applied from the outside through a tube such as a bonding pad, which may cause dielectric breakdown of the gate and cause high-frequency surges. In this case, the circuit formed on the silicon substrate may malfunction.
このための保護対策としてトランジスタの入力１ＩＩｌ
ｃゲ一ト保護回路を設は為方法が知らｊ、ている０第１
図は従来知られているゲート保護回路の一例で、印は平
面図、←）は印のＡ−Ａ線断圓図であゐ０図において１
里はトランジスタが形成場れている半導体基板のチップ
、２は外部からの入力端子となるアルミニウムなどのホ
ンテインクパッド％Ｓはポリシリコン保護抵抗、４は保
謄抵抗３の一端とポンディングパッド３とコンタクト％
ｌＩ＃ｉ保護抵抗８の他端と配線・とのコンタクト、テ
は２つのダイオードＤ、 、 Ｄ。As a protective measure for this, the transistor input 1IIl
I don't know how to set up the gate protection circuit.
The figure shows an example of a conventionally known gate protection circuit.
2 is a semiconductor substrate chip on which a transistor is formed, 2 is a real ink pad made of aluminum or the like that serves as an input terminal from the outside, %S is a polysilicon protection resistor, 4 is one end of the protection resistor 3 and the bonding pad 3 and contact%
lI#i The other end of the protective resistor 8 is in contact with the wiring, and the contacts are two diodes D, , D.
から成る絶縁ゲート璽電界効果トランジスター保饅用の
保護素子群であり、これらのポンディングパッド２％保
膜抵抗ｓＦｉテップｌ上に形成した均一な厚さのフィー
ルド酸化！Ｉｉ會上に形成されている。A group of protective elements for protecting insulated gate field effect transistors consisting of a uniformly thick field oxidation film formed on these bonding pads with 2% film resistance sFi. It is formed on the Ii meeting.
このようなゲート保１１回路を設ければ、ポンディング
パッド３から入力する電圧サージを保護抵抗Ｓによシ減
衰嘔せることができるので、トランジスターのゲート破
壊やシリコン基板テップ１上の回路の誤動作を防止する
ことができる◇高電圧サージに対しては保護抵抗の抵抗
値を大きくしてゲート保護管図っていゐが、保護抵抗の
値會あｔシ大きくす士六フィールド酸化膜９が絶縁破壊
を起すおそれがある友めにせいぜい数にΩ程度のものし
か使用していない。If such a gate protection circuit 11 is provided, the voltage surge input from the bonding pad 3 can be attenuated by the protection resistor S, thereby preventing gate breakdown of the transistor or malfunction of the circuit on the silicon substrate step 1. ◇For high voltage surges, the resistance value of the protective resistor is increased to provide a gate protection tube, but if the value of the protective resistor is increased, the dielectric breakdown of the field oxide film 9 may occur. I only use a few ohms at most for my friends who are at risk of causing this.
ところで、自動車などでは電圧が歇１Ｇ０ボルトで振動
周波数が数ＭＨｚから数１０ＭＨｚのサージが発生する
ことがあるが、このような高電圧、高周波のサージが上
記のような保護回路に入力す；ｂ七保護素子群７のダイ
オードＤ、やり。By the way, surges with a voltage of 1G0 volts and a vibration frequency of several MHz to several tens of MHz may occur in automobiles, etc., and such high voltage, high frequency surges input to the protection circuit as described above;b Diode D of seven protection element group 7, spear.
を介してサージ電流が電ｍラインやアースラインに流れ
込むため、電源ラインやアースライン（牛導体基板やＰ
ウェルを含む）のインピーダンスによｉサージが出力に
リークし次ｆｉ、 ＰＮ接合からサージが出力にリーク
したシして基板上の回路の誤動作をまねくことがある。Because surge current flows into the power line and ground line through the
A surge leaks to the output due to the impedance of the well (including the well), and then a surge leaks to the output from the PN junction, which may cause circuits on the board to malfunction.
本発明け、上記の点ｋかんがみてなされたもので、入力
端子となるポンディングパッドと保護すべきトランジス
タのゲートに接続される保験素子との間に電流制限用保
護抵抗を接続して成る牛導体集積回路のゲート保護回路
において、ポンディングパッド１介して印加される高電
圧サージに対するゲニト保Ｓを確実にするとともに高周
波サージによ１回路の誤動作防止を確冥にする九め、保
護抵抗の値ＳＯＫΩ〜！１００ＫΩとし且つこａｍｍ低
抵抗入力端子の設置部位の酸化膜の厚＠を回路配線部分
のいわゆるフィールドーイビ膜の厚さよ夕厚くしたもの
である。The present invention has been made in consideration of the above point k, and is comprised of a current limiting protection resistor connected between a bonding pad serving as an input terminal and a protection element connected to the gate of a transistor to be protected. In the gate protection circuit of the conductor integrated circuit, a protective resistor is used to ensure the protection against high voltage surges applied through the bonding pad 1 and to ensure that the circuit does not malfunction due to high frequency surges. The value of SOKΩ~! The resistance is set to 100KΩ, and the thickness of the oxide film at the location where the amm low resistance input terminal is installed is made thicker than the thickness of the so-called field-evid film at the circuit wiring portion.
以下本発明を図面に基づいて説明する〇第２図は本発明
によるゲート保護回路の一笑施例を示しており、９）は
平面図、（ロ）ＦｉＧｆ）のＢ−ＢｗｒｄＩＪ図で１図
中第五図と同じ参照数字は同じ構成部分管示している・
アル建エクムのポンディングパッド２にゲート保護回路
の一部であるポリシリコン保護抵抗Ｓをコンタクト４９
介して接続し、このポンディングパッド３とポリシリコ
ン保護抵抗３とから成る回路領域（図中破巌で囲んで示
した領域）は配線・や保護素子群７あるいけトランジス
タ廊などの他の回路領域の酸化膜すなわちフィールド酸
化膜・より厚い酸化１［１Ｇの上に設置されている０フ
イールド酸化膜９の厚さは通常のプロセスで作られる酸
化膜の厚さであるＯ９・〜＆Ｉ声ｍ ｍｍであるのに対
し、この厚い酸化膜１・ＯＪ１名はＬ・〜１、＄ＪＩｍ
程度である。これは車両で使用てれるような場合は士数
１００Ｖの高周波サージに耐える必要があるためである
０ポリシリコン保護抵抗１の他端はコンタク）Ｉを介し
て少なくとも１個の保護素子より成る保護素子群１に接
続され、この保護素子群１はトランジスタ１のゲートに
接続されている◎
次に本発明によゐゲート保＋＋Ｕａ路の製造工程を＃Ｉ
３図を参照して簡単に説明する。The present invention will be explained below based on the drawings. 〇 Figure 2 shows an example of the gate protection circuit according to the present invention, 9) is a plan view, and (b) FiGf) is a B-BwrdIJ diagram in Figure 1. The same reference numerals as in Figure 5 indicate the same component parts.
Contact 49 with the polysilicon protection resistor S, which is part of the gate protection circuit, to the bonding pad 2 of Alken Ekumu.
The circuit area consisting of the bonding pad 3 and the polysilicon protection resistor 3 (the area surrounded by a broken circle in the figure) is connected to other circuits such as wiring, the protection element group 7, and the transistor corridor. The thickness of the 0 field oxide film 9 placed on top of the oxide film, i.e., the field oxide film, is the thickness of the oxide film made by a normal process. mm, whereas this thick oxide film 1・OJ1 name is L・~1, $JIm
That's about it. This is because when used in a vehicle, it is necessary to withstand high-frequency surges of 100V.The other end of the polysilicon protection resistor 1 is a contact, and the protection consists of at least one protection element via I. The protective element group 1 is connected to the gate of the transistor 1.Next, the manufacturing process of the gate protection circuit according to the present invention is #I.
This will be briefly explained with reference to FIG.
Ｐ形シリコン基板１１Ｋ”窒化ｉ１１！ｔ−被着し、窓
！ｓを開孔する◎脅化膜１雪の被着に際して窒化膜！ｓ
Ｏ被着力を増すために窒化膜１２とシリコン基板１１と
の間にうすい酸化膜（厚さ約１・１）ＯＡｔで）！−設
けてもよい（同図ビ）参照）。P-type silicon substrate 11K” nitride i11!t- is deposited, and a window!s is opened.
To increase O adhesion, a thin oxide film (about 1.1 thick OAt) is placed between the nitride film 12 and the silicon substrate 11! - may be provided (see figure B)).
窓開死後熱酸化を行ない、酸化膜１４を１．８〜ＬＯｐ
ｍの厚＠に成長させる（同図−）参照）０以後は通常ｅ
Ｄ ＬＯＣＯ８（Ｌｏｃａｌ ０ｘ１ｄムＺｉｔｉｏｎ
ｏｆ８１１ｉｃｏｎ）シリーングートエ穆でＭ０８ト
ランジスタを形成してゆくのであるが、先ずＦＥＴ
を形成すゐ部分に窒化Ｈｓｓ＠形成してマスクしく同図
（ハ）参照）、酸化膜層を成長させ厚さの異なる酸化膜
１４ｍと酸化膜１４ｂと管形成し（同図に）参照）、さ
ら＃ｃ音化膜１Ｓ會除去したあとにゲート酸化膜ｌ５１
−形成すゐ（同図（へ）参照）。ゲート酸化膜１６管形
成した後、ポリシリコン９１７ｔ−被着し、ゲートと保
護抵抗の／＜ターンを形成しく同図（へ）参照）％窓１
ｓｔ−通してソースおよびドレイン！９を形成する（同
図（ト）参照）。ソースとドレイン１會の形成時にゲー
トとなるポリシリコンのドーピングを行なって奄よいが
、このときポリシリコン保護抵抗のパターンはイオン注
入で霞度コントロールし食後ＣＶＤ−化シリコン（８ｉ
０．）膜などで！スフしておく必要がある。その後は通
例のようにＣＶＤ酸化シリプンなどの層関絶縁膜會被着
さゼ、アルミニウムポンプイングツぐラド２０１に形成
し、コンタクト穴をあけ、アル建エウ五′配線を施し１
次いで表面保１１８１２１１被着しポンディングパッド
２０の穴あけ１行な、う（同図（ホ）参照）。厚い酸化
膜１４厘の最終的な厚さは途中のエツチング工程により
ＬＯ〜ＬＩＪＩｍ程度になっている０
第４図はこのようにして製造し良ゲート保護回路が適用
さ−れるトランジスタ回路で第２図と同じ参照数字は同
じ構成部分を示している。この回路において、保護素子
群１け、拡散抵抗２２と３つのダイオード２Ｂ、２４．
２ｓとにより構成されており％！６は電源ライン、！？
Ｆ！ドレイン出力である０
車両では電圧が数１００ボルト程度で振動周波数が数Ｍ
Ｈｚから数１・ＭＨｚＯ９−ジ８が入力端子すなわちポ
ンディングパッド２Ｖｃ加えられることがある０そのた
めにポリシリコン保饅抵抗ｓＯ抵抗値を充分大きくする
ことＫより。After opening the window, thermal oxidation is performed to reduce the oxide film 14 to 1.8~LOp.
Grow to a thickness of m (see figure -)) Normally e after 0
D LOCO8 (Local 0x1dmuzition
of811icon) The M08 transistor will be formed using the silicone transistor, but first the FET
Nitride Hss@ is formed on the portion where nitride Hss@ is formed as a mask (see figure (c))), and an oxide film layer is grown to form a tube with oxide films 14m and 14b of different thicknesses (see figure (c)). , Furthermore, after removing the #c sound conversion film 1S, the gate oxide film 151 is removed.
-Formation Sui (see figure (f)). After forming the gate oxide film 16, polysilicon 917t is deposited to form the /< turns of the gate and protection resistor.
source and drain through st-! 9 (see figure (g)). It is possible to dope the polysilicon that will become the gate when forming the source and drain 1 groups, but at this time, the pattern of the polysilicon protection resistor is controlled by ion implantation to control the degree of haze, and after the process, the CVD-treated silicon (8i
0. ) with membranes and more! You need to clean it up. After that, as usual, a layered insulating film such as CVD silicon oxide is deposited, formed on aluminum pumping board 201, contact holes are made, and aluminum wiring is applied.
Next, apply the surface adhesive 1181211 and make one row of holes for the bonding pad 20 (see figure (E)). The final thickness of the thick oxide film 14 is approximately LO to LIJIm due to the etching process during the process. Figure 4 shows the second transistor circuit manufactured in this way and to which a good gate protection circuit is applied. The same reference numerals as in the figures indicate the same components. In this circuit, one protective element group, a diffused resistor 22, three diodes 2B, 24.
It is composed of 2s and %! 6 is the power line! ?
F! The drain output is 0. In a vehicle, the voltage is about several hundred volts and the vibration frequency is several M.
Hz to several 1 MHz O9 - 8 may be applied to the input terminal, that is, the bonding pad 2Vc. Therefore, the resistance value of the polysilicon protection resistor sO must be made sufficiently large.
拡散抵抗３８と分布容量とにより作られる時定数管サー
ジの振動周期より大きくすればドレイン出力３丁におけ
るサージ、Ｏ漏れの振幅を小さくできるとともに保護抵
抗畠の抵抗値を大きくすることによりダイオード！８．
！４ｔ−通してｉｔ
電源ライン３・へ流れ込むサージ電源を制限し。By increasing the vibration period of the time constant tube surge created by the diffused resistor 38 and the distributed capacitance, the amplitude of the surge and O leakage at the three drain outputs can be reduced, and by increasing the resistance value of the protective resistor 38, the diode! 8.
! 4T - Limits the surge power flowing into the IT power line 3.
電源ライン３６を通って最終出力端へ漏れるサージを抑
え、誤動作を防ぐことができる０第４図はこのサージが
漏れる場合の経路を示している。第Ｓ図はこのときのポ
リシリコン保護抵抗３の抵抗値に対するドレイン出力２
１へのサージの漏れ電圧の実験結果を示す０このナージ
漏れ電圧ａの値が１ｖ以上あるとシリコン基板上の回路
の誤動作の原因となって望ましくない。Surges leaking through the power supply line 36 to the final output terminal can be suppressed and malfunctions can be prevented. FIG. 4 shows the path in the case where this surge leaks. Figure S shows the drain output 2 versus the resistance value of the polysilicon protection resistor 3 at this time.
1 shows the experimental results of the surge leakage voltage a to 0. If the value of the surge leakage voltage a is 1 V or more, it is undesirable because it causes malfunction of the circuit on the silicon substrate.
またポリシリコン保護抵抗３の抵抗値が大きすぎるとポ
ンディングパッド雪下の酸化膜すなわち厚い酸化膜（集
２図の１０または第３図の１４ｍで示される部分）の容
量が効き、この容量を通してサージが基板に流れ込むの
でやは〕好ましくない０
第６図は本発明によるゲート保護回路のポリシリコン保
護抵抗の形状の一例管示してシフ。Furthermore, if the resistance value of the polysilicon protection resistor 3 is too large, the capacitance of the oxide film under the bonding pad, that is, the thick oxide film (the part indicated by 10 in Figure 2 or 14m in Figure 3) becomes effective, and through this capacitance, This is not desirable because surges flow into the substrate. FIG. 6 shows an example of the shape of the polysilicon protection resistor of the gate protection circuit according to the present invention.
破線Ｃで囲んだ部分は入力端における電界の集中で絶縁
破壊が起らないように転を広くしである。ポリシリコン
は厚さが３５６ＯＡで、ボロンもしくけりンを約１０１
４ａ＋４イオン注入することにより、シート抵抗はｓＯ
ＯΩ／口〜ＩＫＧ／口となり、幅は大電流時の熱溶断を
考慮してＳμｍとなっているがこのと會の抵抗値がＢＯ
ＫΩ〜ｓＯ・にΩで嵐好な結果が得られた。The portion surrounded by the broken line C has a wide roll so that dielectric breakdown does not occur due to concentration of electric field at the input end. The polysilicon is 356 OA thick and contains about 101 boron or phosphorus.
By implanting 4a+4 ions, the sheet resistance becomes sO
The width is Sμm in consideration of thermal breakage at the time of large current, but the resistance value of the meeting is BO.
Good results were obtained with Ω from KΩ to sO·.
上記実施例ではシリコンゲートのＭＯＢ ＦＫＴ（Ｐ
−ＭＯＢ、Ｎ−ＭＯ８％Ｃ−ＭＯ８％）［ついて税明し
良が、アル電ニウムゲート０Ｍ０８ Ｆ、ＢＴ につ
いてもポリシリコン保護抵抗の被着工程全追加すること
により容易に実現でき同じ効果が得られる０本発明ｔア
ル建ニウムゲートのＣ−ＭＯＢ製造工程に適用する場合
の製造工程の概略を第７図に示す。In the above embodiment, a silicon gate MOB FKT (P
-MOB, N-MO8%C-MO8%) FIG. 7 shows an outline of the manufacturing process when applied to the C-MOB manufacturing process of the obtained aluminum gate according to the present invention.
（支）Ｎ形シリコン基板３・の全面に窒化膜（Ｓ ｉ
ＡＮ４）１１を成長畜ぜ先後５ｅａｓ図の領域１３に当
る部分の窒化膜を除去する０
（→ シリコン基板３・の表面に熱配化膜（８１０ｍ）
８２ｔＬ虐〜１０μｍ成長名ぜ（穿化膜３１に被われ友
部分は成長しない）窒化膜を全て除去するＯ
ｅウ 窒化膜除去後さらに！！化ｌｉｋ成長させ。(Support) A nitride film (Si
AN4) After growing 11, remove the nitride film in the area 13 in the 5eas diagram.
82tL ~ 10μm growth name (covered by perforation film 31 and no growth) Remove all the nitride film OeU After removing the nitride film! ! Make it grow.
Ｎ−ＭＯＢ ＦＢＴの基板となるＰウェル３３を形成
するｔめ、ボーン０を拡散する０
に） Ｐ−ＭＯ８ＦＥＴのソース、ドレインｓ４および
保縛ダイオード＄６を形成する次めボ葺ンを拡散する＠
（ホ） Ｎ−ＭＯ８ＰＦＩＴのソース、ドレイン管形成
するためりン０を拡散する〇
（へ）入力保護抵抗となるポリシリコン抵抗３６をＣＶ
Ｄ で形成し、イオン注入にょｐ抵抗値制御を行なう。Form the P-well 33 that will be the substrate of the N-MOB FBT. Diffusion of the bone 0.) Diffusion of the bone 0 to form the source, drain s4 and bonding diode $6 of the P-MO8FET. @ (e) Diffuse phosphorus 0 to form the source and drain tubes of N-MO8PFIT 〇 (e) CV the polysilicon resistor 36 that will become the input protection resistor
The resistance value is controlled by ion implantation.
（ト） ゲート酸化１［ｓ１管成長させ％ざらにコン
タクト部の酸化膜を除去する。(g) Gate oxidation 1 [Grow s1 tube and roughly remove the oxide film on the contact portion.
■ アルオニウム３８を蒸着し配ｍｅ行う。■ Evaporate and arrange Alonium 38.
（す） ＰＳＱ（リンガラス）をＣＶＤで形成し表面
保護Ｍ３静を形成する。(S) Form PSQ (phosphorus glass) by CVD to form surface protection M3.
本発明において、上でポリシリコン保護抵抗の抵抗値を
高くすることｔ述べたが、抵抗値が高くなると抵抗の両
端間の電圧が上昇する良め自動車のような厳しい環境下
で使用される半導、１：
体装置１おいてはポンディングパッドｌ Ｖ ｊｊ ：
ｙン基板との間の放電対策同様にポリシリコン保護抵抗
とシリコン基板との放電対策が必要になり、そのような
対策をすることによｐ高周波サージに対する牛導値装置
の耐性が向上する。In the present invention, it was mentioned above that the resistance value of the polysilicon protection resistor is increased, but as the resistance value increases, the voltage across the resistor increases. 1: In the body device 1, the pounding pad l V jj :
Similarly to the measures against electric discharge between the polysilicon protective resistor and the silicon substrate, measures against electric discharge between the polysilicon protective resistor and the silicon substrate are required, and by taking such measures, the resistance of the cattle guide value device to p high frequency surges is improved.
第一図は実験によ為酸化膜（酸化シリコン）厚と高周波
サージ耐圧との関係を示す。この図から、たとえば±４
００Ｖの耐圧が必要な場合には酸化膜厚をＬ・〜Ｌ丁μ
ｍＫすればよいことがわかる０またこの図から高周波サ
ージ耐圧は静電的なもＯよりかｅ６悪いことがわかる。Figure 1 shows the relationship between the thickness of the oxide film (silicon oxide) and the high-frequency surge withstand voltage based on experiments. From this figure, for example, ±4
If a withstand voltage of 00V is required, the oxide film thickness should be
It can be seen that mK is sufficient.0 Also, from this figure, it can be seen that the high frequency surge withstand voltage is e6 worse than O in terms of electrostatics.
本発明にかけるように、高周波サージが印加されるポン
ディングパッドおよびポリシリコン保ｍ抵抗部分の酸化
膜の厚−ｇｔ−充分厚くすれば高電圧サージが印加され
て４酸化膜の絶縁破壊による故障を起すことなく、高周
波サージがシリフン基板から絶縁されたポリシリコン保
護抵抗に印加式れても充分減衰した後にポリシリコン保
護紙ＦＬＫ襞続てれた保ｓｉｓ子群のフラングダイオー
ドを通してシリコン基板すなわち電源う１：□
インに印加されデージ４充分減衰しているために回路の
誤動作を起すことはない＠
以上説明ｌ−友ように１本発明においては、入力端子と
ゲート保護素子群との間に接続されたポリシリコン保護
抵抗の抵抗値′ｔＳＯＫΩ〜１００ＫＱとし且つ入力端
子となるポンディングパッドとポリシリコン保護抵抗の
設置場れる部分の酸化膜の厚さ會他の回路形成部分の酸
化膜すなわちフィールド酸化膜より厚（したので、入力
端子に高周波サージ電圧が印加されてもゲートの絶縁破
壊や基板上の回路の誤動作を起すことなく、高抵抗値を
有するポリシリ；ン保護抵抗によりサージ電圧を減衰す
ることができる。According to the present invention, if the thickness of the oxide film on the bonding pad and the polysilicon holding resistor part to which high frequency surges are applied - gt - is made sufficiently thick, high voltage surges will be applied and failures will occur due to dielectric breakdown of the 4 oxide film. Even if a high-frequency surge is applied to the polysilicon protection resistor insulated from the silicon substrate, it is attenuated sufficiently and then passed through the flang diodes of the protection group connected to the polysilicon protection paper FLK folds to the silicon substrate, i.e. Power supply 1: □ Since the level 4 applied to the input terminal is sufficiently attenuated, it will not cause malfunction of the circuit. The resistance value of the polysilicon protective resistor connected to the input terminal should be set to 100 KQ, and the thickness of the oxide film on the bonding pad that becomes the input terminal and the area where the polysilicon protective resistor is installed, and the oxide film on other circuit forming parts, i.e. The film is thicker than the field oxide film, so even if high-frequency surge voltage is applied to the input terminal, it will not cause dielectric breakdown of the gate or malfunction of the circuit on the board, and the polysilicon protection resistor with high resistance value can absorb the surge voltage. can be attenuated.
第１図は従来の絶縁グー）Ｉｔ電界効果トランジスタの
ゲート保ｓｉａ路を示しておシ、（へ）け同保鰻回路め
平面図、（ロ）はに）のＡ−ＡＩＦｒ＠図、第２図は本
発明によゐゲート保１１回路のゲート保護回路を示して
お夛、（イ）は同僚ａｍ路の平頁図、←）Ｆｉ（（イ）
ＯＢ−Ｂ断面図、第１図は本発明によるゲート保ｇｔａ
路を有する半導体回路の製造工程會（ハ）〜■で示す図
、第４図は本発明によるゲート保Ｓ回路の電気回路％第
Ｓ図はポリシリコン保護抵抗の抵抗値とナージＯ漏れ値
との関係管示す図、ｆｓ−図は本発ｆｌＪ４によゐゲー
ト保護回路のポリシリ；ン保護抵抗の配置形状の一例、
第７Ｅは本発１ｌｊＩＫよるゲート保護回路１有するア
ルオニウムゲー）ＯＣ−ＭＯ８製造工程を（６）〜（’
Ｊ）で示す図、第８図は酸化膜厚と高周ｔｌＩブージ耐
圧との関係管示す図であろ０
！−チップ、鵞−ポンディングパッド、３・・・ポリシ
リ；ン保護抵抗、４．ｓ−コンタクト、・−配線、１−
保護素子群、Ｓ−・電界効果トランジスタ、■・軸フィ
ールド酸化１［，１０，１４−酸化膜、１１−Ｐ形シリ
フン基板、１２゜ｌｌ−１ｌ化膜、１３，１＠−・・窓
、１＠−１’−）酸化膜、１７−ポリシリ；ン膜、ｌ嘗
・・・ソース。
ドレイン、鵞Ｏ−アルン二つムボンデイングパッド％２
五−表面保嚢膜、１３・−拡散抵抗、！ｌ、！４．雪暴
・−ダイオード
脣 許 輿 願 人 日童自動車株式会社代雇人弁瀧
士 鈴 木 弘 男
第
（イ）
１ｇ１
１４ａ １４ｂ
寸。Figure 1 shows the gate protection circuit of a conventional insulation field effect transistor. Figure 2 shows the gate protection circuit of the gate protection 11 circuit according to the present invention.
OB-B sectional view, FIG. 1 is a gate protection gta according to the present invention.
Figure 4 shows the electrical circuit of the gate protection circuit according to the present invention. The fs-diagram is an example of the arrangement of the polysilicon protection resistor of the gate protection circuit according to the developed flJ4.
The 7th E shows the manufacturing process of (6) to ('
The figure shown in J), Figure 8, is a diagram showing the relationship between the oxide film thickness and the high frequency tlI Bouge breakdown voltage. -Chip, bonding pad, 3... polysilicon protection resistor, 4. s-contact, - wiring, 1-
Protective element group, S-・Field effect transistor, ■・Axis field oxidation 1[,10,14-oxide film, 11-P type silicon substrate, 12゜ll-1l film, 13,1@-・・window, 1@-1'-) oxide film, 17-polysilicon film, 1... source. Drain, O-Arun two bonding pads%2
5- Surface capsular membrane, 13.- Diffusion resistance,! l,! 4. Snowstorm - Diode side Hiroko Hiromu Suzuki Hiromu Suzuki (A) 1g1 14a 14b Dimensions.
Claims (1)
ンジスタのグー）Ｋ接続される保護素子との関に電流制
限用保護抵抗を接続して成る半導体集積回路のゲート保
護回路において。 前記保護抵抗の値’１）ＳＯＫΩ〜５ｏｏｘΩとし且つ
前記ポンディングパッドと前記保護抵抗とが設けられた
半導体基板上の酸化膜の厚さを他の回路素子が設けられ
た半導体基板上の酸化膜の厚さより厚くシ曳ことｔＩ！
＃黴とするゲート保護回路。[Claims] In a gate protection circuit for a semiconductor integrated circuit, which includes a current-limiting protection resistor connected between a bonding pad serving as an input terminal and a protection element connected to a transistor to be protected. . Value of the protective resistance '1) SOKΩ to 5ooxΩ, and the thickness of the oxide film on the semiconductor substrate on which the bonding pad and the protective resistor are provided is the same as the oxide film on the semiconductor substrate on which other circuit elements are provided. It's thicker than the thickness of tI!
#Gate protection circuit against mold.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57005448A JPS58123763A (en) | 1982-01-19 | 1982-01-19 | Protective circuit for gate of semiconductor integrated circuit |
| DE19823243465 DE3243465A1 (en) | 1982-01-19 | 1982-11-24 | GATE PROTECTION CIRCUIT FOR AN INTEGRATED SEMICONDUCTOR CIRCUIT |
| GB08300725A GB2113469A (en) | 1982-01-19 | 1983-01-12 | Gate protection circuit for MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57005448A JPS58123763A (en) | 1982-01-19 | 1982-01-19 | Protective circuit for gate of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58123763A true JPS58123763A (en) | 1983-07-23 |
Family
ID=11611489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57005448A Pending JPS58123763A (en) | 1982-01-19 | 1982-01-19 | Protective circuit for gate of semiconductor integrated circuit |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS58123763A (en) |
| DE (1) | DE3243465A1 (en) |
| GB (1) | GB2113469A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4924280A (en) * | 1987-01-23 | 1990-05-08 | Oki Electric Industry Co., Ltd. | Semiconductor fet with long channel length |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4819047A (en) * | 1987-05-15 | 1989-04-04 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
| US4835416A (en) * | 1987-08-31 | 1989-05-30 | National Semiconductor Corporation | VDD load dump protection circuit |
| US5032742A (en) * | 1989-07-28 | 1991-07-16 | Dallas Semiconductor Corporation | ESD circuit for input which exceeds power supplies in normal operation |
| DE4301552A1 (en) * | 1993-01-21 | 1994-07-28 | Telefunken Microelectron | Integrated power resistor arrangement |
| KR101040859B1 (en) * | 2009-09-02 | 2011-06-14 | 삼성모바일디스플레이주식회사 | Organic Light Emitting Display Device |
-
1982
- 1982-01-19 JP JP57005448A patent/JPS58123763A/en active Pending
- 1982-11-24 DE DE19823243465 patent/DE3243465A1/en not_active Ceased
-
1983
- 1983-01-12 GB GB08300725A patent/GB2113469A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4924280A (en) * | 1987-01-23 | 1990-05-08 | Oki Electric Industry Co., Ltd. | Semiconductor fet with long channel length |
| US4987464A (en) * | 1987-01-23 | 1991-01-22 | Oki Electric Industry Co., Ltd. | Encapsulated FET semiconductor device with large W/L ratio |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2113469A (en) | 1983-08-03 |
| DE3243465A1 (en) | 1983-07-28 |
| GB8300725D0 (en) | 1983-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100311578B1 (en) | Semiconductor device | |
| KR19990066812A (en) | Reliable Diffusion Resistors and Diffusion Capacitors | |
| KR20060089673A (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| EP0661744A1 (en) | Semiconductor integrated circuit device | |
| JPS58123763A (en) | Protective circuit for gate of semiconductor integrated circuit | |
| US5731628A (en) | Semiconductor device having element with high breakdown voltage | |
| JPS60100469A (en) | Semiconductor device | |
| JP2974003B2 (en) | Semiconductor device and manufacturing method thereof | |
| US4922316A (en) | Infant protection device | |
| EP0087155B1 (en) | Means for preventing the breakdown of an insulation layer in semiconductor devices | |
| JPH0518466B2 (en) | ||
| JPH0821630B2 (en) | Semiconductor device | |
| JPS59154056A (en) | Semiconductor device | |
| JPH0738413B2 (en) | Semiconductor device | |
| JPH0410472A (en) | Protective circuit | |
| JPS61179576A (en) | Semiconductor integrated circuit device | |
| JPH08274265A (en) | Semiconductor device | |
| JPS62250664A (en) | Semiconductor integrated circuit | |
| JPS62166557A (en) | Protective device against electrostatic breakdown of semiconductor | |
| JPS61150263A (en) | Semiconductor ic device | |
| JPS6225448A (en) | Gate protective semiconductor device | |
| JPS5965453A (en) | Semiconductor device having multi-layer wiring | |
| JPH04133468A (en) | Input protection circuit of semiconductor device | |
| KR19990002870A (en) | Electrostatic discharge preventing transistor and manufacturing method | |
| JPH01238064A (en) | Semiconductor input protective device |