GB2113469A - Gate protection circuit for MOSFET - Google Patents
Gate protection circuit for MOSFET Download PDFInfo
- Publication number
- GB2113469A GB2113469A GB08300725A GB8300725A GB2113469A GB 2113469 A GB2113469 A GB 2113469A GB 08300725 A GB08300725 A GB 08300725A GB 8300725 A GB8300725 A GB 8300725A GB 2113469 A GB2113469 A GB 2113469A
- Authority
- GB
- United Kingdom
- Prior art keywords
- gate
- oxide film
- integrated circuit
- resistor
- gate protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000000670 limiting effect Effects 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 18
- 230000015556 catabolic process Effects 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A gate protection circuit for a MOSFET in a semiconductor integrated circuit, which can effectively attenuate the surge voltage input to the MOSFET gate so as not to cause erroneous operations in the integrated circuit even if a high-frequency high surge voltage is applied thereto, comprises a polycrystalline silicon protection resistor 3 having a resistance of 50 to 500 kiloohms interconnecting the input terminal bonding pad 2 and the gate of the MOSFET 8, which resistance is formed on an insulating oxide film 10 the thickness (1.0 to 1.8 micron) of which is greater than that (0.6 to 0.8 micron) of the field oxide film 9 where the other circuits are formed. <IMAGE>
Description
SPECIFICATION
Gate protection circuit for semiconductor integrated circuit
The present invention relates generally to a gate protection circuit for a semiconductor integrated circuit, and more specifically to a surge voltage protection circuit provided for an insulated gate field effect transistor. This protection circuit is necessary for protecting the gate from high-frequency high surge voltage inputted through an input terminal such as a bonding pad and for preventing the transistor from being activated erroneously by the surge voltage.
The background of the present invention will be explained with its application to the semiconductor integrated circuit, in particular, to an insulated gate field effect transistor used for an automotive vehicle.
An insulated gate field effect transistor is termed
MOS FET since the gate is formed in combination with metal (gate electrode), oxide (gate insulator) and semiconductor, being widely used in various fields. However, since the gate oxide film of this insulated gate field effect transistor is relatively thin and the gate impedance thereof is fairly high, if high-frequency high surge voltage is inputted through the bonding pad from an external device, there are some problems in that the gate is broken down or the circuit formed on a semiconductor silicon substrate is erroneously activated due to the high surge voltage.In applying MOS FETs to an automotive vehicle, in particular, the abovementioned problems are serious because an automotive vehicle is usually provided with various elements or apparatus which will readily generate high-frequency high surge voltage, for instance, such as an alternator, a starter motor, an ignition system, switches, etc. In more detail, when such an inductive element as described above is turned on or off at a high speed, a kind of electric wave is generated as electric noise from the inductive element. Therefore, when this electric noise wave is received by a semiconductor device having a high input impedance such as a field effect transistor, surge voltage as high as 400 to 500 volts sometimes develops across the input terminals of a semiconductor device.
In order to protect the semicondutor device from the surge voltage, there is well known a method of
providing a gate protection circuit, e.g., a surge voltage protection resistor connected between the input terminal and the gate of the field effect transistor. When such a gate protection resistor is additionally provided, since the surge voltage input ted through the bonding pad can be attenuated ohmicly, it is possible to prevent the transistor gate from beng broken down or the transistor from being activated erroneously. However, if the resistance of the protection resistor is increased excessively, since a high voltage develops across the protection resistor, the field oxide film (insulating oxide film) under the protection resistor may be easily broken down between the protection resistor and the semiconductor substrate.Accordingly, the ordinary resistance of the protection resistor is approximately several kiloohms.
By the way, in an automotive vehicle, there often exists a case where the surge voltage develops at the input terminal of a FET, the voltage of which is as high as several hundreds volts and the frequency of which is as high as several megahertz to several tens of megahertz. In the case where such high-frequency high surge voltage is inputted to the device, the surge current flows to the power supply line or the ground line (semiconductor substrate) via other elements or from P-N junction and sometimes leaks to the output terminal of the integrated circuit according to the magnitude of impedance, thus resulting in erroneous operation in the integrated circuit formed on the same substrate.
The structure of the prior-art field effect transistor including a gate protection circuit will be described in more detail hereinafter with reference to Figures 1(A) and 1(B).
With these problems in mind, therefore, it is the primary object of the present invention to provide a gate protection circuit for a semiconductor integrated circuit which can effectively attenuate surge voltage inputted to the integrated circuit and thus prevent the circuit from being operated erroneously due to the high-frequency high surge voltage, without causing breakdown within the semiconductor device.
To achieve the above-mentioned object, the gate protection circuit for an semiconductor integrated circuit according to the present invention comprises a polycrystal silicon protection resistor connected between input terminal bonding pad and gate of an integrated circuit, the resistance of which is about 50 to 500 kiloohms, and an insulating oxide film formed on the semiconductor substrate in such a way that the thickness of the oxide film on which the bonding pad and the protection resistor are formed is greater than that of the oxide on which other circuits are formed.
Since the resistance of the protection resistor is great, it is possible to effectively attenuate the surge voltage inputted from the input bonding pad before reaching the gate of the integrated circuit. Further, since only the insulating oxide film under the bonding pad and the protection resistor is thick, it is possible to reliably prevent breakdown caused by the surge voltage between the oxide film and the semicondutor substrate, without exerting a harmful effect upon the field oxide film under the other integrated circuit.
The features and advantages of the gate protection circuit for a semiconductor integrated circuit according to the present invention over the prior-art gate protection circuit will be more clearly appreciated from the following description of the preferred embodiment of the invention taken in conjunction with the accompanying drawings in which like reference numerals designate tthe same or similar elements or sections throughout the Figures thereof and in which::
Figure 1(A) is a top view showing the pattern of the gate protection circuit used for a typical prior-art insulated-gate field effect transistor;
Figure 1(BJ is a cross-sectional view taken along the line A-A shown in Figure 1(A);
Figure 2(A) is a top view showing the pattern of the gate protection circuit used for the insulated-gate field effect transistor according to the present invention;
Figure 2(B) is a cross-sectional view taken along the line B-B shown in Figure 2(A);
Figure 3 is a top view showing the pattern of the polycrystal silicon gate protection circuit used for the insulated-gate field effect transistor according to the present invention;;
Figure 4 is an equivalent circuit diagram of the gate protection circuit for the integrated-gate field effect transistor according to the present invention shown in Figure 2(A) or Figure 3;
Figure 5 shows a graphical representation of the relationship between the resistance of the polycrystal silicon gate protection resistor and the surge voltage leaked to the drain of a FET;
Figure 6 shows a graphical representation of the relationship between breakdown voltage due to high-frequency surge and thickness of insulating oxide film;
Figure 7 shows the process of manufacturing a silicon-gate MOS FET having a gate protection circuit according to the present invention, in which a
P-type silicon semicondutor substrate chip is used; and
Figure 8 shows the process of manufacturing an aluminum-gate MOS FET having a gate protection circuit according to the present invention, in which a
N-type silicon semiconductor substrate chip is used.
To facilitate understanding of the present invention, a brief reference will be made to a prior-art gate protection circuit for an insulated-gate integrated circuit, with reference to the attached drawings.
In Figures 1(A) and (B), the reference numeral 1 denotes a semiconductor substrate chip or pellet in which a transistor is formed; the reference numeral 2 denotes an input terminal such as an aluminum bonding pad; the reference numeral 3 denotes a current limiting protection resistor made of polycrystal silicon; the reference numeral 4 denotes a junction point between one end of the protection resistor 3 and the bonding pad 2; the reference numeral 5 denotes another junction point between the other end of the protection resistor 3 and a wire 6; the reference numeral 7 denotes an element group including two diodes D1 and D2 for protecting an insulated-gate field effect transistor 8. Further, the bonding pad 2 and the protection resistor 3 are formed on a uniformly-thickfield oxide film 9formed on the semiconductor substrate 1.
As explained above, the gate protection resistor 3 can ohmicly attenuate the surge voltage inputted through the bonding pad before the surge voltage
reaches the gate of the transistor 8, thus preventing the gate from being broken down or the transistor from being activated erroneously due to high surge voltage.
However, in the case where the resistance of the resistor 3 is excessively high, since a high voltage develops across both the ends of the resistor 3, there exist a danger that the field oxide film 9 under the protection resistor 3 may be broken down via the semiconductor substrate 1. Therefore, the resistance is about several kiloohms at the most in the prior-art protection resistor 3.
By the way, in an automotive vehicle, in the case where high-frequency high surge voltage (500 to 600V and 5 to 60 MHz) develops across the input terminal of the field effect transistor 8, the surge voltage easily leaks from the resistor 3 or the PN junction to the power line or the ground line directly or through the diodes D1 and D2 and the leaked surge current often reaches the output terminal of the transistor 8 through the impedances of the power line and the ground line including the semiconductor substrate chip 1 and a P well, thus resulting in an erroneous operation of the transistor 8.
In view of the above description, reference is now made to an embodiment of the gate protection circuit for a semiconductor integrated circuit according to the present invention, with reference to the attached drawings.
Figures 2(A) and 2(B) shows a first embodiment of the present invention. In the Figure, a current limiting gate protection resistor 3 is connected between an aluminum bonding pad 2 and a wire 6 through two junction points 4 and 5. The wire 6 is connected to a protection element group 7 made up to at-least one element, and the protection element group 7 is connected to the gate of a transistor 8. The protection resistor 3 serves to cause a voltage drop of the surge voltage inputted to the integrated circuit through the input terminal such as the bonding pad 2, before the surge voltage is applied to the gate of the transistor 8.
Therefore, the higherthe protection resistance, the more effectively the transistor 8 will be protected from a high voltage. However, when the protection resistance is excessively high, since a high voltage develops across both the ends of the protection resistor 3, the oxide film 10 under both ends of the protection resistor 3 may be broken down via the semiconductor substrate 1.
Under these considerations, the resistance of the protection resistor 3 is adjusted to 50 to 500 kiloohms in this embodiment by the process of ion implantation through which the concentration of impurity atoms such as boron or phosphor can be controlled. As depicted in Figure 2(B), the thickness of the input-side oxide film 10 on which the bonding pad 2 and the polycrystal silicon protection resistor 3 are formed (the circuit area enclosed by the dashed lines in Figure 2(A)) is greater than that of the field oxide film 9 on which other circuits such as a wire 6, a protection element group 7, a transistor 8, etc. are formed.
The field oxide film 9 can be formed in accordance with an ordinary manufacturing process, the thickness of which is approximately from 0.6 to 0.8 micron. In contrast with this, the thickness of the input-side oxide film 10 is approximately from 1.0 to 1.8 micron.
The reason why only the field oxide film 9 is thin as compared with the input-side oxide film 10 is as follows: in an integrated circuit, since some through holes (formed in insulation oxide films to connect two conductors (are necessary to connect aluminum wires to the semiconductor chip 1, in the case where the depth of the through-holes is excessive, there exists a danger that the aluminum wire is vertically sheared off easily at the through-hole portions.
Figure 3 shows a second embodiment of the present invention, in which an exemplary shape of the polycrystal silicon protection resistor 3 is depicted. In the Figure, the portion near the input terminal of the bonding pad 2 (enclosed by dashed curves) is broader in width to prevent the breakdown caused by electric field concentration of high surge voltage which develops across both the ends of the protection resistor 3. In this embodiment, the polycrystal silicon resitor 3 is about 0.35 micron (3500 A) in thickness, 5 micron in the width near the input terminal (these dimensions are determined under the consideration of thermal melting caused when a large current flows therethrough) and approximately 50 to 500 kiloohms in total resistance.The film resistance is from 500 to 1000 ohms per square centimeter, which can be adjusted by implanting ions of boron or phosphor at a rate of about 104 ##per square centimeter.
Figure 4 shows an equivalent circuit of the field effect transistor including the gate protection circuit according to the present invention.
In the Figure, the reference numeral 2 denotes the bodning pad and the numeral 3 denotes the protection resistor. The reference numeral 7 denotes a protection element group including a diffusion resistor 12 and three diodes 13, 14 and 15. The numeral 16 denotes a power supply line and the numeral 17 denotes a drain of one of field effect transistors 8.
In the Figure, the dashed lines show the route through which surge current flows from the protection resistor 3, through the power supply line 16, to the drain 17.
When the resistance of the protection resistor 3 is sufficiently high, since the surge voltage drops linearly through the resistor 3 in accordance with ohmic law, it is possible to reduce the electric surge power (product of surge voltage and surge current) applied to the power supply line 16 via the diodes 13 and 14, and therefore the surge current flowing through the power supply line 16 to the drain 17 (output terminal) of the field effect transistor 8 can be reduced. Further, it is also possible to reduce the amplitude (peak-to-peak voltage) of the leaked surge voltage by determining the time constant obtained by the product of distributed resistance and distributed capacitance of the diffusion resistor 12 to be sufficiently greater than the vibration period (1 to 20
MHz) of the surge voltage.
Figure 5 shows an experimental result of the relationship between the resistance (kiloohms) of the polycrystal silicon gate protection resistor 3 and the surge voltage leaked to the drain 8. As depicted in the graphical representation, it is desirable to determine the resistance of the resistor 3 to be more than 50 kiloohms, because there exists a danger than an erroneous operation occurs when a surge voltage leaked to the drain exceeds one volts.
There has been described hereinabove the necessity of increasing the resistance of the polycrystal silicon protection for reducing the surge voltage applied to the gate of the field effect transistor.
However, as the resistance increases, since the voltage developing across both the ends of the protection resistor 3 also increases, due consideration is additionally necessary for the electric breakdown caused between the polycrystal silicon protection resistor 3 and the semiconductor substrate 1 nearthe bonding pad 2, as well as the electric breakdown caused between the bonding pad 2 and silicon substrate 1, in the case where a semiconductor device is used under severe environment conditions where a high-frequency high surge voltage is usually applied thereto, for instance, in an automotive vehicle.
Figure 6 shows a graphical representation of the relationship between breakdown voltages due to an exemplary high-frequency surge and the thickness of the oxide film (micron). The breakdown voltage is measured as the peak-to-peak voltage of the exemplary surge waveform with a frequency of 1 to 20 megahertz and with a damping envelope of about 20 microseconds, as depicted in Figure 6. This figure indicates that in the case where the oxide film is required to withstand high-frequency surge voltage of more than 400 volts, the oxide film thickness must be from 1.6 to 1.7 micron. Further, as understood by the figure, the breakdown voltage due to such dynamic (alternating) surge voltage as described above is lower than that due to static (direct) voltage.
That is to say, providing that the oxide film 10 on which the bonding pad 2 and the polycrystal protection resistor 3 are formed is sufficiently thick, without increasing the thickness of the field oxide film 9 on which other circuits are formed, it is possible to reliably prevent breakdown in the oxide film 10 even if a high surge voltage is applied to the bonding pad 2 and the resistor 3.
Figure 7 shows the process of manufacturing the insulated-gate field effect transistor (silicon-gate
MOS FET) having a gate protection circuit according to the present invention.
First; a nitride film (Si3N4) 21 is formed on a P-type silicon semiconductor substrate chip 1 so as to provide a bare surface 22 (in step 1). In forming the nitride film 21, it may be preferable to form a thin oxide film (less than 0.1 micron) between nitride film and semiconductor chip to increase adhesive power between the two. Secondly, an oxide film (SiO2) 23 is grown up to a thickness of 1.8 to 2.0 micron by thermal oxidation (the chip 1 is exposed to vapor at a high temperature to form silicon oxide) (in step 2).
Thereafter, a MOS transistor is manufactured in accordance with an ordinary LOCOS (localized oxidation of silicon) method as follows: First, another nitride film 24 is formed for masking an area on which a FET is formed (in step 3). Secondary, the oxide film 23 is additionally grown up so as to form another oxide film 10, and a field oxide film 9 is newly formed on the bare surface (in step 4). Thirdly, after the nitride film 24 has been removed, a gate oxide film 25 is formd (in step 5). Fourthly, after the gate oxide film 25 has been formed, a polycrystal silicon films 3 and 26 are formed to make patterns of the gate 26 and the protection resistor 3 (in step 6).
Fifthly, a source and a drain 27 are formed through the bare surface 28 (in step 7). In forming the source and the drain 27, the impurity of the polycrystal silicon formed into the gate is controlled by doping.
In this case, however, it is necessary to mask the pattern of the polycrystal protection resistor 3 by a silicon oxide film formed by chemical vapor deposition method, after the impurity atom concentration in the resistor 3 has been controlled by ion implantation. Thereafter, as is usual, a film for insulating two adjoining layers is formed by silicon exide made by chemical vapor deposition; an aluminum bonding pad 2 is attached, junction contact point holes are formed; aluminum wiring is performed; a surface protecting film 29 is formed to cover the device (in step 8). The final thickness 10 of the oxide film under the bonding pad 2 and the protection resistor 3 is reduced to about 1.0 to 1.8 micron, because of certain etching process.
Description has been made of the manufacturing process of MOS FETs of a silicon gate (i.e. P-MOS,
N-MOS, C-MOS, etc.); however, it is also possible to readily manufacture aluminum-gate MOS FETs having a gate protection circuit according to the present invention by adding the step of forming the polycrystal silicon protection resistor.
Figure 8 shows the process of manufacturing the aluminum-gate MOS FET.
First, a nitride film (Si3N4) 21 is formed on a N-type silicon substrate chip 1 and the nitride film is removed from a portion 22 to provide a bare surface (in step 1). Secondly, an oxide film 23 is grown up to a thickness of 1.8 to 2.0 micron by thermal oxidation (the chip 1 is exposed to vapor at a high temperature to form silicon oxide SiO2) (in step 2). In this step, the surface covered by the nitride film is not oxidized.
Thirdly, the nitride film 21 is removed and the oxide film 23 is additionally grown up so as to form anotheroxidefilm 10, and afield oxide film 9 is newly formed on the bare surface. Next, boron (B) is diffused to form a P well 30 which becomes a base of a N-MOS FET under the silicon oxide film 9 (in step 3). Fourthly, boron is further diffused to form a source and a drain 31 of a P-MOS FET and a protection diode 32 under the silicon oxide film 9 (in step 4). Fifthly, phosphor (p) is diffused to form a source and a drain 33 of a N-MOS FET in the P well 30 (in step 5). Sixthly, a polycrystal silicon resistor 3 for the gate protection circuit is formed on the thicker oxide film 10 by chemical vapor deposition method and the resistance is controlled by ion implantation (in step 6).Seventhly, a gate oxide film 34 is grown up on the silicon resistor 3 and some oxide film portions are removed (in step 7). Eightly, an aluminum 35 is vapor-deposited for wiring (in step 8). Ninthly, a surface protection film 36 is formed thereon by producing a phosphorus glass by chemical vapor deposition (in step 9).
As described above, in the gate protection circuit for a semiconductor integrated circuit according to the present invention, since the resistance of a polycrystal silicon protection resistor connected between the input terminal and the gate protection element group is so determined as to lie from 50 to 500 kiloohms and since the thickness of the oxide film on which the input terminal (bonding pad) and th polycrystal silicon protection resistor are formed is so determined as to be greater than that of the oxide film on which other circuits are formed (i.e. the field oxide film), even if high-frequency high surface voltages are applied to the input terminal of the semiconductor integrated circuit, it is possible to effectively attenuate the surge voltage inputted to the integrated circuit owing to the resistance of the gate protection resistor, without causing breakdown in the oxide film, thus effectivey preventing the circuit from being activated erroneously due to high-frequency high surge voltage.
It will be understood by those skilled in the art that the foregoing description is in terms of a preferred embodiment of the present invention wherein various changes and modifications may be made without departing from the spririt and scope of the invention, as set forth in the appended claims.
Claims (6)
1. A gate protection circuit for an semiconductor integrated circuit connected between an input bonding pad and a gate of an integrated circuit formed on a semiconductor substrate, which comprises:
(a) a gate protection resistor with a high resistance, said resistor being connected between the bonding pad and the gate of the integrated circuit; and
(b) an insulating oxide film formed on the semiconductor substrate, the thickness of said oxide film on which the bonding pad and said current limiting protection resistor are formed is greater than that of said oxide film on which other circuits are formed.
2. A gate protection circuit for an semiconductor integrated circuit as set forth in claim 1, wherein the resistance of said gate protection resistor is from 50 to 500 kiloohms.
3. A gate protection circuit for an semiconductor integrated circuit as set forth in claim 2, wherein said gate protection resistor is made of polycrystal silicon film approximately 0.35-micron thick and approximately 5-micron broad, the resistance of said resistor being adjusted by ion implantation.
4. A gate protection circuit for an semiconductor integrated circuit as set forth in claim 1, wherein the thickness of said oxide film on which the bonding pad and said gate protection resistor are formed is approximately from 1.0 to 1.8 micron and the thickness of said oxide film on which other circuits are formed is approximately from 0.6 to 0.8 micron.
5. gate protection circuit for a semiconductor integrated circuit substantially as herein described with reference to and as illustrated by Figures 2(A) and 2(B), or Figures 2(A), 2(B), and 3, or Figures 2(A), 2(B), and 4, or Figures 2(A), 2(B), 3, and 4, of the accompanying drawings.
6. A process for manufacturing a gate protection circuit for a semiconductor integrated circuit substantially as herein described with reference to and as illustrated by Figure 7 or Figure 8, of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57005448A JPS58123763A (en) | 1982-01-19 | 1982-01-19 | Protective circuit for gate of semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8300725D0 GB8300725D0 (en) | 1983-02-16 |
| GB2113469A true GB2113469A (en) | 1983-08-03 |
Family
ID=11611489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08300725A Withdrawn GB2113469A (en) | 1982-01-19 | 1983-01-12 | Gate protection circuit for MOSFET |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS58123763A (en) |
| DE (1) | DE3243465A1 (en) |
| GB (1) | GB2113469A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0305935A2 (en) * | 1987-08-31 | 1989-03-08 | National Semiconductor Corporation | VDD load dump protection circuit |
| US4819047A (en) * | 1987-05-15 | 1989-04-04 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
| US5032742A (en) * | 1989-07-28 | 1991-07-16 | Dallas Semiconductor Corporation | ESD circuit for input which exceeds power supplies in normal operation |
| DE4301552A1 (en) * | 1993-01-21 | 1994-07-28 | Telefunken Microelectron | Integrated power resistor arrangement |
| CN102005166A (en) * | 2009-09-02 | 2011-04-06 | 三星移动显示器株式会社 | Organic light emitting display device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2545527B2 (en) * | 1987-01-23 | 1996-10-23 | 沖電気工業株式会社 | Semiconductor device |
-
1982
- 1982-01-19 JP JP57005448A patent/JPS58123763A/en active Pending
- 1982-11-24 DE DE19823243465 patent/DE3243465A1/en not_active Ceased
-
1983
- 1983-01-12 GB GB08300725A patent/GB2113469A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4819047A (en) * | 1987-05-15 | 1989-04-04 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
| EP0305935A2 (en) * | 1987-08-31 | 1989-03-08 | National Semiconductor Corporation | VDD load dump protection circuit |
| EP0305935A3 (en) * | 1987-08-31 | 1992-08-05 | National Semiconductor Corporation | Vdd load dump protection circuit |
| US5032742A (en) * | 1989-07-28 | 1991-07-16 | Dallas Semiconductor Corporation | ESD circuit for input which exceeds power supplies in normal operation |
| DE4301552A1 (en) * | 1993-01-21 | 1994-07-28 | Telefunken Microelectron | Integrated power resistor arrangement |
| CN102005166A (en) * | 2009-09-02 | 2011-04-06 | 三星移动显示器株式会社 | Organic light emitting display device |
| US8742784B2 (en) | 2009-09-02 | 2014-06-03 | Samsung Display Co., Ltd. | Organic light emitting display device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8300725D0 (en) | 1983-02-16 |
| DE3243465A1 (en) | 1983-07-28 |
| JPS58123763A (en) | 1983-07-23 |
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