JPH1065157A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the element breakdown due to a surge voltage, etc., applied to the semiconductor element within a semiconductor device. SOLUTION: N<+> /P/N<+> -type bidirectional Zener diode 17 are built in between the gate and the source of a MOS FET 19, so that even if surge voltage, etc., is applied to a semiconductor device, the N<+> /P/N<+> -type bidirectional Zener diodes 17 may art as a clamp circuit for avoiding the element breakdown, thereby enabling the element to be protected even in a smaller chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a transistor, and more particularly, to a semiconductor device having a structure suitable for preventing electrostatic breakdown of a transistor.

[0002]

2. Description of the Related Art The prior art is shown in FIGS. FIG.
FIG. 4 is an equivalent circuit diagram showing a conventional semiconductor device.
FIG. 2 is a sectional view of a main part showing a conventional semiconductor device.

A conventional semiconductor device in which a P ⁺ / N / P ⁺ type bidirectional Zener diode is connected between a gate and a source is shown in FIG.
As shown in FIG. 5, an N well layer 4 is formed on a surface layer of a P ⁻ epitaxial layer 3 on a P ⁺ substrate 2 with which a drain electrode 1 of a MOS FET 19 contacts, and a field oxide film 5 is formed on the N well layer 4. A bidirectional Zener diode 18 (see FIG. 3) composed of a P ⁺ layer and an N layer 16 was present in the field oxide film 5.

The P ⁺ layer 1 of the bidirectional Zener diode 18
Reference numeral 5 denotes a gate aluminum 10 and a source aluminum 1 by a wiring contacting a contact hole provided in the interlayer insulating film 6.
1 connected. 7 is P ⁺ layer, 8 is N ⁺ layer, 9 is N
The layer 12 is a polycrystalline silicon film.

FIG. 3 is an equivalent circuit diagram showing a conventional semiconductor device. In the conventional semiconductor device shown in FIG.
By setting the Zener withstand voltage of the P ⁺ / N / P ⁺ type bidirectional Zener diode 18 connected between the sources to be lower than the withstand voltage of the MOS FET 19, when a surge voltage or the like is applied, the Zener withstands before the MOS FET 19. Since the Zener diode 18 breaks down, the Zener diode 18 functions as a clamp circuit, and the MOS FET
Nineteen elements were prevented from being destroyed.

[0006]

However, in the conventional example shown in FIGS. 3 and 4, the P ⁺ / N / P ⁺ type bidirectional Zener diode has a soft Zener withstand voltage waveform (FIG. 5 (b)). )), When the chip size is reduced, there is a problem that a sufficient protection circuit is not provided, and element destruction is caused. The reason is that if the Zener diode is formed of P ⁺ / N / P ⁺ , a breakdown occurs in the surface layer because the breakdown voltage determining region (low concentration region) is formed of the N layer. This is because the leak before the breakdown increases and the operating resistance increases.

Further, in the conventional example, since the P ⁺ layer of the Zener diode and the source layer of the MOS FET are formed at the same time, there is a problem that the Zener breakdown voltage is high. The reason is that the condition for forming the source of the MOS FET becomes dominant and the Zener withstand voltage cannot be controlled. In order to lower the Zener withstand voltage in the conventional example, it was necessary to add an IPR.

An object of the present invention is to provide a semiconductor device which has solved the above-mentioned problems.

[0009]

To achieve the above object, according to an aspect of a semiconductor device according to the present invention is a semiconductor device having a Pch insulated gate transistor formed on a semiconductor substrate, in a semiconductor substrate N ⁺ / P / N ⁺ type bidirectional Zener diode, wherein the bidirectional Zener diode connects the gate region and the source region of the transistor.

The N of the Pch insulated gate transistor
⁺ Layer and N ⁺ layer of the N ⁺ / P / N ⁺ -type bidirectional Zener diode, and is formed at the same time.

The N ⁺ / P / N ⁺ type bidirectional Zener diode is formed in a plurality of stages.

[0012]

According to the present invention, an N.sup. ⁺ / P / N.sup. ⁺ Type bidirectional Zener diode is built in between the gate and the source of the semiconductor device, so that the Zener breakdown voltage waveform is hardened and the operating resistance of the Zener portion is reduced. By improving the electrostatic withstand voltage, when a surge voltage or the like is applied to the semiconductor device, the surge voltage or the like can be clamped, and element destruction can be prevented.

[0013]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

In FIG. 1, a semiconductor device according to an embodiment of the present invention is a Pch insulated gate transistor (MOS).
FET) 19, an N ⁺ / P / N ⁺ type bidirectional Zener diode 17 is arranged between the gate and the source.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. As shown in FIG.
P ⁻ on P ⁺ substrate 2 with which drain electrode 1 of ET19 contacts
On the surface layer of the epitaxial layer 3, an oxide film 5
It is formed to a thickness of about 12000 ° and is patterned using lithography.

Further, a polycrystalline silicon film 12 is formed on oxide film 5.
Is formed to a thickness of 4000 to 6000 °, and is patterned by using lithography technology.
An N ⁺ layer 13 and a P layer 14 are formed therein by using a lithography technique, and an interlayer insulating film 6 is formed on the N ⁺ layer 13 and the P
It is formed to a thickness of Å and patterned using lithography technology. The gate aluminum electrode 10 and the source aluminum electrode 11 are in contact with each other on the N ⁺ layer 13 to form an N ⁺ / P / N ⁺ type bidirectional Zener diode 17.

As described above, N ⁺ / P / N ⁺ is formed in the semiconductor substrate.
Type bidirectional Zener diode 17 is arranged, and the N ⁺ /
The P / N ⁺ type bidirectional Zener diode 17 connects the gate region and the source region of the MOS FET 19 as a Pch insulated gate transistor.

Next, the operation of the embodiment of the present invention will be described.
This will be described in detail with reference to FIG.

By setting the withstand voltage V _{17 of the} N ⁺ / P / N ⁺ type bidirectional Zener diode 17 lower than the withstand voltage of the MOSFET 19, when a surge voltage or the like is applied to the MOS FET 19, N ⁺ is applied before the MOS FET 19. / P /
Since the N ⁺ -type bidirectional Zener diode 17 breaks down, a surge voltage or the like is not applied to the MOS FET 19 as it is, so that element destruction can be prevented.

The N ⁺ / P / N ⁺ type bidirectional Zener diode 17 has a hard zener breakdown voltage waveform (FIG. 5).
(Refer to (b)), the operating resistance is small, and the breakdown is instantaneous. Therefore, the influence of the surge voltage or the like on the MOS FET 19 can be reduced, and the element destruction can be more reliably prevented.

Further, the experimental results show that And the Zener structure is of the N ⁺ / P / N ⁺ type, so that the ESD resistance is 1400 V → 3900 on the MIL + side.
V and the voltage on the MIL- side was increased from 1200 V to 3500 V. At the same time, the operating resistance was also reduced from 130Ω to 30Ω.

[0022]

Next, an embodiment of the present invention will be described in detail with reference to FIGS.

In manufacturing the semiconductor device in this embodiment, as shown in FIG. 2, an oxide film 5 is formed on the surface layer of the P ^- epitaxial layer 3 on the P ⁺ substrate 2 with which the drain electrode 1 of the MOS FET 19 contacts. Is formed to a thickness of 10,000 °, and is patterned using lithography technology.

Further, a polycrystalline silicon film 12 is formed thereon to a thickness of 4700.degree. And patterned by lithography to form an N.sup. ⁺ Layer 1 in the polycrystalline silicon film 12.
3 and a P layer 14 are formed using lithography technology, and an interlayer insulating film (BPSG film) 6 is formed thereon to a thickness of 6500 ° and patterned using lithography technology. The gate aluminum electrode 10 and the source aluminum electrode 11 are in contact with the N ⁺ layer 13 to form an N ⁺ / P / N ⁺ type bidirectional Zener diode 17.

As described above, N ⁺ / P / N ^{+ is} contained in the semiconductor substrate.
Type bidirectional Zener diode 17 is arranged, and the N ⁺ /
The P / N ⁺ type bidirectional Zener diode 17 connects the gate region and the source region of the MOS FET 19 as a Pch insulated gate transistor.

Next, the operation of the embodiment of the present invention will be described with reference to an equivalent circuit diagram of the semiconductor device of FIG.

By setting the withstand voltage V _{17 of the} N ⁺ / P / N ⁺ type bidirectional Zener diode 17 lower than the withstand voltage of the MOS FET 19, the surge voltage and the like can be reduced.
Is applied to N ⁺ / P before the MOS FET 19.
Since the / N ⁺ type bidirectional Zener diode 17 breaks down, a surge voltage or the like is not applied to the MOS FET 19 as it is, so that element destruction can be prevented.

Further, the N ⁺ / P / N ⁺ type bidirectional Zener diode 17 has a hard zener breakdown voltage waveform (FIG. 5).
(Refer to (b)), the operating resistance is small, and the breakdown is instantaneous. Therefore, the influence of the surge voltage or the like on the MOS FET 19 can be reduced, and the element destruction can be reliably prevented even for a smaller chip. Can be.

(Embodiment 2) Next, Embodiment 2 of the present invention
Will be described with reference to FIG. In the second embodiment,
The semiconductor device according to the first embodiment is manufactured without increasing the number of steps.

In the process of forming the N ⁺ / P / N ⁺ type bidirectional Zener diode 17 described in the first embodiment, the semiconductor device according to the second embodiment has a MOS transistor as shown in FIG.
The N ⁺ layer 8 of the FET 19 is formed by contact phosphorus I / I, and the N ⁺ layer 13 of the N ⁺ / P / N ⁺ type bidirectional Zener diode 17 is formed at the same time.

Thus, it is possible to form a semiconductor device which is advantageous in element destruction without increasing the number of steps as compared with the conventional P ⁺ / N / P ⁺ type bidirectional Zener diode 18.

In order to obtain the same effect as the N ⁺ / P / N ⁺ type bidirectional Zener diode 17 of the present invention by using the conventional P ⁺ / N / P ⁺ type bidirectional Zener diode 18, Conventional P ⁺ / N / P ⁺ bidirectional Zener diode 1
Since the P ⁺ layer 8 of 8 is formed separately from the P ⁺ layer 7 of the MOS FET 18, a Zener boron PR step is required, and the number of steps is increased.

[0033]

As described above, according to the present invention, an N ⁺ / P / N ⁺ type bidirectional Zener diode is built in between a gate and a source of a semiconductor device. Can be prevented from being destroyed. The reason is that the Zener structure is of the N ⁺ / P / N ⁺ type, so that the Zener withstand voltage waveform can be hardened and the operating resistance is reduced.

In addition, a semiconductor device advantageous for element destruction can be formed in the same number of steps as a conventional P ⁺ / N / P ⁺ type bidirectional Zener diode. The reason is that MOSFET
This is for forming the N ⁺ layer of the N ⁺ / P / N ⁺ type bidirectional Zener diode in the same step as the formation of the N ⁺ layer.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram showing a semiconductor device according to a conventional example.

FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIG. 5A is a waveform diagram showing a Zener breakdown voltage waveform of a Zener structure according to the present invention, and FIG. 5B is a waveform diagram showing a Zener breakdown voltage waveform of a Zener structure according to a conventional example.

[Explanation of symbols]

Reference Signs List 1 drain electrode 2 P ⁺ substrate 3 P ^- epitaxial layer 4, 9, 16 N layer 5 oxide film 6 interlayer insulating film 7, 15 P ⁺ layer 8, 13 N ⁺ layer 10 gate aluminum electrode 11 source aluminum electrode 12 polycrystalline silicon Film 14 P layer 17 N ⁺ / P / N ⁺ type bidirectional Zener diode 19 MOS FET (Pch insulated gate transistor)

Claims (3)

[Claims] 1. A semiconductor device having a Pch insulated gate transistor formed on a semiconductor substrate, comprising: an N ⁺ / P / N ⁺ type bidirectional Zener diode in the semiconductor substrate; Is a semiconductor device in which a gate region and a source region of the transistor are connected. Wherein the N ⁺ layer of the the N ⁺ layer of the Pch insulated gate transistor N ⁺ / P / N ⁺ -type bidirectional Zener diode, claim 1, characterized in that formed at the same time 3. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the N ⁺ / P / N ⁺ type bidirectional Zener diode is formed in a plurality of stages.