JPS58122150U - Unauthorized access detection circuit to memory - Google Patents
Unauthorized access detection circuit to memoryInfo
- Publication number
- JPS58122150U JPS58122150U JP1679282U JP1679282U JPS58122150U JP S58122150 U JPS58122150 U JP S58122150U JP 1679282 U JP1679282 U JP 1679282U JP 1679282 U JP1679282 U JP 1679282U JP S58122150 U JPS58122150 U JP S58122150U
- Authority
- JP
- Japan
- Prior art keywords
- program
- detection signal
- register
- access address
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Storage Device Security (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のメモリへの不正アクセス検出回路を示す
ブロック図、第2図は本考案によるメモリへの不正アク
セス検出回路を示すブロック図である。
1・・・アクセスアドレス設定レジスータ、2・・・実
行中アクセスアドレスレジスタ、3・・・プログラム番
−号設定レジスタ、4・・・実行中プログラム番号
レジスタ、5A〜5N・・・レジスタ値一致検出回路、
6、・・NOT回路、7.11・・・AND回路、8・
・・プログラムカウンタ、90〜9N・・・プログラム
カウンタ値設定レジスタ、10・・・NOR回路、12
・・・OR回路。なお、図中、同一符号は同−又は相当
部分を示す。FIG. 1 is a block diagram showing a conventional memory unauthorized access detection circuit, and FIG. 2 is a block diagram showing a memory unauthorized access detection circuit according to the present invention. 1...Access address setting register, 2...Access address register in progress, 3...Program number - number setting register, 4...Program number in progress register, 5A to 5N...Register value match detection circuit,
6....NOT circuit, 7.11...AND circuit, 8.
...Program counter, 90-9N...Program counter value setting register, 10...NOR circuit, 12
...OR circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
を記憶する実行中アクセスアドレスレジスタと所定のア
クセスアドレスを設定したアクセスアドレス設定レジス
タとの値を入力してアクセスアドレスの一致検出信号を
出力する第1のレジスタ値一致検出回路と、実行中プロ
グラム番号を記憶する実行中プログラム番号レジスタと
所定のプログラム番号を設定したプログラム番号設定レ
ジスタとの値を入力してプログラム番号1致検出信号を
出力する第2のレジスタ値一致検出回路とを備え、上記
アクセスアドレスの一致検出信号と−プログラム番号の
不一致検出信号とに基いてメモリへの大正7クセス時に
割込信号を発生するようになされたメモリへの不正アク
セス検出回路において、プログラムの実行をカウントす
るプログラムカウンタと、正当なプログラム実行中に正
当なアクセスを行う時のプログラムカウンタ値をそれぞ
れ予め設定記憶する各プログラムカウンタ値設定レジス
ターと、これらレジスタのプログラムカウンタ値と上記
プログラムカウンタとの値を入力してそれぞれ一致検出
信号を出力する各レジスタ値一致検出回路と、設牢記憶
された各プログラムカウンタ値と実行されたプログラム
カウンタ値とがいずれも不一致の時のプログラムカウン
タ値下一致信号と上記プログラム番号一致検出信号との
論−埋積出力を得ると共′に、この論理積出力と上記プ
ログラム番号一致検出信号との論理和出力を得、この論
理和出力と上記アクセスアドレスの一致検出信号との論
理積によってメモリへの不正アクセス時に割込信号を発
生する論理回路とを設けたことを特徴とするメモリへの
不正アクセス検出回路。A first register value that inputs the values of an access address register during execution that stores an access address when a program is executed by a computer and an access address setting register that sets a predetermined access address and outputs an access address match detection signal. A second register value that inputs the values of the match detection circuit, the running program number register that stores the running program number, and the program number setting register that sets a predetermined program number, and outputs a program number matching detection signal. a coincidence detection circuit, and is configured to generate an interrupt signal when the memory is accessed in Taisho 7 based on the coincidence detection signal of the access address and the mismatch detection signal of the -program number. , a program counter that counts the execution of a program, each program counter value setting register that stores the program counter value when a legitimate access is made during legitimate program execution, and the program counter values of these registers and the above. Each register value match detection circuit inputs the value of the program counter and outputs a match detection signal, and the program counter when the stored program counter value and the executed program counter value do not match. At the same time as obtaining the logical sum output of the lower value match signal and the above program number match detection signal, the logical sum output of this AND output and the above program number match detection signal is obtained, and the logical sum output and the above program number match detection signal are obtained. 1. A circuit for detecting unauthorized access to a memory, comprising: a logic circuit that generates an interrupt signal at the time of unauthorized access to the memory by ANDing an access address with a match detection signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1679282U JPS58122150U (en) | 1982-02-08 | 1982-02-08 | Unauthorized access detection circuit to memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1679282U JPS58122150U (en) | 1982-02-08 | 1982-02-08 | Unauthorized access detection circuit to memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58122150U true JPS58122150U (en) | 1983-08-19 |
Family
ID=30029143
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1679282U Pending JPS58122150U (en) | 1982-02-08 | 1982-02-08 | Unauthorized access detection circuit to memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58122150U (en) |
-
1982
- 1982-02-08 JP JP1679282U patent/JPS58122150U/en active Pending
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