JPS58118B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, particularly a switch for writing information (hereinafter referred to as a write switch).

).

Conventionally, in this type of semiconductor memory device, the light switch uses an MO whose source and drain are double-diffused.
S transistor (hereinafter referred to as D2SAMO8T).

) was used. D2SAMO8T has the same type of pn junction in the source region and drain region, so its electrical characteristics are symmetrical with respect to the direction of current between the drain and source.

This symmetry of electrical characteristics is the reason why D2SAMO8T is conventionally used as a light switch in semiconductor memory devices.

A detailed explanation of the conventional example can be found in the publication I Nis Nis C Digest published in 1977.
Op Technical Pavers (15SCCDIGES)
Kei Shimotori (K) published on pages 76, 77, and 240 of
, Shimotori) et al. (especially the FIGU
RE4(a)).

However, as a result of a detailed study of the memory cell and its peripheral circuits, the inventor found that the light switch does not necessarily require symmetry in electrical characteristics.

On the contrary, in the symmetrical D2SAMO8T, the drain region also has a high concentration pn junction like the source region, so both the drain electrode and the source electrode have a large parasitic capacitance, and the write drive line has a large number of parasitic capacitances. Since a write switch is connected, a conventional circuit using D2SAMO8T as a write switch has the drawback that the capacity of the write drive line is extremely large (which results in a significant increase in write time).

An object of the present invention is to reduce the parasitic capacitance of a write drive line by using a transistor with a small parasitic capacitance as a write switch, thereby providing a high-speed semiconductor memory device with a short write time.

According to the present invention, a DSAMO8T is provided as an information write switch, with a source electrode connected to the information line, a drain electrode connected to the write momme drive line, and a gate electrode connected to the digit selection line. A semiconductor memory device can be obtained.

Next, the present invention will be explained with reference to the figures.

FIG. 1 shows a light switch and a one-transistor type memory cell of a conventional semiconductor memory device.

A voltage level corresponding to a binary signal "1" or "0" is applied to the write drive line 10 by a write drive circuit.

At this time, when a high level voltage is applied to the digit drive line 11, a high level voltage is applied to the gate electrode 2 of the light switch 100, and the light switch 100 becomes conductive.

When the write switch 100 becomes conductive, the binary signal on the write drive line 10 is transmitted to the information line 13.

Further, the 2-channel signal on the information line 13 causes the transfer gate 20 to become conductive when the potential on the word line 12 becomes high level.
0 is stored in the capacity 300.

Terminal 14 of capacitor 300 is connected to a power source.

In this conventional circuit, the light switch 100 has a D2SA
Since NO8T is used, a high concentration pn junction is connected to both the source electrode 3 and the drain electrode 1, and a large parasitic capacitance is attached thereto.

On the other hand, since a large number of write switches are connected to the write drive line 10, the parasitic capacitance of the write drive line 10 is extremely large.

Therefore, it takes time to charge and discharge the capacitance of the write drive line 10, resulting in a drawback that the write time is extremely long.

FIG. 2 shows an embodiment of a semiconductor memory device according to the present invention.

Since the circuit operation is exactly the same as the conventional one, the explanation will be omitted here.

Here, DSAMO8T is used for the light switch 400.

The source electrode 6 of the DSA is connected to an information line 18 , the gate electrode 5 is connected to a digit drive line 15 , and the drain electrode 4 is connected to a write drive line 16 .

DSAMO8T has a highly doped pn junction on the source side, but since the pn junction on the drain side is a lightly doped junction, the parasitic capacitance on the drain side is extremely small.

Because of this asymmetry, it has not been used in the past.

However, the inventor has once again confirmed that this is an unnecessary concern.

Although the present invention broke the conventional wisdom, its effects are significant and noteworthy.

For example, even if a large number of such light switches are connected, the parasitic capacitance associated with the write drive line is extremely small compared to conventional circuits.

Therefore, in the circuit according to the present invention, the time required to charge and discharge the parasitic capacitance associated with the write drive line is short, and a high-speed write operation is possible.

Note that although a semiconductor memory device having a one-transistor type dynamic memory cell has been described here, the present invention is not limited thereto and can also be applied to a semiconductor memory device having a six-transistor type static memory cell. It is.

[Brief explanation of the drawing]

FIG. 1 shows the write-switch and memory cell portions of a conventional semiconductor memory device. 10 is a write drive line, 100 is a light switch, 11
12 is a word line, 13 is an information line, 200 is a transfer gate, and 300 is a capacity for information storage. FIG. 2 shows the write switch and memory cell portion of the semiconductor memory device according to the present invention. 16 is a write drive line, 400 is a light switch, 15
17 is a digit selection line, 17 is a word line, 18 is an information line, 500 is a transfer gate, and 600 is a capacity for information storage.

Claims (1)

[Claims] 1. A DSAMOS transistor is provided as an information write switch, with a double-diffused source electrode connected to the information line, a drain electrode connected to the write drive line, and a gate electrode connected to the digit selection line. Characteristic semiconductor memory device.