JPS58118153A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a poly Si gate FET having a low density layer of the same polarity as a drain and a source between a drain, a source, and an Si substrate without using a metallic mask, etc. CONSTITUTION:On the substrate or well 1, a field insulation film 2 and a gate insulation film 3 are formed resulting in the formation of a poly Si gate 4. With the poly Si 4 as a mask, ion implantation is performed at a low energy, and accordingly high density source and drain layers 5 are formed. After the oxidation of the entire body, when an oxide film 7 is etching-removed, the dimension of the poly Si decreases. Next, again with the poly Si 4 as a mask, an ion implantation is performed at a high energy, accordingly low density layers 6 are formed. In this method, where the etching rate for the oxide film on the poly Si is kept grasped, the low density layer 6 can be accurately formed, and thus a poly Si gate FET of high performance can be obtained.

Description

[Detailed Description of the Invention] According to the present invention, between the drain and the source and the silicon substrate,
The present invention relates to a method for manufacturing an IJ silicon gate type semiconductor device having a source and a drain, 11yl poles, and a low #fake layer.

The MO8 type semiconductor device to which the present invention is applied is shown in FIG. 1, where 1 is a silicon substrate well.

2rD field insulating film, 5 gate insulating film, 4 holes 1
1 silicon 11 conductor, 5 a source and train, 61 source and train, (b) pole and low $9 layer ・In the MOEI type semiconductor having the structure shown in Fig. 1, between the train and source and the substrate or well In, drain and source and 1'
By increasing the low concentration layer of the 8'I electrode, there are the following advantages.

1) Between Train and Chanul, it is possible to carry out the 9-layer honing to the Chamel side.

% fI'' of the drain pressure delivered to the short channel
It's all about prevention. (Punch-through is very slow.) 2) The capacitance between the base I well, the source, and the train is reduced, which is effective in speeding up the probe.

Conventional manufacturing method of a semiconductor device having such a structure t-r
After forming the field insulating film, gate oxide S, and gate W electrode, apply a low concentration to the self-alignment line.

High-energy ion implantation is performed, and
Large sweat saw 711F rain region tube formed with f, then metal mask etc.? In order to create a low-concentration source and a high-concentration region C in the train region (5)'f in Figure 1, ions are implanted at high concentration and low energy.
The low concentration region fYl of 6 in FIG. 1 was formed.

In this conventional process, the crotch of the mask fitting such as a metal mask, the mask misalignment, and the area 6 in Fig. 1 are lost. be.

After removing the defects according to the present invention and forming a good-to-po+3 silicon electrode, the first step is to perform high-concentration, low-emergence ion implantation into the cell line.
-The urn forms 5 areas.

Etch the entire film to reduce the gate polysilicon size and reduce the concentration.

High-energy ion implantation is performed first. 1st
A well extension 1 (r, low concentration region C, 6 in FIG. 1) is formed over the substrate in the S region of the decoy.

*Issuing will be explained in detail below. The manufacturing process of the present invention is shown in the second example, and the manufacturing process is explained below in accordance with the process.

(g) Form a field IPJ powder 2° gate insulating film 3 on the substrate or white work 91.

CB) Form gate polysilicon 4.

(C) High-concentration, low-energy ion implantation is performed using Kate polysilicon 4 as a mask to form a high-concentration II-C. A drain region 5 is formed.

(D) Oxidize the whole.

(]I!1 Etching the acid-etched film 7. At this time, the polysilicon size is reduced compared to before wI conversion.

(F'l Using the gate polysilicon as a mask, low concentration, high energy ion implantation is performed, and low concentration -thJ
form 6.

According to the present invention, gold can be used without using a mask such as a mask.
1st [iZl's 6 area is too drunk #L#
If the etching rate of the acid on the polysilicon in step φ) of step 11u is known, the area No. 6 of 111-71 can be formed with precision.

In the manufacturing process according to the present invention, conventional IT
This eliminates some of the shortcomings.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device that is the object of the present invention, and Figures 2 to (F) are cross-sectional views of each step in the manufacturing method of the present invention. 1... Base tube 2... Field insulating film 5... Gate insulating film 4... Gate polysilicon 5... Source and drain 6... Image concentration diffusion layer 7 with the same polarity as the source and drain...
・Acid-based silicon film] Figure 1

Claims (1)

[Claims] 1. Manufacturing of Silicon Gate MOB Type Semiconductor Device ■In the rod, on the substrate or well, field insulation II1.
Form a gate insulation layer and apply voltage 11conflF on top of it.
7? After that, using the polysilicon gate electrode as a mask, high-concentration impurities are ion-implanted at low energy to form a process line and a train line on the 79th line.
3i', by removing the ferric acid silicon film,
After reducing the dimensions of the gate electrode, impurities with low fIk& are ion-implanted using the available energy so that they are the same polarity as the source and train and have low f! A method of manufacturing a semiconductor device in which #11 NI is formed between a train, a source, a well, or a silicon substrate to reduce f% mold.