JPS58117722A - Digital-to-analog converter - Google Patents

Abstract

PURPOSE:To reduce the response time, by dividing a digital input into a plurality of upper-order and lower-order bits and synthesizing the outputs of each converter with weighing, in a D-A converter of pulse integration system. CONSTITUTION:The digital input is divided into upper-order 4 bits and lower- order 8 bits, and the upper order bits are inputted to an upper-order duty conversion circuit 5A and the lower-order bits are inputted to a lower-order duty conversion circuit 5B. When the clock frequency generated at a clock generator 3 is 4,096kHz, the output frequency of the circuit 5A is 256kHz and that of the circuit 5B is 16kHz, and they are synthesized with the weight of 16:1 at an addition circuit 8, then the ripple of both duty conversion circuit outputs is suppressed in the ratio, and the time constant of smoothing low pass filters 6A, 6B is 8ms, which is remarkably reduced in comparison with conventional types not dividing bits into upper and lower-order bits.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DA converter, and particularly to a pulse integration type DA converter.

Generally, a pulse-integration type D-A converter converts a digital input into a pulse duty ratio, generates a pulse signal by turning on and off the reference power output using a solenoid, and smoothes the output using a low-pass filter to produce an analog output. This method does not require a large number of precision resistors, so it has very high accuracy and stability, making it particularly suitable for electronic balances.

As the tutee ratio conversion method, a method using an up/down counter, a method using a counter and a digital comparator, etc. are known.

FIG. 1 shows a conventional example. After one stroke of the digital input 1, a square wave pulse shown in FIG. The digital duty ratio conversion circuit 5 is supplied with the base wall voltage from the reference power supply 4 and the clock pulse from the clock generator 3. The rectangular pulse output shown in Fig. 2 (4) is a pulse width modulation type in which the period T is constant and the time TV to reach Hi level is varied according to the digital input. The square pulse output shown is of a frequency modulation type in which the pulse field Tl is constant and the period TV is varied in proportion to the reciprocal of the digital input.

In such conventional devices, for example, 12-bit D-
When manufacturing an A converter, set the clock frequency & fe to 40
Assuming 96 KHz, the frequency f of the square pulse output is 096. If the low-pass filter is configured with one OR stage, the time constant τ must be set to about 1 second in order to keep the output ripple within 1/2 LSB.
The response time until the output of the A converter enters the 1/2LS13 requires approximately 9 seconds. As the number of bits of digital input increases, the response time becomes longer.

The object of the present invention is to provide 1 no h even when the number of bits increases.
It is an object of the present invention to provide a D-A converter that has a sufficiently high response speed and a low ripple content.

The D-A converter of the present invention is a converter in which a digital input of multiple r bits is converted into a serial pulse signal having a predetermined peak value, and the duty of the pulse changes in accordance with the value of the digital input. The circuit is divided into a conversion circuit relating to the upper plurality of bits of the digital input and a conversion circuit relating to the lower number bits (characterized in that it is provided with means for substantially weighting and adding the outputs of each conversion circuit). It is said that

Examples of the present invention will be described below based on Figure mI.

FIG. 3 shows a block diagram of an embodiment of the present invention.

A duty conversion circuit 5A for the upper bits and a low-pass filter 6A for smoothing its square pulse output, and a duty conversion circuit 5B for the lower bits and a low-pass filter 6B for smoothing its square pulse output are provided,
The reference *M4 and the clock generator 6 are shared by the two duty conversion circuits 5A and 5B. When the digital input is 12 pits, for example, the upper 4 bits are input to the upper duty conversion circuit 5A, and the remaining 8 bits are input to the lower 4 et duty conversion circuit 5B. Low pass filters 6A and 6
The weighted outputs of B are added by an adder circuit 8 and output to an analog output line 7. The weighting coefficient of the adder circuit 8 is such that when the upper 4 bits are set to 1, the lower 8 bits are set to K = 1.
It becomes 1/16. Therefore, the feedback circuit resistance R=IKQ
In this case, by setting R1=1−11R2=16KQ, the gain of the upper 4 bits becomes 1 and the gain of the lower 8 bits becomes 1/16.

In such a configuration, the upper 4 bits and throat frequencies el/
l is the clock frequency kfC=4096KH as in the conventional example
If z, then it becomes. Furthermore, if the same CR single-stage low-pass filter as the conventional example is used, the ripple will be reduced to 1/4LS for 12 bits.
If the time constant τl is suppressed to B, that is, 1/16384, the time constant τl will be 8 milliseconds, and the time until entering 1/4 LSB will be about 80 milliseconds. Next, for the remaining lower 8 bits, a circle 56 is output at frequency f2 = knee = 16, but the full scale output of the lower 8 bits is 8 bits in total, which is the full scale output of the upper 4 bits. Since it only has the blessings of 1 12 bits 4.096 16, the ripple content can be allowed up to 16 times, so 1/4LSBX16 = 4L
SB is allowed, the time constant τ2 becomes 8ms, and τl=
It becomes τ2.

In the end, the output of the adder circuit 8 is the added value of these two outputs, so the ripple is 6, which is the same as before, and the time constant is the same for both, but the response time is 80 ms. 8 Comparing this to the conventional example, it means that the time has been shortened to about 1/100.

In the above embodiment, the circuit is divided into upper 4 bits and lower 8 bits, but if the digital input bits of the lower duty conversion circuit are increased by doubling p(b) in this way, the time constant of each stage becomes τ are equal to each other, and the technical idea of the present invention can be implemented most effectively. Examples of such bit number division configurations include a 3-bit + 6-bit division configuration for a total of 9 bits, a 3-stage configuration of 2 bits + 4 bits + 8 bits for a total of 14 bits, and a total of 18 bits. In this case, a two-stage configuration of 6 bits + 12 bits is used. Generally speaking, the upper bit is N and the lower bit is 2 × N1 where n = 0.1.2.3. −・・
- is preferable.

FIG. 4 shows an embodiment in which the duty conversion circuit is divided into t-3 stages when the digital input is 14 bits. As mentioned above, it is divided into upper 2 bits, middle 4 bits, and lower 8 bits. In this case, when the weighting coefficient is weighted by 1, the resistance value R1°R2+R3 of the adding circuit and the gain of the adding circuit are as follows. However, the resistance value R of the feedback circuit is set to R=IKΩ as in the case of FIG.

Relationship tNK Input resistance Gain upper 2 bits I RI=IK! Q 1 middle 4 bits 1/4R2 = 4 to Ω single 4 lower 8 bits) 1/64 R3 = 64KQ 1/64 In the present invention, the addition means is not limited to the addition circuit as described above. , in WfR terms, it is possible to use a means of performing addition and checking. FIG. 5 shows an embodiment in which the reference power supply voltage supplied to duty conversion circuits 5A, 5B, and 5C is marketed. This embodiment has the same division (li configuration) as the one in FIG. , a voltage proportional to the cr gain, that is, 1/4E, is supplied to the duty conversion circuit 5B relating to the middle 4 bits, and 1/64B is supplied to the duty conversion circuit 5C relating to the lower 8 bits. As a means for this purpose, the reference voltage #!4 is divided by a series circuit of resistors R1r, R2e, and R3 and supplied to each duty change circuit.Examples of each resistance value are as follows: R1=IKΩ, R2=3KΩ
, R,3=60. The adder circuit 9 is designed to perform stepless addition.

As a low-pass filter in the present invention, the above-mentioned OR
Of course, in addition to the filter, other known smoothing means, such as a G-bore active filter, can be used.

According to the present invention, a D-A converter with high sugar content and relatively fast response can be obtained at low cost.

Furthermore, as is generally well known, since an A-D converter can be constructed by using a D-A converter in a feedback circuit, the D-A converter of the present invention can be applied to achieve high precision and It is ideal for use in electronic balances, etc. to obtain an inexpensive A-D converter.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing a conventional example, and FIG. 2 is a circuit block diagram showing a conventional example. Fig. 3G--Circuit block diagram showing an embodiment of the present invention; Fig. 4 is a circuit block diagram showing an embodiment of the present invention; Fig. 5 is a circuit block diagram showing yet another embodiment of the present invention. It is a diagram. 1...Digital input lines 5A, 5B, 5C! ...Duty conversion amount In
6A, 6B, 60...Low pass fino [ri8・
...Weighting is added to the circuit 9... Addition circuit patent applicant Shimadzu Corporation

Claims (2)

[Claims] (1) A conversion circuit that converts a multi-bit digital input into a serial pulse signal having a predetermined peak value, and in which the duty of the pulse changes in accordance with the value of the digital input, is connected to the upper plurality of the digital inputs. At least two including a conversion circuit related to bits and a conversion circuit related to lower multiple bits.
1. A D-A converter, characterized in that it is disassembled into more than one set of conversion circuits, and is provided with means for substantially weighting and adding the outputs of each conversion circuit. (2) The DA converter according to claim 1, wherein the number of lower bits is greater than the number of upper bits.