JPH03196280A - Multi-input operational amplifier circuit and integrating circuit using the amplifier circuit - Google Patents

Multi-input operational amplifier circuit and integrating circuit using the amplifier circuit

Info

Publication number
JPH03196280A
JPH03196280A JP1335896A JP33589689A JPH03196280A JP H03196280 A JPH03196280 A JP H03196280A JP 1335896 A JP1335896 A JP 1335896A JP 33589689 A JP33589689 A JP 33589689A JP H03196280 A JPH03196280 A JP H03196280A
Authority
JP
Japan
Prior art keywords
input
operational amplifier
amplifier circuit
circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1335896A
Other languages
Japanese (ja)
Other versions
JPH0547868B2 (en
Inventor
Hiroshi Kondo
寛 近藤
Tsuneo Toyama
遠山 恒夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toko Inc
Original Assignee
Toko Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toko Inc filed Critical Toko Inc
Priority to JP1335896A priority Critical patent/JPH03196280A/en
Publication of JPH03196280A publication Critical patent/JPH03196280A/en
Publication of JPH0547868B2 publication Critical patent/JPH0547868B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To process the addition and the subtraction at one time by using a voltage/current converter containing an emitter negative feedback resistance and a differential amplifier set at the output stage of the voltage/current converter. CONSTITUTION:A voltage/current converter A which converts the input signal voltage into a logarithmic function is provided together with a differential amplifier B having high gains which secures the single output from the output of the converter A. Thus an operational amplifier circuit is obtained. A signal input stage converts the input signal voltage into a differential current via the emitter negative feedback resistances R1 and R2 and supplies the differential current to a diode D2. Then a transistor differential pair is biased with the forward voltage of the diode D2. Thus the single output is obtained. Thus an accurate operation is secured despite a high impedance of a signal source.

Description

【発明の詳細な説明】 (産業上の利用分野〕 本発明は、超広帯域な半導体集積回路に好適であって、
殊に、加算器、積分器、或いはアクティブ・フィルタ等
に適した多入力演算増幅回路に関するものである。
[Detailed Description of the Invention] (Industrial Application Field) The present invention is suitable for ultra-wideband semiconductor integrated circuits, and includes:
In particular, it relates to multi-input operational amplifier circuits suitable for adders, integrators, active filters, etc.

[従来例〕 第7図は、−船釣な演算増幅回路を加算回路として用い
た場合の従来例を示した回路図である。
[Conventional Example] FIG. 7 is a circuit diagram showing a conventional example in which a conventional operational amplifier circuit is used as an adder circuit.

図に於いて、入力端子30.乃至30sには、夫々入力
信号電圧■1.乃至■、Nが印加され、演算増幅器A。
In the figure, input terminal 30. From 30s to 30s, the input signal voltage 1. to ■, N is applied, and operational amplifier A.

の反転入力端子と入力端子30.乃至309間に重み付
は用の複数の抵抗Rffl乃至R3Nが接続されており
、反転入力端子と出力端子5間に負帰還抵抗R4゜が接
続されている。抵抗R31乃至R3,4に流れる電流1
1乃至iNは、次のように表される。
Inverting input terminal and input terminal 30. A plurality of weighting resistors Rffl to R3N are connected between the inverting input terminal and the output terminal 5, and a negative feedback resistor R4° is connected between the inverting input terminal and the output terminal 5. Current 1 flowing through resistors R31 to R3,4
1 to iN are expressed as follows.

l =i、+i2−t−−−−−・・+iN!+  −
Vll/R311L =L□/Rsz。
l = i, +i2-t---+iN! + −
Vll/R311L =L□/Rsz.

・−’ N −V I N/ R11N従って、抵抗L
l乃至R3Nに流れる電流iI乃至i、は、帰還抵抗R
4゜に流れる。その電流をiとすると、出力電圧■。は
、次式のように表される。
・-' N -V I N/ R11N Therefore, resistance L
The currents iI to i flowing through l to R3N are feedback resistors R
Flows at 4°. If the current is i, then the output voltage is ■. is expressed as the following equation.

■。−−R4゜i −−R1゜(i、+i2 +  −・−−−+ i N
)−R4o(Vz/R:+++V+z/R:+z+−十
V I 、、/ RxN) ・・−一−−−・−−−−−(1) 第7図に示した一般的な演算増幅回路による加算回路は
、上記の式から明らかなように多数の入力電圧に、夫々
外付けの抵抗R31乃至R3Nによる任意の重み付けを
行って加算するようになされている。通常、これらの抵
抗R3+乃至R3Nは、プリント基板にチップ抵抗器等
を実装して構成されている。
■. −−R4゜i −−R1゜(i, +i2 + −・−−−+ i N
)-R4o (Vz/R:+++V+z/R:+z+-1VI,,/RxN) ・・−1−−−・−−−−−−(1) General operational amplifier circuit shown in Fig. 7 As is clear from the above equation, the adding circuit according to the above is configured to add arbitrary weights to a large number of input voltages using external resistors R31 to R3N, respectively. Usually, these resistors R3+ to R3N are constructed by mounting chip resistors or the like on a printed circuit board.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第7図のような一般の演算増幅回路を用いた加算回路は
、信号入力段に比較的大きな抵抗が付加される為に、信
号源インピーダンスが極めて高くなる欠点がある。即ち
、入力インピーダンスが極めて高い演算増幅回路となる
欠点がある。又、この演算増幅回路を積分回路として用
いた場合もその反転入力端子に積分定数の一つの因子と
なる抵抗が付加されており、従って、このような演算増
幅回路による加算回路或いは積分回路を用いたアクティ
ブ・フィルタ、殊に、梯子型のアクティブ・フィルタ等
のように多段にこの種の演算増幅回路が接続される場合
には、入力段に抵抗が接続される為に、信号源インピー
ダンスの影響を受は易くなり、正確な演算が行えなくな
る欠点がある為に、これらの抵抗を可能な限り小さなも
のとして用いるか、或いはアクティブ・フィルタ等には
、使用できない場合があった。
An adder circuit using a general operational amplifier circuit as shown in FIG. 7 has a drawback that the signal source impedance becomes extremely high because a relatively large resistance is added to the signal input stage. That is, there is a drawback that the operational amplifier circuit has extremely high input impedance. Also, when this operational amplifier circuit is used as an integrating circuit, a resistor is added to its inverting input terminal, which is a factor of the integral constant. When an operational amplifier circuit of this type is connected in multiple stages, such as in a ladder-type active filter, the influence of the signal source impedance may be affected because a resistor is connected to the input stage. Because of this disadvantage, it is necessary to use these resistors as small as possible, or they cannot be used in active filters or the like.

且つ、演算増幅回路の入力段に発生する寄生容量と、抵
抗R31乃至RffNが接続される為に高周波帯域の周
波数特性を劣化させる欠点がある。
Moreover, since the resistors R31 to RffN are connected to the parasitic capacitance generated at the input stage of the operational amplifier circuit, there is a drawback that the frequency characteristics in the high frequency band are deteriorated.

更に、第7図に示したような加算回路は、位相反転型の
加算回路であって負の信号が加算されている例を示して
いるが、正の信号を加算する場合には、この加算回路の
出力段に更に正の信号を加算する加算回路を付加する必
要があり、構造上も定数計算の上でも極めて複雑な回路
となる欠点がある。
Furthermore, the adder circuit shown in Fig. 7 is a phase inversion type adder circuit and shows an example in which negative signals are added, but when adding positive signals, this addition It is necessary to add an adder circuit for adding a positive signal to the output stage of the circuit, which has the drawback of making the circuit extremely complicated both in terms of structure and constant calculation.

又、第7図に示すように重み付は用の抵抗R21乃至R
AINは、外付けのチップ抵抗器となる為に、従来の演
算増幅回路では、部品数が増す欠点がある。
In addition, as shown in FIG.
Since AIN is an external chip resistor, conventional operational amplifier circuits have the disadvantage of increasing the number of components.

本発明は、上述のような欠点を改善するべくなされたも
ので、その主な目的は、信号源インピーダンスが高くと
も正確な演算が可能であって、多段に演算増幅回路が接
続される加算器、積分器、或いはアクティブ・フィルタ
等に好適な演算増幅回路を提供するものである。
The present invention has been made to improve the above-mentioned drawbacks, and its main purpose is to provide an adder that can perform accurate calculations even when the signal source impedance is high, and that has operational amplifier circuits connected in multiple stages. , an integrator, an active filter, and the like.

本発明の他の目的は、加算と減算が同時に処理が可能な
演算増幅回路を提供するものである。
Another object of the present invention is to provide an operational amplifier circuit capable of processing addition and subtraction simultaneously.

(課題を解決する為の手段) 本発明の多入力演算増幅回路は、複数の入力端子を具え
、複数の入力信号電圧をその入力信号に対応した数のエ
ミッタ負帰還抵抗を具え、それらのエミッタ負帰還抵抗
を介して入力信号電圧を対数関数を有する差動電流に変
換する電圧電流変換器と、該電圧電流変換器の出力を単
一出力として得るトランジスタ差動対とその能動負荷回
路からなる差動増幅器から構成されたものである。
(Means for Solving the Problems) A multi-input operational amplifier circuit according to the present invention is provided with a plurality of input terminals, a number of emitter negative feedback resistors corresponding to the input signals, and a number of emitter negative feedback resistors corresponding to the input signals. Consists of a voltage-current converter that converts the input signal voltage into a differential current having a logarithmic function via a negative feedback resistor, a differential pair of transistors that obtains the output of the voltage-current converter as a single output, and its active load circuit. It consists of a differential amplifier.

〔作用〕[Effect]

本発明の多入力演算増幅回路は、信号入力段が入力信号
電圧をエミッタ負帰還抵抗を通して差動電流に変換し、
その差動電流がダイオードに流れるようになされ、その
ダイオードの順方向電圧によってトランジスタ差動対を
バイアスして単一出力を得るものである。
In the multi-input operational amplifier circuit of the present invention, the signal input stage converts the input signal voltage into a differential current through the emitter negative feedback resistor,
The differential current is caused to flow through the diode, and the forward voltage of the diode biases the differential pair of transistors to obtain a single output.

〔実施例〕〔Example〕

第1図は、本発明に係る演算増幅回路を説明する為の一
実施例である。
FIG. 1 is an embodiment for explaining an operational amplifier circuit according to the present invention.

第1図の演算増幅回路は、入力信号電圧を対数関数に変
換する電圧電流変換器Aと電圧電流変換器への出力から
単一出力を得る高利得の差動増幅器Bで構成されている
。1,2は反転入力端子、3.4は正転入力端子、5は
出力端子であって、6.7が夫々電源電圧端子、接地端
子である。
The operational amplifier circuit shown in FIG. 1 is composed of a voltage-current converter A that converts an input signal voltage into a logarithmic function, and a high-gain differential amplifier B that obtains a single output from the output to the voltage-current converter. 1 and 2 are inverting input terminals, 3.4 is a normal input terminal, 5 is an output terminal, and 6.7 is a power supply voltage terminal and a ground terminal, respectively.

先ず、電圧電流変換器Aについて説明する。反転入力端
子1,2は、コレクタを共通接続したトランジスタQ、
、Q、のベースに夫々接続され、それらのトランジスタ
Q、、Qtのエミッタに電流源回路8,9が夫々接続さ
れている。正転入力端子3.4は、コレクタを共通接続
したトランジスタQ3.Q、のベースに夫々接続され、
それらのトランジスタQ3.Q、のエミッタに電流源回
路10゜11が夫々接続されている。電源電圧端子6は
、ダイオードD、のカソードに接続され、ダイオードD
、のカソードは、ダイオードD2.0:lのアノードに
接続され、ダイオードDi、D3のカソードが夫々トラ
ンジスタQ、、Q、のコレクタの共通接続点とトランジ
スタQ3.Q、のコレクタの共通接続点に接続されてい
る。トランジスタQ、とQ3のエミッタ間にエミッタ負
帰還抵抗R、が接続され・ トランジスタQ2とQ4の
エミッタ間には、エミッタ負帰還抵抗R2が接続され゛
ている。
First, the voltage-current converter A will be explained. Inverting input terminals 1 and 2 are transistors Q whose collectors are commonly connected;
, Q, and the emitters of these transistors Q, , Qt are connected to current source circuits 8 and 9, respectively. The normal input terminal 3.4 is connected to a transistor Q3.4 whose collectors are commonly connected. connected to the base of Q, respectively,
Those transistors Q3. Current source circuits 10 and 11 are connected to the emitters of Q and Q, respectively. The power supply voltage terminal 6 is connected to the cathode of the diode D.
The cathodes of diodes D2.0:l are connected to the anodes of diodes D2.0:l, and the cathodes of diodes Di, D3 are connected to the common connection point of the collectors of transistors Q, , Q, respectively, and transistors Q3. Q, is connected to the common connection point of the collectors of Q. An emitter negative feedback resistor R is connected between the emitters of transistors Q and Q3, and an emitter negative feedback resistor R2 is connected between the emitters of transistors Q2 and Q4.

電圧電流変換器Aの出力段である差動増幅器Bは、トラ
ンジスタ差動対をなすトランジスタQs。
The differential amplifier B, which is the output stage of the voltage-current converter A, includes a transistor Qs forming a differential pair of transistors.

Q6の共通接続されたエミッタと電源電圧端子6間に定
電流源回路12が接続され、それらのコレクタにトラン
ジスタQ、、Q、からなる能動負荷回路が接続されてい
る。トランジスタQ、、Q、のコレクタは共通接続され
、出力端子5に接続されている。トランジスタQ5は、
そのベースがダイオードD2とトランジスタQ、、Q、
のコレクタとの接続点に接続されている。トランジスタ
Q6は、そのベースがダイオードD、とトランジスタQ
3゜Q4のコレクタの接続点に接続され、夫々バイアス
されている。出力端子5と接地端子7間には、負荷回路
R4が接続されている。
A constant current source circuit 12 is connected between the commonly connected emitters of Q6 and the power supply voltage terminal 6, and an active load circuit consisting of transistors Q, , Q is connected to their collectors. The collectors of the transistors Q, ,Q, are commonly connected and connected to the output terminal 5. Transistor Q5 is
Its base is diode D2 and transistor Q, ,Q,
is connected to the connection point with the collector. Transistor Q6 has a diode D at its base and a transistor Q
It is connected to the connection point of the collector of 3°Q4 and is biased respectively. A load circuit R4 is connected between the output terminal 5 and the ground terminal 7.

第1図の実施例に於いて、入力端子1.3間の電圧を■
1とし、入力端子2.4間の電圧を■2とする。エミッ
タ負帰還抵抗R,,R,に流れる差動電流を夫々I+、
Izすると、差動電流1.、I。
In the embodiment shown in Figure 1, the voltage between input terminals 1 and 3 is
1, and the voltage between input terminals 2 and 4 is 2. The differential currents flowing through the emitter negative feedback resistors R, , R, are respectively I+,
If Iz, the differential current 1. ,I.

は、次式のような関係式で表される。is expressed by the following relational expression.

1+ −V+ /R+  −−−・・−・−−−−−−
−−−−−(2)I z = V 2 / Rz  −
−−−−−−−−−−−(3)又、定電流源回路8乃至
11に流れる定電流をI、、とすると、トランジスタQ
1乃至Q4のコレクタ電流は、夫々(1,、−11)、
(In−I2)、(1,。
1+ −V+ /R+ −−−・・−・−−−−−−
−−−−−(2) I z = V 2 / Rz −
−−−−−−−−−−−(3) Also, if the constant current flowing through the constant current source circuits 8 to 11 is I, then the transistor Q
The collector currents of Q1 to Q4 are (1,, -11), respectively.
(In-I2), (1,.

+ 1 +)、(1,+ It)と表される。従って、
これらのコレクタ電流が加算されて入力端子V、、V2
がダイオードD2.D3によって対数変換され、順方向
電流IA、1.とじて得られる。
+ 1 +), (1, + It). Therefore,
These collector currents are added to the input terminals V, , V2
is diode D2. Logarithmically transformed by D3, the forward current IA, 1. Obtained by binding.

IA=21.、− (1,+ Iz )  −−m−−
−−(4)L =21fi+ (It +Iz )  
−・−・−・・−(5)又、ダイオードD2.D3のカ
ソード間の電位差をΔVとすると、 ΔV−Vt In (Is + IA)と表される。
IA=21. , − (1, + Iz ) −−m−−
--(4)L =21fi+ (It +Iz)
−・−・−・・−(5) Also, diode D2. If the potential difference between the cathodes of D3 is ΔV, it is expressed as ΔV−Vt In (Is + IA).

一方、差動増幅器Bの差動対トランジスタQs。On the other hand, the differential pair transistor Qs of the differential amplifier B.

Q6のコレクタ電流は、定電流源回路12に流れる電流
を21.とじ、信号電流をΔiとすると、夫々Nx−Δ
i)、(lx+Δi)の電流が流れることになる。そし
て、トランジスタQ、、Q、のコレクタの電位差Δ■は
、 と表される。
The collector current of Q6 is the current flowing through the constant current source circuit 12. When the signal current is Δi, Nx-Δ
i), a current of (lx+Δi) will flow. The potential difference Δ■ between the collectors of the transistors Q, , Q, is expressed as follows.

従って、(6)式と(7)式から、次式のように表され
る。
Therefore, from equations (6) and (7), it is expressed as the following equation.

ここで、I、+12をIcとすると、(8)式は、次式
のように表される。
Here, when I and +12 are Ic, the equation (8) is expressed as the following equation.

21、 −1c     lx  −Δ1(9)式から
信号電流Δiを求めると、と表され、00)式に(2)
式と(3)式を代入すると、1゜ と表される。
21, −1c lx −Δ1 When the signal current Δi is determined from the formula (9), it is expressed as 00) and the formula (2)
Substituting the equation and equation (3), it is expressed as 1°.

従って、負荷回路RLに流れる出力電流2ΔiをIoと
すると、出力電流I0は、01)式より、r、−2Δ 
i X −−・ (V+  / R+   +  Vz  / 
Rz  )  −・−02)r、1 と表される。
Therefore, if the output current 2Δi flowing through the load circuit RL is Io, the output current I0 is determined by r, -2Δ
i X --- (V+ / R+ + Vz /
Rz ) −・−02) r, 1 .

02)式から出力電流I。には、エミッタ負帰還抵抗R
1,’ Rzの因子が含まれ、且つ入力電圧が電流に変
換されて、加算されることが明らかに示されている。
02) Output current I from the formula. is the emitter negative feedback resistor R
It is clearly shown that a factor of 1,' Rz is included and that the input voltages are converted to currents and summed.

一方、第2図の実施例は、電圧電流変換回路Aが第1図
の実施例とは異なり、夫々のコレクタを共通接続したト
ランジスタロ11乃至Q I Nに対称にトランジスタ
Q z +乃至Q!Nが配置されており、これらのトラ
ンジスタのベースに夫々入力端子1゜乃至is、3.乃
至3Nが接続され、トランジスタロ11乃至Q I N
のエミッタに電流源回路8.乃至8Nが接続され、トラ
ンジスタQ z +乃至Q 2Nのエミッタに電流源回
路10.乃至10Mが接続されている。対称的に配置さ
れているトランジス75口乃至Q1NとQ z +乃至
Q zNが夫々のエミッタ間にエミッタ負帰還抵抗R1
1乃至RIMが接続されている。尚、出力段の差動増幅
RWBは、第1図の実施例の構成と同一である。
On the other hand, in the embodiment shown in FIG. 2, the voltage-current conversion circuit A is different from the embodiment shown in FIG. N are arranged, and input terminals 1° to is, 3. 3N are connected, transistors 11 to Q I N
A current source circuit is connected to the emitter of 8. 8N are connected to the emitters of the transistors Q z + to Q 2N, and a current source circuit 10. 10M are connected. Transistors 75 to Q1N and Q z + to Q zN arranged symmetrically form an emitter negative feedback resistor R1 between their respective emitters.
1 to RIM are connected. Incidentally, the differential amplifier RWB in the output stage has the same configuration as the embodiment shown in FIG.

第2図の実施例は、電圧電流変換器Aが入力端子1.乃
至IN、31乃至3Hが複数個具えられた多入力演算増
幅回路の他の実施例である。入力端子11と3.乃至I
Nと3.4の間の電圧を夫々■、乃至V9とすると、こ
の実施例の出力電流I。
In the embodiment of FIG. 2, the voltage-current converter A has input terminals 1. This is another embodiment of a multi-input operational amplifier circuit including a plurality of IN to IN and 31 to 3H. Input terminals 11 and 3. ~I
Assuming that the voltages between N and 3.4 are 1 and V9, respectively, the output current I of this embodiment is.

は、02)式から推定して第2図の実施例に於いても次
式のように表すことができる。
can be estimated from equation 02) and expressed as the following equation in the embodiment of FIG.

T。T.

Io −m−・(V l/ n z +−−−−−+ 
VN /RIN)■、。
Io −m−・(V l/nz +−−−−−+
VN/RIN)■,.

θω 03)式に示されるようにエミッタ負帰還抵抗R乃至R
INによって入力電圧相互間に重み付けがなされて加算
される。
θω 03) As shown in the formula, the emitter negative feedback resistors R to R
The input voltages are weighted and added by IN.

第3図の実施例では、第1図の多入力演算増幅回路の反
転入力端子の一端に出力電圧■。が帰還された負帰還回
路である。正転入力端子21,22に、入力電圧V、、
V、が印加され、反転入力端子23には、入力電圧■3
が入力されている。出力端子5から出力電圧■。が出力
され、同時に出力電圧■。が反転入力端子の一端に帰還
されている。第3図の実施例をシグナル図で記載すると
、第4図のように表すことができる。
In the embodiment shown in FIG. 3, the output voltage ■ is applied to one end of the inverting input terminal of the multi-input operational amplifier circuit shown in FIG. is a negative feedback circuit. The input voltage V, , is applied to the normal rotation input terminals 21 and 22.
V, is applied, and the input voltage ■3 is applied to the inverting input terminal 23.
is entered. Output voltage from output terminal 5■. is output, and at the same time the output voltage ■. is fed back to one end of the inverting input terminal. If the embodiment shown in FIG. 3 is described using a signal diagram, it can be expressed as shown in FIG. 4.

第4図のシグナル図に基づいて、第3図の実施例につい
て説明する。第1図の実施例は、電流動作型であるが、
電圧に変換して第4図のシグナル図を示して、その出力
電圧■。は、次式のように表される。
The embodiment shown in FIG. 3 will be described based on the signal diagram shown in FIG. 4. The embodiment shown in FIG. 1 is a current-operated type, but
Convert it to voltage and show the signal diagram in Figure 4, and its output voltage ■. is expressed as the following equation.

Vo −A −At(Vi  ”−Vo)+A −AX
(V2−13)(但し、A + 、 A 2は、電圧電
流変換回路Aの入力段に具えられたトランジスタ対と、
それらのトランジスタのエミッタ間に接続されたエミッ
タ負帰還抵抗とからなる差動対の増幅率) ここで、A2 /A、”’  k  とすると、]二記
の式は、次式のように表される。
Vo −A −At(Vi ”−Vo)+A −AX
(V2-13) (However, A + and A 2 are a transistor pair provided in the input stage of the voltage-current conversion circuit A,
The amplification factor of the differential pair consisting of the emitter negative feedback resistor connected between the emitters of these transistors) Here, A2 /A, ``'k'' The two equations can be expressed as the following equation. be done.

vo=V、  4−kL −kVi (但し、A、/A、=にとし、1/A−A、が略零であ
って、A・A、)1とする。) ここで、k=1とすると、出力電圧■。は、■ 。  
−■ 1 −ト Vz      Vs   −−−−
−−−0ωと表される。
vo=V, 4-kL -kVi (However, A, /A, =, 1/A-A, is approximately zero, and A.A,)1. ) Here, if k=1, the output voltage ■. ■.
−■ 1 −to Vz Vs −−−−
---It is expressed as 0ω.

従って、第3図の実施例の示すように本発明の多入力演
算増幅回路を接続することよって、本発明の多入力演算
増幅回路は、加算と減算が同時に処理することが可能と
なる。
Therefore, by connecting the multi-input operational amplifier circuit of the present invention as shown in the embodiment of FIG. 3, the multi-input operational amplifier circuit of the present invention can process addition and subtraction simultaneously.

第5図の実施例は、多入力演算増幅器の正転入力端子が
共通接続され、反転入力端子の一端に入力信号v3が入
力され、他の反転入力端子に出力電圧■。が帰還される
ように接続されている。この場合の実施例では、その出
力電圧■。は、次式のように表される。
In the embodiment shown in FIG. 5, the non-inverting input terminals of the multi-input operational amplifier are commonly connected, the input signal v3 is input to one end of the inverting input terminal, and the output voltage ■ is input to the other inverting input terminal. is connected so that it is returned. In this case, the output voltage ■. is expressed as the following equation.

■。= (1+k)V、−kV3 に−1とすると、 V o= 2 V 、  −V 、  −−−−−−−
−−−−−−041と表される。この実施例では、入力
信号電圧■。
■. = (1+k)V, -kV3 is set to -1, then V o = 2 V , -V , ----------
------041. In this example, the input signal voltage ■.

を二倍に増幅して電圧電流増幅器Aに入力することが可
能になることを示している。
This shows that it is possible to double the voltage and input it to the voltage/current amplifier A.

第6図の実施例は、多入力演算増幅器の正転入力端子2
1.22に、夫々入力電圧V、、V2が印加され、反転
入力端子の夫々に出力電圧V0が帰還される応用例であ
って、この実施例の出力電圧■。は、次式のように表さ
れる。
The embodiment shown in FIG. 6 is the normal input terminal 2 of a multi-input operational amplifier.
1.22 is an application example in which input voltages V, , V2 are applied to each, and output voltage V0 is fed back to each inverting input terminal, and the output voltage of this embodiment is (2). is expressed as the following equation.

k=1とすると、 と表すことができる。If k=1, It can be expressed as.

更に、図示されていないが、第3図の実施例の出力端子
3と接地間にコンデンサCを接続することによって、多
入力演算増幅回路は、積分回路として用いることができ
る。出力電圧■。は、03)式のように表される。従っ
て、 Vo = V + 十Vz−V3 =  Vi −−−
−−03)”と表される。
Furthermore, although not shown, by connecting a capacitor C between the output terminal 3 of the embodiment of FIG. 3 and ground, the multi-input operational amplifier circuit can be used as an integrating circuit. Output voltage■. is expressed as in equation 03). Therefore, Vo = V + 10Vz-V3 = Vi ---
--03)".

出力端子5にコンテンツCが接続されているので、出力
電圧■。は、次式のように表される。
Since content C is connected to output terminal 5, the output voltage is ■. is expressed as the following equation.

(但し、多入力演算増幅回路の相互コンダククンスg 
rnは、gm=x7rと表される。Cはコンデンサの容
量である。) 従って、03)式と06)式より、伝達関数としては、
V、     V、  →−V2   V:l    
  5Cr00′ と表される。
(However, the mutual conductance g of a multi-input operational amplifier circuit
rn is expressed as gm=x7r. C is the capacitance of the capacitor. ) Therefore, from equations 03) and 06), the transfer function is:
V, V, →-V2 V:l
It is expressed as 5Cr00'.

従って、多入力演算増幅回路の内部抵抗rは、次式のよ
うに表すことができる。
Therefore, the internal resistance r of the multi-input operational amplifier circuit can be expressed as follows.

q′7)式から明らかなように、多入力演算増幅回路の
定電流lx、Inを変化することによって、積分定数を
可変することができる。斯かる積分回路は、アクティブ
・フィルタとして応用することが可能であり、従来の積
分回路より、信号源インピーダンスを低くすることがで
きる為に、この積分回路を多段に接続したとしても、高
周波特性は、極めて良好なものとすることができる。
As is clear from equation q'7), the integral constant can be varied by changing the constant current lx, In of the multi-input operational amplifier circuit. Such an integrating circuit can be applied as an active filter, and the signal source impedance can be lowered than that of conventional integrating circuits, so even if this integrating circuit is connected in multiple stages, the high frequency characteristics will be , it can be made extremely good.

(効果〕 上述のように本発明の多入力演算回路は、エミッタ負帰
還抵抗を具える電圧電流変換器とその出力段の差動増幅
器で形成され、斯かる多入力演算増幅回路によれば、加
算と減算が同時に処理可能な、加算減算回路が極めて簡
単な回路で形成することが可能である。又、重み付けの
為の外付けの抵抗器が不要である為に、信号源インピー
ダンスは、極めて小さなものとすることができる。従っ
て、斯かる多入力演算回路で、加算回路或いは積分回路
等が容易に形成することが可能であり、これらの回路を
多段に接続して、アクティブ・フィルタ等を形成するこ
とが可能である。
(Effects) As described above, the multi-input operational amplifier circuit of the present invention is formed of a voltage-current converter equipped with an emitter negative feedback resistor and a differential amplifier at its output stage, and according to this multi-input operational amplifier circuit, It is possible to form an addition/subtraction circuit that can process addition and subtraction simultaneously using an extremely simple circuit.Also, since no external resistor is required for weighting, the signal source impedance is extremely low. Therefore, adding circuits, integrating circuits, etc. can be easily formed using such multi-input arithmetic circuits, and these circuits can be connected in multiple stages to form active filters, etc. It is possible to form.

更に、本発明の多入力演算増幅回路は、エミッタ負帰還
抵抗を用いて差動電流を得る為に、外付けの抵抗器が少
なくて済み、部品点数を低減することが可能であると共
に、抵抗間に発生する寄生容量を低減することが可能で
あり、又、外付は抵抗を低減することができる為に、高
周波特性を改善することが可能であり、高周波用のアク
ティブ・フィルタ等に極めて効果的である。
Furthermore, since the multi-input operational amplifier circuit of the present invention obtains a differential current using emitter negative feedback resistors, the number of external resistors can be reduced, and the number of components can be reduced. It is possible to reduce the parasitic capacitance that occurs between the two, and since external resistance can be reduced, it is possible to improve high frequency characteristics, making it extremely useful for high frequency active filters, etc. Effective.

【図面の簡単な説明】 第1図は、本発明に係る多入力演算増幅回路の一実施例
を示す回路図、第2図は、本発明に係る多入力演算増幅
回路の他の実施例を示す回路図、第3図、第5図、第6
図は、多入力演算増幅回路の応用例を説明する為の回路
図、第4図は、第3図のシグナル図、第7図は、従来の
演算増幅回路を用いた加算回路の一例を示す回路図であ
る。 △:電圧電流変換回路、B二差動増幅器、■、2:反転
入力端子、3,4:正転入力端子、5:出力端子、6:
電源電圧端子、7:接地端子、8乃至12;定電流源回
路。
[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit diagram showing one embodiment of the multi-input operational amplifier circuit according to the present invention, and FIG. 2 is a circuit diagram showing another embodiment of the multi-input operational amplifier circuit according to the present invention. Circuit diagrams shown in Figures 3, 5, and 6
The figure is a circuit diagram for explaining an application example of a multi-input operational amplifier circuit, Figure 4 is a signal diagram of Figure 3, and Figure 7 is an example of an adder circuit using a conventional operational amplifier circuit. It is a circuit diagram. △: Voltage-current conversion circuit, B two differential amplifier, ■, 2: Inverting input terminal, 3, 4: Normal input terminal, 5: Output terminal, 6:
Power supply voltage terminal, 7: ground terminal, 8 to 12: constant current source circuit.

Claims (7)

【特許請求の範囲】[Claims] (1)複数の入力信号電圧が夫々供給される複数の入力
端子を具え、該入力端子に対応した数のエミッタ負帰還
抵抗を介して対数関数電流に変換する電圧電流変換器と
、該電圧電流変換器の出力によってバイアスされるトラ
ンジスタ差動対と該トランジスタ差動対の能動負荷回路
からなり、出力端子から該電圧電流変換器の出力を単一
出力とする差動増幅器とからなることを特徴とする多入
力演算増幅回路。
(1) A voltage-current converter comprising a plurality of input terminals to which a plurality of input signal voltages are respectively supplied, and converting the voltage into a logarithmic function current through a number of emitter negative feedback resistors corresponding to the input terminals; It is characterized by consisting of a differential pair of transistors biased by the output of the converter and an active load circuit of the differential pair of transistors, and a differential amplifier that outputs the output of the voltage-current converter as a single output from an output terminal. Multi-input operational amplifier circuit.
(2)前記多入力演算増幅回路の反転入力端子の一つを
該多入力演算増幅回路の出力端子に接続して負帰還回路
を形成したことを特徴とする特許請求の範囲第1項記載
の多入力演算増幅回路。
(2) A negative feedback circuit is formed by connecting one of the inverting input terminals of the multi-input operational amplifier circuit to an output terminal of the multi-input operational amplifier circuit. Multi-input operational amplifier circuit.
(3)前記多入力演算増幅回路の反転入力端子の一つの
入力端子を該多入力演算増幅回路の出力端子に接続して
負帰還回路を形成し、正転入力端子と他の反転入力端子
を入力信号電圧の加算或いは減算の為の入力端子とした
ことを特徴とする特許請求の範囲第1項記載の多入力演
算増幅回路。
(3) Connect one of the inverting input terminals of the multi-input operational amplifier circuit to the output terminal of the multi-input operational amplifier circuit to form a negative feedback circuit, and connect the normal input terminal and the other inverting input terminal to the output terminal of the multi-input operational amplifier circuit. 2. The multi-input operational amplifier circuit according to claim 1, wherein the multi-input operational amplifier circuit is used as an input terminal for adding or subtracting input signal voltages.
(4)前記多入力演算増幅回路の反転入力端子の一つの
入力端子を該多入力演算増幅回路の出力端子に接続して
負帰還回路を形成し、正転入力端子の少なくとも二つを
共通接続した接続点と、他の反転入力端子を入力信号電
圧の加算と減算の為の入力端子としたことを特徴とする
特許請求の範囲第1項記載の多入力演算増幅回路。
(4) One of the inverting input terminals of the multi-input operational amplifier circuit is connected to the output terminal of the multi-input operational amplifier circuit to form a negative feedback circuit, and at least two of the normal input terminals are connected in common. 2. The multi-input operational amplifier circuit according to claim 1, wherein the connection point and the other inverting input terminal are used as input terminals for adding and subtracting input signal voltages.
(5)複数の入力信号電圧をエミッタ負帰還抵抗を介し
て対数関数電流に変換する多数の入力端子を具える電圧
電流変換器と、該電圧電流変換器の出力を単一出力化す
る該電圧電流変換器の出力によってバイアスされるトラ
ンジスタ差動対と該トランジスタ差動対の能動負荷回路
とからなる差動増幅器から構成された多入力演算増幅回
路と、該差動増幅器の出力端子と接地間に接続されたコ
ンデンサとからなることを特徴とする多入力演算増幅回
路を用いた積分回路。
(5) A voltage-current converter comprising a large number of input terminals that converts a plurality of input signal voltages into logarithmic function currents via an emitter negative feedback resistor, and a voltage-current converter that converts the output of the voltage-current converter into a single output. A multi-input operational amplifier circuit consisting of a differential amplifier consisting of a differential pair of transistors biased by the output of a current converter and an active load circuit for the differential pair of transistors, and a circuit between the output terminal of the differential amplifier and ground. An integrating circuit using a multi-input operational amplifier circuit, characterized in that it consists of a capacitor connected to a capacitor.
(6)入力信号電圧を対数関数電流に変換する電圧電流
変換器を入力段に具え、該電圧電流変換器の出力から単
一出力を得るトランジスタ差動対と能動負荷回路からな
る差動増幅器から構成された演算増幅回路であって、該
電圧電流変換器が、第1のダイオードのカソードに第2
と第3のダイオードのアノードが夫々接続され、該第2
のダイオードのカソードに第1と第2のトランジスタの
コレクタが夫々接続され、該第3のダイオードのカソー
ドに第3と第4のトランジスタのコレクタが夫々接続さ
れ、該第1乃至第4のトランジスタのエミッタに夫々電
流源回路が接続され、該第1と該第3のトランジスタの
エミッタ間に第1のエミッタ負帰還抵抗が接続され、該
第2と該第4のトランジスタのエミッタ間に第2のエミ
ッタ負帰還抵抗が接続され、該第1と該第2のトランジ
スタのベースを夫々第1と第2の反転入力端子とし、該
第3と該第4のトランジスタのベースを夫々第1と第2
の正転入力端子とし、且つ、該第2のダイオードと該第
1と該第2のトランジスタとの接続点が前記トランジス
タ差動対の一方のトランジスタのベースに接続され、該
第3のダイオードと該第3と該第4のトランジスタとの
接続点が該トランジスタ差動対の他方のトランジスタの
ベースに接続されてなることを特徴とする多入力演算増
幅回路。
(6) A differential amplifier consisting of a differential pair of transistors and an active load circuit, which has a voltage-current converter in its input stage that converts the input signal voltage into a logarithmic function current, and obtains a single output from the output of the voltage-current converter. an operational amplifier circuit configured such that the voltage-to-current converter has a cathode of a first diode connected to a second diode;
and the anode of the third diode are connected, respectively, and the second
The collectors of the first and second transistors are connected to the cathode of the third diode, respectively, the collectors of the third and fourth transistors are connected to the cathode of the third diode, and the collectors of the first to fourth transistors are connected to the cathode of the third diode. A current source circuit is connected to each emitter, a first emitter negative feedback resistor is connected between the emitters of the first and third transistors, and a second negative feedback resistor is connected between the emitters of the second and fourth transistors. An emitter negative feedback resistor is connected, the bases of the first and second transistors are used as first and second inverting input terminals, respectively, and the bases of the third and fourth transistors are used as the first and second inverting input terminals, respectively.
a normal input terminal of the transistor, and a connection point between the second diode and the first and second transistors is connected to the base of one transistor of the transistor differential pair; A multi-input operational amplifier circuit, characterized in that a connection point between the third and fourth transistors is connected to the base of the other transistor of the differential pair of transistors.
(7)複数の入力信号電圧を対数関数電流に変換する電
圧電流変換器を入力段に具え、該電圧電流変換器の出力
から単一出力を得るトランジスタ差動対と能動負荷回路
からなる差動増幅器から構成された多入力演算増幅回路
であって、該差動増幅器の出力端子と接地端子間にコン
デンサを接続した積分回路を形成したことを特徴とする
特許請求の範囲第6項記載の多入力演算増幅回路を用い
た積分回路。
(7) The input stage is equipped with a voltage-current converter that converts a plurality of input signal voltages into logarithmic function currents, and a differential transistor consisting of a differential pair of transistors and an active load circuit obtains a single output from the output of the voltage-current converter. The multi-input operational amplifier circuit according to claim 6, characterized in that the multi-input operational amplifier circuit is constituted by an amplifier, and an integrating circuit is formed by connecting a capacitor between the output terminal and the ground terminal of the differential amplifier. An integration circuit using an input operational amplifier circuit.
JP1335896A 1989-12-25 1989-12-25 Multi-input operational amplifier circuit and integrating circuit using the amplifier circuit Granted JPH03196280A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1335896A JPH03196280A (en) 1989-12-25 1989-12-25 Multi-input operational amplifier circuit and integrating circuit using the amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1335896A JPH03196280A (en) 1989-12-25 1989-12-25 Multi-input operational amplifier circuit and integrating circuit using the amplifier circuit

Publications (2)

Publication Number Publication Date
JPH03196280A true JPH03196280A (en) 1991-08-27
JPH0547868B2 JPH0547868B2 (en) 1993-07-19

Family

ID=18293584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1335896A Granted JPH03196280A (en) 1989-12-25 1989-12-25 Multi-input operational amplifier circuit and integrating circuit using the amplifier circuit

Country Status (1)

Country Link
JP (1) JPH03196280A (en)

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