JPH11271367A - Circuit for detecting electric field intensity - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce parts constituting a circuit and lessen the danger of self oscillation by connecting collectors of three transistors with loads, emitters with a constant current source and a base of the third transistor with a reference voltage source and including an integration circuit in one load. SOLUTION: Transistors Q1 , Q2 and a constant current source I1 constitute a differential amplifier. Transistors Q1 , Q3 , the constant current source I1 and a reference voltage source Vref constitute a rectification circuit. Transistors Q4 , Q5 as a current mirror circuit input a collector current IC3 flowing in the transistor Q3 to an integration circuit. In the constitution, when the reference voltage Vref is higher than a base voltage VBE1 of the transistor Q1 , only the transistor Q3 operates. When the reference voltage Vref is lower than the base voltage VBE1 the transistors Q1 , Q2 operate. A constant current I0 becomes almost collector current IC1 , IC2 of the transistors Q1 , Q2 . The circuit can be used as a simple differential amplifier having the transistors Q1 , Q2 as differential inputs at this time. All of the transistors Q1 , Q3 operate at a middle range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field strength detection circuit, and more particularly to a field strength detection circuit for radio waves in mobile communication.

[0002]

2. Description of the Related Art As shown in FIG. 18, a conventional electric field strength detection circuit is constituted by combining several stages of an intermediate frequency amplification (IFamp) block and a rectification circuit block. Usually, the rectifier circuit block is often called an RSSI circuit, but the original RSSI means an electric field strength detection function,
In order to function as an SI circuit operation, the entire circuit configuration of FIG. 18 is required.

FIG. 19 is a circuit diagram more specifically showing a basic block of an electric field intensity detection circuit comprising an intermediate frequency amplification block and a rectification circuit block, which is a unit circuit of the conventional electric field intensity detection circuit of FIG. Shown in A dotted line indicates an intermediate frequency amplification block (having a differential amplifier circuit configuration with IFamp), and a dashed line indicates a rectifier circuit (half-wave rectifier circuit). The conventional RSSI circuit is constructed by connecting several stages in series by the method of FIG. 18 using FIG. 19 as a basic block (FIG. 20 shows an example of two-stage connection).

[0004] In mobile communication, a mobile terminal receives a radio wave of a constant level transmitted from a fixed base station, so that the reception level (electric field strength) greatly varies. Causes of this fluctuation include the moving speed of the mobile device, the influence of extraneous noise, the influence of reflection from buildings, and the like. This is called fading, and it is impossible to predict the amount of fluctuation.

[0005] Therefore, in a general mobile terminal, it is necessary to always detect the electric field level of the received radio wave and determine the state. This technology is an indispensable function in mobile communication.

This can be always detected as an electric field level of a radio wave if an output characteristic (RSSI characteristic) proportional to a change in reception input level is obtained.

[0007]

As described above, since the conventional RSSI circuit uses a plurality of units each including an intermediate frequency amplifier (IFamp) and a rectifier circuit in series, the unit configuration is complicated. There are problems that a large number of components and the cost for the components are increased in the circuit configuration, and there is a possibility that self-oscillation may occur.

The present invention has been made to solve these problems and to provide an electric field intensity detection circuit having a small number of components and no self-oscillation.

[0009]

A basic form of an electric field strength detection circuit according to the present invention comprises a first transistor of a first type having a collector connected to a first load and an emitter connected to a constant current source. , A second transistor of a first type having a collector connected to a second load and an emitter connected to the constant current source, and base electrodes of the first and second transistors receiving an intermediate frequency input. And a first transistor of a first type having an emitter connected to the constant current source, a collector connected to the third load, and a base connected to the first constant voltage source, and It is composed of a basic unit in which a circuit including an integrating circuit is connected to one of the third loads.

A typical load including the integrating circuit is a second transistor of a second type having a collector and a base connected to the collector of the third transistor, and a base having a base of the fourth transistor. And a current mirror-connected second type fifth transistor whose collector is connected to the integrating circuit.

In some cases, a direct integration circuit is used as a load.

Further, the first through third transistors
A plurality of units are connected in series with each other as a unit, the collector of the first transistor of the preceding unit is connected to the base of the first transistor of the succeeding unit, and the second connection of the preceding unit is made. Forming a multi-stage connection by connecting the collector of the transistor to the base of the second transistor of the subsequent unit and connecting the collector of the third transistor of each unit to a common load connecting to the integrating circuit; It is a desirable embodiment to have an adding circuit that adds the maximum current of each unit and outputs the addition result to an integrating circuit.

According to another embodiment of the present invention, a collector of the first type is connected to a first connection point via a first resistor, and an emitter of the first type is connected to a constant current source. A transistor and a collector connected to the first transistor via a second resistor;
And a second transistor of a first type having an emitter connected to a constant current source, a base electrode of the first and second transistors to which an intermediate frequency input is input, and an emitter connected to A third transistor connected to the constant current source, a collector connected to a first constant voltage, and a base connected to the first constant voltage; and a collector connected to the first transistor.
A fourth transistor of a second type having a base connected to the first connection point, a base connected to the first connection point, and a collector connected to the integration circuit. The second embodiment of the present invention also includes an electric field strength detection circuit having at least one set of circuits in which the first transistor and the fifth transistor of the first type make a current mirror connection.

In this embodiment, as in the first embodiment, an integration process by multistage connection and stepwise output addition is desirable.

[0015]

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1A shows an electric field strength detection circuit according to the present invention.
FIG. 1 is a circuit diagram showing a first embodiment of a basic circuit (hereinafter, referred to as an RSSI circuit). That is, the first, second and third
Transistors Q1, Q2, and Q3 are connected to the first, second, and third loads, respectively, to the collector, the emitter is connected to the constant current source I1, and the IF frequency is input to the bases of the transistors Q1 and Q2. Is connected to the reference voltage source, and the integrating circuit is connected to any of the first, second, and third loads.

The basic unit block (hereinafter referred to as the basic block) of the RSSI circuit according to the present invention has the configuration shown in FIG. 1A and is the most typical first embodiment shown in FIG.
The first embodiment will be described with reference to the configuration shown in FIG.

In FIG. 1C, transistors Q1,
A differential amplifier is composed of a block of Q2, resistors R1 and R2 and a constant current source I1, and transistors Q1, Q2 and Q
3. A rectifier circuit is configured by a block of the constant current source I1 and the reference voltage source Vref. The transistors Q4 and Q5 are current mirror circuits, and input a collector current flowing through the transistor Q3 to an integrating circuit. The integration circuit integrates and smoothes the AC current component and converts it to a DC component.

Further, the circuit shown in FIG.
The second embodiment used for the third load shown in FIG.
This case corresponds to the purpose of use for reinverting the output.

As a third embodiment, a practical RSSI circuit is constructed by connecting the basic blocks shown in FIG.

The connection in this case is made as shown in FIG. FIG. 2A shows an example of two-stage connection, in which multi-stage connection is performed through connection lines extending from the collectors of the second-stage transistors Q6, Q7, and Q8 to the subsequent unit.

FIG. 2B shows a portion in which a direct integrating circuit is used as a common load for the transistors Q3 and Q8 instead of the circuit using the current mirror connection of the transistors Q4 and Q5 shown in FIG. 2A. This is the fourth embodiment, in which the circuit does not consider the conversion of the phase of the sum of the collector currents of the transistors Q3 and Q8.

The operation of the basic block of the RSSI circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram for explaining the operation of the basic block of the first embodiment of the RSSI circuit of the present invention. In FIG. 3, the collector currents of the transistors Q1, Q2, and Q3 are denoted by IC1, IC2, and IC3, respectively.
1 and Q2 are respectively VBE1, VBE2,
Assuming that the base voltage of the transistor Q3 is Vref (reference voltage source) and the constant current source is Io, the relational expressions (1) and (2) between IC1 and IC3 using VBE1 and Vref as variables, and VBE2 and Vref as variables IC2 and IC3
As is well known, the following expressions hold for the relational expressions (3) and (4).

Here, VT = KT / q (q: electron charge, K: Boltzmann's constant, T: absolute temperature) It is known that VT２５26 mV at 25 ° C. FIG. 4A is a graph showing the relations of the equations (1) to (4).
It is represented as

The horizontal axis of FIG. 4A is VBE1-Vref for the transistor Q1, VBE2-Vref for the transistor Q2, and the horizontal axis scale unit is VT. The vertical axis is the collector current, and the vertical scale unit is I
o. As is clear from FIG.
When Vref is sufficiently higher than VBE1,
Only the transistor Q3 operates (Io of the constant current source is
Almost IC3). Region C is when Vref is sufficiently lower than VBE1 and transistor Q
1 and Q2 only operate, and Io of the constant current source is almost
C1 and IC2. In this region, the transistor Q
It can also be used as a simple differential amplifier having 1, Q2 as a differential input. In region B, transistors Q1,
Both Q2 and Q3 operate.

With respect to the B region, FIGS.
This will be described with reference to FIG. To make the description easier to understand,
The transistor Q2 will be ignored. As shown in FIG. 4B, when a sine wave (solid line) is input to the base of the transistor Q1 (with respect to the horizontal axis of the graph), if the base voltage Vref of the transistor Q3 is fixed, the base voltage of the transistor Q3 Changes relative to the base voltage of the transistor Q1 as shown by a broken line. FIG. 4C shows the characteristics obtained by converting these voltage changes into current changes (with respect to the vertical axis of the graph). In response to the change in the input voltage of the transistor Q1, the collector current IC1 changes as shown by the solid line. Corresponding to this, the collector current IC3 changes as indicated by the dashed line. The above explanation is
2 was ignored, but actually both Q1 and Q2 operate.

When the transistors Q1 and Q2 are differentially input, the collector current changes as shown in FIG. When the collector current IC1 (in-phase input) changes as indicated by the solid line, the collector current IC2 (inverted input) changes as indicated by the broken line. The corresponding change in the collector current IC3 is as shown on the right. In FIG. 4C, the collector current IC
1. It is clear if one considers that IC2 has changed independently.

FIG. 4D will be described in more detail. FIG. 5 shows the transistors Q1, Q
2 input voltage level versus output current (collector current IC1,
IC2, IC3). In FIG. 5, the horizontal axis represents the transistors Q1, Q2 in both FIGS. 5 (a) and 5 (b).
The input voltage level (differential input level) of Q2 is shown.
The leftmost graph shows the input level = 0 (no signal),
This shows that the differential input level increases as the position shifts to the right. The vertical axis indicates the output current,
FIG. 5A shows output currents of the transistors Q1 and Q2,
FIG. 5B shows the output current of the transistor Q3. In FIG. 5A, when the differential input level of the transistors Q1 and Q2 increases, the output current changes from left to right, and as shown in FIG. 4, no current flows beyond the reference current source Io. The collector currents of the transistors Q1 and Q2 are saturated as shown in the rightmost diagram of FIG. The corresponding change in the collector current IC3 is shown in FIG.
(B), the collector current IC3 decreases as the input levels of the transistors Q1 and Q2 increase.

FIG. 6 shows a differential input level pair of the transistors Q1 and Q2 and an integrated value characteristic of the collector current IC3 of FIG. 5B. As shown in FIG. 6, as the input level increases, the integral output decreases.

Next, consider the case where the RSSI circuit basic blocks of the present invention are connected as shown in FIG. The connection method between the stages (for example, the first stage and the second stage connection) is implemented as shown in FIG. In FIG. 2, when a signal is input to the transistors Q1 and Q2 (Vin in FIG. 7),
The signal of the collector current of Q2 is amplified and output.
In this circuit, the transistor Q1 has an opposite-phase output, and the transistor Q2 has an in-phase output. The amplified signal is input to the second-stage differential input (the bases of the transistors Q6 and Q7), and the signals are further amplified and output from the collectors of the transistors Q6 and Q7.

In FIG. 7, the first-stage input signal Vin
, The amplitude increases in the later stage. However, since the signal output level does not exceed the power supply voltage, the input signal is saturated without being amplified above a certain level.

FIG. 8 shows the input level of the input signal Vin and the output (current output) characteristic of each stage in FIG.
As described with reference to FIG. 6, the output level decreases as the input level increases. In FIG. 8, the fifth input level is
Since it is the largest compared to the other stages, it saturates fast at the low input level. Since the first-stage input level is the smallest as compared with the other stages, it does not saturate unless the input level is high. The output current of each stage is added by an adder circuit and rectified by an integrating circuit, whereby a characteristic as shown by a solid line (fine line) shown in FIG. 8 can be obtained.

FIG. 9A is a basic circuit diagram of a fifth embodiment representing the second embodiment of the RSSI circuit of the present invention. The difference between the first embodiment and the first embodiment shown in FIG. 1A is that the collector of the transistor Q3 is directly connected to Vc.
c, and that the transistors Q1 and Q2 are connected via the resistors R3 and R4 respectively to the addition transistor Q4 between the connection point between the other end of the resistors R3 and R4 and Vcc. The basic operating principle is shown in FIG.
Same as (c). The operation of this circuit is shown in FIG.
0, FIG. 11 and the drawings described in the first embodiment will be described together.

FIG. 10 is a circuit diagram for explaining the operation principle of the second embodiment. In FIG. 10, the collector currents of the transistors Q1, Q2 and Q3 are respectively represented by IC
1, IC2, and IC3, the base voltages of the transistors Q1 and Q2 are VBE1 and VBE2, respectively, the base voltage of the transistor Q3 is Vref (reference voltage source), and the constant current source is Io.
The relationship between C1 and IC3 and the relationship between IC2 and IC3 using VBE2 and Vref as variables are the same as in the equations (1) to (4) described in the first embodiment, and thus will not be described. Also, the VI characteristic graph relating to this equation is the same as that in FIG.

The difference from the first embodiment (FIG. 3) is that
Since IC1 + IC2 = IC4, this point will be described with reference to another drawing.

FIG. 11 shows the relationship between the input voltage level of the transistors Q1 and Q2 and the output current (collector currents IC1, IC2 and IC4) with respect to the circuit diagram 10. First
Although the description of the same points as in FIGS. 5A and 5B described in the embodiment is omitted, when the transistors Q1 and Q2 change as shown in FIG.
Since there is a relationship of 1 + IC2, IC4 changes as shown in FIG.

FIG. 12 shows the transistor Q of FIG.
1, the Q2 input level versus the IC4 output current integration characteristic.
Unlike the first embodiment, the output current integral increases in proportion to the increase in the input level.

FIG. 9B shows a circuit in which an integrating circuit is directly connected in place of the current mirror connection between Q4 and Q5 of the basic circuit shown in FIG. 9A.
Same as (a), without phase reversal.
Example.

Next, the characteristics when the basic circuit of the fifth embodiment shown in FIG. 9A is connected in multiple stages similar to FIG. 7 of the first embodiment will be described. Fifth Embodiment of Second Embodiment
The connection of the circuit of this embodiment is performed as shown in FIG.

FIG. 13 shows an example of a two-stage connection of the basic units shown in FIG. 9A, which is the seventh embodiment.

FIG. 14 shows that the load of each block is R3 and R3.
The eighth embodiment is an embodiment in which the connection point with No. 4 is connected to one integration circuit.

FIG. 15 shows the relationship between the input level of the input signal Vin and the output of each stage in the case of multi-stage connection as shown in FIG.
(Current output) characteristics. As described with reference to FIG. 12, the output level increases as the input level increases. In FIG. 15, since the fifth-stage input level is the largest as compared with the other stages, it saturates first at a low input level. Since the first-stage input level is the smallest as compared with the other stages, it does not saturate unless the input level is high. The output current of each stage is added by an adder circuit and rectified by an integrating circuit to obtain a characteristic shown by a solid line (thin line) shown in FIG.

FIG. 16A includes at least a capacitor in the connection between the collectors of the first and second transistors from the collectors of the first and second transistors to the base of the succeeding transistor in the third embodiment shown in FIG. 2A. This is a circuit according to the ninth embodiment in which a bias circuit is inserted, and this configuration is a circuit expected to suppress abnormal oscillation.

As a tenth embodiment, a voltage follower circuit is inserted as shown in FIG. 16B, which is effective in stabilizing the circuit at high frequencies.

FIG. 17A shows a bias circuit including at least a capacitor in the connection between the collectors of the first and second transistors and the base of the succeeding transistor in the unit connection of the eighth embodiment shown in FIG. This is the circuit of the eleventh embodiment inserted, and this configuration is a circuit expected to have the effect of suppressing abnormal oscillation.

Further, as a twelfth embodiment, a voltage follower circuit is inserted as shown in FIG. 17 (b), which is effective for stabilizing the circuit at a high frequency.

[0047]

A first effect of the structure of the present invention described above is that the possibility of oscillation is significantly reduced as compared with the conventional circuit configuration. The reason is that a general intermediate frequency amplifier has a high total gain of 100 dB or more.
Unless the wiring is done with the utmost care in the routing of the input / output wiring and the isolation, etc., oscillation will easily occur. That is, the more complicated the connection between the amplification blocks of each stage and the interface to the rectifier circuit, the easier the oscillation. In the present invention, the number of constituent elements is significantly reduced, and the interface portion and the like are simplified, so that the possibility of oscillation is significantly reduced as compared with the conventional circuit.

The second effect is that higher integration can be achieved than in a conventional circuit. The reason for this is that the number of elements is significantly reduced and simplified.

The third effect is that power consumption can be reduced as compared with the conventional circuit. The reason is that the circuit configuration is simplified.

[Brief description of the drawings]

FIG. 1A is an explanatory diagram of a basic circuit of a first embodiment of an electric field strength detection circuit according to the present invention, FIG. 1B is a diagram showing a first embodiment as a basic block, and FIG. 2 for the third load
FIG. 11 is a diagram showing a third embodiment using two current mirror connections.

2A is a circuit diagram of a third embodiment having a two-stage connection configuration of the basic blocks shown in FIG. 1C, and FIG. 2B is a circuit diagram showing currents of transistors Q4 and Q5 in FIG. 2A. FIG. 14 is a diagram showing a load portion of a circuit diagram of a fourth embodiment using an integrating circuit instead of a mirror connection.

FIG. 3 is an explanatory diagram of the principle of the basic block shown in FIG. 1;

4A is a diagram showing a relationship between a collector current for each collector and a differential input of the basic block shown in FIG. 1, and FIG. 4B is a diagram showing a base voltage change of transistors Q1 and Q3 with respect to a sine wave input; (C) is a diagram illustrating a characteristic obtained by converting the voltage change into a current change, and (d) is a diagram illustrating a change in the IC3 when a differential input between the transistors Q1 and Q2 is input.

FIG. 5A is a diagram showing the input level at the base of the transistors Q1 and Q2 versus the output current characteristic at the collector, and FIG. 5B is a diagram showing the characteristic of the output current at the collector of the transistor Q3 at that time.

FIG. 6 is a graph showing the input level of transistors Q1 and Q2 shown in FIG. 5 versus the output current of transistor Q3.

FIG. 7 is an explanatory diagram showing a stage-wise output addition connection of a multistage connection by the basic unit of the present invention.

8 is a current characteristic diagram showing an integrated output of the adder circuit in the case of the multi-stage connection shown in FIG.

9A is a circuit diagram of a fifth example as a basic block of a second embodiment of the electric field strength detection circuit of the present invention, and FIG. 9B is a diagram illustrating transistors Q4 and Q5 of FIG. 9A. FIG. 13 is a diagram showing a portion of the sixth embodiment in which an integrating circuit is directly connected instead of the Karen and Mailer connection of FIG.

FIG. 10 is an explanatory diagram of a basic block of the second embodiment shown in FIGS. 9A and 9B.

11A is a diagram showing input level versus output current characteristics of transistors Q1 and Q2 of the second basic block shown in FIG. 9A, and FIG. 11B is a diagram showing output current characteristics of a combined output current IC4 at that time; FIG.

12 is a diagram showing the input current level of the transistors Q1 and Q2 of the basic block shown in FIG. 9A versus the output current characteristic of IC4.

FIG. 13 is a circuit diagram of a seventh embodiment showing a two-stage connection of the basic blocks shown in FIG. 9 (a).

14 is an eighth embodiment in which an integrating circuit is directly connected instead of the current mirror connection of the two-stage connection Q4 and Q5 shown in FIG.
FIG. 3 is a circuit diagram of the embodiment of FIG.

FIG. 15 is an explanatory diagram showing an integral output of an adder circuit in a stage-by-stage addition connection of five stages of the basic block shown in FIG. 9A.

FIG. 16A is a circuit diagram of a ninth embodiment in which a capacitor and a bias circuit are inserted as an insertion circuit in the connection between the first and second transistors in the block of the third embodiment shown in FIG. 2; 10B is a circuit diagram of a tenth embodiment in which the insertion circuit is a voltage follower circuit.

FIG. 17A is a circuit diagram of an eleventh embodiment in which a capacitor and a bias circuit are inserted as an insertion circuit in the connection between the first and second transistors in the block of the seventh embodiment shown in FIG. 14; 13B is a circuit diagram of a twelfth embodiment in which the insertion circuit is a voltage follower circuit.

FIG. 18 is a block diagram showing a conventional electric field strength detection circuit.

19 is a circuit diagram of a basic unit of the electric field strength detection circuit shown in FIG.

20 is a circuit diagram of a two-stage connection of the basic blocks shown in FIG.

Claims (17)

[Claims] 1. At least a first type comprising a first type
, Second and third transistors, first, second and third transistors.
An electric field intensity detection circuit having a load circuit, a first reference voltage source circuit, and a constant current source circuit, amplifying the input intermediate frequency, and rectifying the intermediate frequency amplification result. One of the second and third load circuits includes an integrating circuit, connecting the collector of the first transistor to the first load circuit, connecting the collector of the second transistor to the second load circuit, Connecting the collector of the third transistor to the third load circuit, connecting the emitter of the first transistor, the emitter of the second transistor, the emitter of the third transistor, and the constant current source; An electric field strength detection circuit for connecting the base of the transistor and the first reference voltage source circuit. 2. An intermediate frequency is input between the bases of the first and second transistors, the first and second loads are first and second resistors, respectively, and the base of the third transistor is A third reference load source, the third load is a second transistor of a second type having a collector and a base connected to the collector of the third transistor, and a base is the fourth transistor. 2. The electric field intensity detection circuit according to claim 1, wherein the electric field intensity detection circuit is a current mirror connection circuit including a second transistor connected to a base of the transistor and having a collector connected to the integration circuit. 3. At least the first, second, and third
, The first, second, and third load circuits, and the constant current source circuit as a unit, and a plurality of units are connected in series. An electrical circuit is connectably connected between the collector of the transistor and the base of the first transistor of the second unit following the collector of the transistor, and the collector of the second transistor of the first unit and the second circuit of the second unit. 2. A multi-stage connection is made by connecting an electric circuit between the bases of the transistors so that an electric circuit can be inserted and connecting the preceding unit and the succeeding unit.
An electric field strength detection circuit as described in the above. 4. The electric field detection circuit according to claim 3, wherein the base of the third transistor of each unit is connected to the same first reference voltage source in at least two units. 5. The electric circuit inserted between the first transistors and between the second transistors in the connection between the preceding unit and the unit succeeding the unit is an electric circuit including at least a capacitor. The electric field strength detection circuit according to claim 3. 6. The electric circuit inserted between the first transistor and the second transistor in the connection between the preceding unit and the unit following the unit includes at least a voltage follower circuit. The electric field strength detection circuit according to claim 3, wherein the electric field strength detection circuit is a circuit. 7. The collector of a third transistor of each unit is connected to a first connection point, and one first common circuit is connected to each unit as a third load via the first connection point. The electric field strength detection circuit according to claim 3, wherein the electric field strength detection circuits are commonly connected. 8. The electric field strength detection circuit according to claim 7, wherein the first common circuit serving as the common third load is an integration circuit. 9. The first common circuit serving as the common third load includes a fourth transistor of a second type having a collector connected to the collector of the third transistor, and a collector being an integrator circuit. And a current mirror connection circuit of a second type fifth transistor having a base connected to the base and collector of the fourth transistor.
An electric field strength detection circuit as described in the above. 10. The electric field strength detection circuit according to claim 9, wherein the first load and the second load in each unit connected in series are first and second resistors, respectively. 11. The third collector, wherein the other ends of the respective collectors of the first and second transistors are connected to a second connection point, and connected to a second common circuit via the second connection point. , And the emitters of the first, second, and third transistors are connected to a constant current source, and the first and second bases constitute an intermediate frequency differential input terminal. An electric field strength detection circuit in which a base of the third transistor is connected to the first reference voltage source. 12. The electric field strength detection circuit according to claim 11, wherein said second common circuit is an integration circuit. 13. A configuration in which the first and second loads of each of the succeeding units are connected to the input terminal of one of the integration circuits via the second connection point. 13. The electric field strength detection circuit according to claim 12, wherein the connection between the units of the first and second transistors forms a multistage connection by the connection according to claim 3. 14. The second common circuit includes a fourth transistor of a second type having a collector and a base connected to the second junction point, and a base having a base of the fourth transistor. 12. The electric field intensity detection circuit according to claim 11, wherein the current intensity detection circuit is a current mirror connection circuit including a second transistor connected to the integration circuit and a collector connected to the integration circuit. 15. The first and second loads of each unit are connected to a third and a fourth resistor connected to the collector of a respective transistor, and the other end of the third and the fourth resistor is connected to the second and the third resistors. 4. A connection between the first and second transistors of each unit, wherein the first and second transistors are connected to a connection point and are connected from the second connection point to an input terminal of one of the current mirror connection circuits. 15. A multi-stage connection is constituted by the connection described above.
An electric field strength detection circuit as described in the above. 16. The electric field strength detection circuit according to claim 1, wherein the integration circuit is a parallel connection circuit of a resistor and a capacitor. 17. An output current of each unit is added,
3. The electric field intensity detection circuit according to claim 2, further comprising an addition circuit that outputs the addition result to an integration circuit.