GB2336437A

GB2336437A - Field strength detection circuit

Info

Publication number: GB2336437A
Application number: GB9906441A
Authority: GB
Inventors: Tomohiro Fujii
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1998-03-20
Filing date: 1999-03-19
Publication date: 1999-10-20
Anticipated expiration: 2019-03-19
Also published as: GB9906441D0; AU2134399A; JP3616494B2; JPH11271367A; AU750998B2; GB2336437B

Abstract

A field strength detection circuit e.g. for mobile phones, has an extremely low possibility of self-oscillation and a reduced power dissipation, and is capable of being integrated at a larger scale. This circuit is comprised of first, second, and third transistors Q1-Q3 whose emitters are coupled together, which are driven by a common constant current sink 14 connected to the coupled emitters of the transistors Q1-Q3. First and second loads 11, 12 are connected to the collectors of the first two transistors Q1, Q2 and a third load 20 is connected to a collector of the third transistor Q3. The third load includes an integrator 21. An input voltage is applied across bases of the first and second transistors Q1-Q2 while a reference voltage 13 is applied to a base of the third transistor Q3. A rectified output current with respect to the input voltage is generated at the collector/drain of the third transistor and integrated by the integrator in the third load, thereby producing an output proportional to the level of the input voltage. The bipolar resistors shown may be replaced by FET's with source and drain replacing collector and emitter respectively. As an alternative the integrator may be connected to the loads 11 and 12 and several stages may be cascaded.

Description

2336437

ELECTRIC-FIELD STRENGTH DETECTION CIRCUIT

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electric-field strength detection circuit comprising bipolar transistors or Metal -Oxide-Semi conductor Field-Effect Transistors (MOSFETs) and more particularly, to an electric-field strength detection circuit for detecting the strength of the electric field of a radio wave or signal, which is applicable to a Received Signal Strength Indicator (RSSI) circuit designed for various mobile stations or terminals such as a cellular phone. 2. Description of the Prior Art

In the mobile communication systems, since a mobile 15 station receives a fixed-level radio wave or signal transmitted from a fixed base station, the level of the received radio wave or the electric-field strength of the received signal is likely to fluctuate within a comparatively wide range. This fluctuation is caused by some ef f ects such as the movement of the mobile station, external noises, and reflection of the radio wave by buildings. This phenomenon that the strength of the received signal fluctuates with time is termed the '%fading". It is impossible or extremely difficult to forecast the amount or level of fluctuation of the received electric- field strength.

Therefore, to realize the mobile communication, it is essential for the mobile station or terminal to detect always the level or strength of the electric-field of the received wave or signal and to notify the status of the received wave or signal. This need can be accomplished by producing an output signal proportional to the change of the level or strength of the received radio wave in a circuit. The circuit realizing this function has been termed a "RSSI circuit".

Fig. 1 shows a basic configuration of a conventional electric-f ield strength detection circuit or RSSI circuit applied to a mobile station such as a cellular phone.

In Fig. 1, the conventional RSSI circuit 101 is comprised of an Intermediate Frequency (IF) amplifier block 150 including cascadeconnected IF differential amplifiers 111 and 151 located at first to sixth stages, and a rectifier block 160 including rectifiers 112 located at the first to fourth stages and an integrator 113.

An input signal SIN, which is transmitted from a frequency mixer (not shown), is applied to the differential amplifier 111 located at the first stage, producing an amplified output signal Sol. The amplified output signal So, is applied to the dif f erential amplifier 111 located at the second stage, producing an amplified output signal S02. The amplified output signal 502 is applied to the differential amplifier 111 located at the third stage, producing an amplified output signal S03. The amplified output signal Soi is applied to the differential amplifier 111 located at the fourth stage, producing an amplified output signal S04 - The amplified output signal So4 is applied to the differential amplifier 151 located at the fifth stage, producing an amplified output signal S05. The amplified output signal Scs is applied to the dif f erential amplifier 151 located at the sixth stage, producing an amplified output signal SouT. The amplified output signal SouT is sent to a demodulator (not shown).

The amplified output signal So,, which is outputted from the differential amplifier 111 at the first stage, is further applied to the rectifier 112 located at the first stage, producing a rectified output signal Sal. Similarly, the amplified output signals S02, S03, and S041 which are respectively outputted from the differential amplifiers 111 located at the second to fourth stages, are further applied respectively to the rectifiers 112 located at the second to fourth stages, producing rectified output signals SR2, SR?, and SIL4.

The four rectified butput signals SRI, SR2, SR3, and SR4 thus produced are added to one another to be applied to the integrator 113. The integrator 113 produces an integrated output signal 5ROUT by integrating the sum of the rectified output signals SR1r SR2P SR3, and SR4. The integrated output signal SROUT thus produces is sent to a controller (not shown) for controlling a transmitting power of the mobile station or the like.

Only the rectifier block 160 has been often termed a RSSI circuit. However, the function of a RSSI circuit is actually realized not only by the rectifier block 160 but also by the IF amplifier block 15 0. Therefore, the combination of the rectifier block 160 and the amplifier block 150 should be termed a RSSI circuit.

From this point of view, the integrated output signal SROUT of the integrator 113 is equal to an output signal SRs51 of the conventional RSSI circuit or electric-f ield detection circuit 101 in Fig. 1. Fig. 2 shows a circuit configuration of the differential amplifier 111 and the rectifier 112 located at the first stage in Fig. 1. is In Fig. 2, the differential amplifier ill is comprised of a differential pair of npn-type bipolar transistors Q101 and Q102 whose emitters are coupled together, a constant current sink 114 sinking a constant current Ijol, and two load resistors R101 and R102 for the transistors Q101 and Q102, respectively. The 20 coupled emitters of the transistors Q101 and Q102 are connected to the ground through the constant current sink 114. Collectors of the transistors Q101 and Q102 are respectively connected through the resistors R101 and R102 to a power supply line applied with a power supply voltage Vcc. An input voltage V:- a, which is equal to the input signal SIN in Fig. 1, is differentially applied across bases of the transistors Q101 and Q102.

The rectifier 112 is comprised of a differential pair of npn-type bipolar transistors 0103 and Q104 whose emitters are coupled together, a constant current sink 115 sinking a constant current 1102, a pnp-type bipolar transistor Q105 whose collector and base are coupled together and which serves as a load of the transistor Q103, a differential pair of npn-type bipolar transistors Q107 and Q108 whose emitters are coupled together, a constant current sink 116 sinking a constant current 1103, and a pnp-type bipolar transistor Q109 whose collector and base are coupled together and which serves as a load of the transistor Q107.

The coupled emitters of the transistors Q103 and Q104 are connected to the ground through the constant current sink 115.

A collector of the transistor Q103 is connected to the coupled collector and base of the transistor Q105. An emitter of the transistor 0105 is connected to the power supply line of Vc:c. A collector of the transistor Q104 is directly connected to the power supply line of Vcc. A collector voltage of the transistor Q101 (i. e., a first amplifier output voltage) of the differential amplif ier 111 is applied to a base of the transistor Q103. A base of the transistor Q104 is applied with a fixed reference voltage Vr.f supplied by a reference voltage source 113.

The coupled emitters of the transistors Q107 and Q108 are connected to the ground through the constant current sink 116. A collector of the transistor Q107 is connected to the coupled collector and base of the transistor Q109. An emitter of the transistor Q109 is connected to the power supply line of Vcc. A collector of the transistor Q108 is directly connected to the power supply line of Vcc. A collector voltage of the transistor Q102 (i.e., a second amplified output voltage) of thedifferential amplifier 111 is applied to a base of the transistor Q107. Abase of the transistor Q108 is applied with the fixed reference voltage V.f supplied by the reference voltage source 113.

The coupled base and collector of the transistor Q105 and the coupled base and collector of the transistor Q109 are further coupled together, f rom which an amplif ied and f ull-wave rectif ied output current 1c), equal to the rectified output signal SPI, in Fig. 1 is derived.

The differential amplifiers 111 and the rectifiers 112 located at the second to fourth stages in Fig. 1 have the same configuration as those shown in Fig. 2. The differential amplifiers 151 located at the fifth and sixth stages in Fig- 1 have the same conf iguration as that of the dif f erential amplif ier 111 in Fig. 2.

Fig. 3 shows a circuit configuration of the conventional two-stage RS5I circuit shown in Fig. 1, in which two ones of the combination of the differential amplifier 111 and the rectifier 112 shown in Fig. 2 are cascade-connected at two stages. The operation is substantially the same as that of the circuit of Fig. 2 and therefore, the explanation about the circuit configuration of Fig. 3 is omitted here.

With the conventional electric-field strength detection circuit or RSSI circuit shown in Fig. 1, as described above, the differential amplifiers 111 in the IF differential amplifier block 150 and the rectifiers 112 in the rectifier block 160 have the circuit configuration shown in Fig. 2 or 3. As a result, there are the problems that (a) the circuit configuration is complicated, (b) the fabrication cost is high due to necessity of a lot of electronic elements or devices, and (c) the possibility of self-oscillation is high.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention to provide an electric-field strength detection circuit having an extremely low possibility of self -oscillation.

Another object of the present invention to provide an electric-f ield strength detection circuit that can be integrated on a larger scale.

Still another object of the present invention to provide an electric-field strength detection circuit having a reduced power dissipation.

The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.

According to a f irst aspect of the present invention, an electric-f ield strength detection circuit is provided, which is comprised of (a) first, second, and third transistors whose emitters/sources are coupled together; the first, second, and third transistors being driven by a common constant current; (b) a constant current source/sink for supplying /sinking the common constant current; the constant current source/sink being connected to the coupled emitters /sources of the first, second, and third transistors; (c) a first load connected to a collector/drain of the first transistor; (d) a second load connected to a collector/drain of the second transistor; (e) a third load connected to a collector/drain of the third transistor; the third load including an integrator; and (f) a reference voltage source for supplying a reference voltage.

An input voltage is applied across bases of the first and second transistors while the reference voltage is applied to a base of the third transistor. A rectified output current with respect to the input voltage is generated at the collector/drain of the third transistor and integrated by the integrator in the third load, thereby producing an output of the electric-field strength detection circuit proportional to the level of the input voltage.

With the electric-f ield strength detection circuit according to the first aspect of the present invention, first, this circuit is constituted by the first to third transistors, the constant current sourcelsink, the reference voltage source, the first and second loads for the first and second transistors, and the third load including the integrator for the third transistor. Therefore, the number of the necessary electronic components or devices is drastically decreased and at the same time, the input/output interfaces are simplified. As a result, the possibility or danger of self -oscillation is extremely low.

Second, since the number of the necessary electronic components or devices is drastically decreased and the input/output interfaces are simplified, the electric-field strength detection circuit according to the first aspect can be integrated on a larger scale than that of the conventional circuit.

Third, because the-circuit configuration is drastically simplified, the power dissipation can be reduced.

In a preferred embodiment of the circuit according to the first aspect, the third load includes a current mirror circuit. The rectified output current flows to the integrator through the current mirror circuit. There is an additional advantage that -g- the proportion coefficient (or inclination angle) of the output of the electric-field strength detection circuit can be easily adjusted by changing the mirror ratio of the current mirror circuit.

In another preferred embodiment of the circuit according to the first aspect, the integrator itself serves as the third load. There is an additional advantage that the circuit configuration is simplified.

According to a second aspect of the present invention, another electric-field strength detection circuit is provided, which is comprised of (a) first to n-th cascade-connected amplifier-rectifier circuits for generating first to n-th amplified output signals and first to n-th rectified output signals, respectively, where n is an integer greater than unity; (b) an adder for adding the first to n-th rectified output signals and producing an added output signal; and (c) a load having an integrator for integrating the added output signal to generate an output of the electric- field strength detection circuit.

Each of the first to n-th amplifier-rectifier circuits comprises (a-1) first, second, and third transistors whose emitters/sources are coupled together; the first, second, and third transistors being driven by a common constant current; (a-2) a constant 'current source/sink for suppl ying/s inking the common constant current; the constant current source/sink being connected to the coupled emitters /sources of the first, second, and third transistors; (a-3) a first load connected to a collector/drain of the first transistor; (a-4) a second load connected to a collector/drain of the second transistor; and (a-5) a reference voltage source for supplying a reference voltage.

An input voltage Is applied across bases of the first and second transistors while the reference voltage is applied to a base of the third transistor in the first amplifier-rectifier circuit. The output of the electric-field strength detection circuit is proportional to the level of the input voltage.

The configuration of the electric-field strength detection circuit according to the second aspect of the present invention is substantially equal to the cascade connection of a plurality of the electric-field strength detection circuits according to the first aspect of the present invention. Therefore, the circuit according to the second aspect has the same advantages as those in the circuit according to the first aspect.

There is an additional advantage that the level of the output of the electric-f leld strength detection circuit is easily raised and adjusted by changing the cascading number n of the amplifier- rectifier circuits, along with the same advantages as those in the circuit according to the first aspect.

In a preferred embodiment of the circuit according to the second aspect, the (n - 1)-th amplifier-rectifier circuit is directly connected to the n-th amplifier-rectifier circuit. There is an additional advantage that the circuit configuration is simplified.

In another preferred embodiment of the circuit according to the second aspect, the (n - 1) -th amplif ier-rectif ier circuit is connected to the n-th amplifier-rectifier circuit through a coupling circuit.

In this embodiment, it is preferred that the coupling circuit includes a coupling capacitor and a bias circuit. There is an additional advantage that any abnormal oscillation is suppressed. The coupling circuit may include a voltage follower circuit. There is an additional advantage that the operation at high frequency ranges can be stable.

According to a third aspect of the present invention, still another electric-f -ield strength detection circuit is provided, which is comprised of (a) first, second, and third transistors whose emitters /sources are coupled together; the first, second, and third transistors being driven by a common constant current; (b) a constant current source/sink for supplying/ sinking the common constant current; the constant current source/sink being connected to the coupled emitters/ sources of the f irst, second, and third transistors; (c) a first load connected to a collector/drain of the first transistor; (d) a second load connected to a collector/drain of the second transistor; the second load being connected to the first load at a connection point; (e) a third load connected to the connection point of the first and second loads; the third load including an integrator; and (f) a reference voltage source for 5 supplying a reference voltage.

An input voltage is applied across bases of the first and second transistors while the reference voltage is applied to a base of the third transistor. A rectified output current with respect to the input voltage is generated at the connection paint of the first and second loads and is integrated by the integrator in the third load, thereby producing an output proportional to the level of the input voltage.

With the electric-field strength detection circuit according to the third aspect of the present invention, because of the substantially same reason as that of the electric-field strength detection circuit according to the first aspect, there are the same advantages as those in the circuit according to the first aspect.

In a preferred embodiment of the circuit according to the third aspect, the third load includes a current mirror circuit. The rectified output current flows to the integrator through the current mirror circuit. The-re is an additional advantage that the proportion coefficient (or inclination angle) of the output of the electric-field strength detection circuit can be easily adjusted by changing the mirror ratio of the current mirror circuit.

In another preferred embodiment of the circuit according to the third aspect, the integrator itself serves as the third load. There is an additional advantage that the circuit configuration is simplified.

According to a fourth aspect of the present invention, a further electricf ield strength detection circuit is provided, which is comprised of (a) first to n-th cascade-connected amplifier-rectifier circuits for generating first to n-th amplified output signals and first to n-th rectified output signals, respectively, where n is an integer greater than unity; (b) an adder for adding the first to n-th recti f ied output signals and producing an added output signal; and (c) a load having an integrator for integrating the added output signal to generate an output of the electric-field strength detection circuit.

Each of the first to n-th amplifier-rectifier circuits comprises (a-1) first, second, and third transistors whose emitters/sources are coupled together; the first, second, and third transistors being driven by a common constant current; (a-2) a constant current source/sink for supplying/sinking the common constant current; the constant current source/sink being connected to the coupled emitters /sources of the first, second, and third transistors; (a-3) a first load connected to a collector/drain of the first transistor; (a-4) a second load connected to a collector/drain of the second transistor; the second load being connected to the first load at a connection point; and (a-5) a reference voltage source for supplying a reference voltage.

An input voltage is applied across bases of the first and second transistors while the reference voltage is applied to a base of the third transistor in the first amplifier-rectifier circuit. The output of the electric-field strength detection 10 circuit is proportional to the level of the input voltage.

In a preferred embodiment of the circuit according to the fourth aspect, the (n - 1)-th amplifier-rectifier circuit is directly connected to the nth amplifier-rectifier circuit. There is an additional advantage that the circuit configuration 15 is simplified.

In another preferred embodiment of the circuit according to the fourth aspect, the (n - 1) -th amplifier-rectif ier circuit is connected to the n-th amplifier-rectikier circuit through a coupling circuit.

In this embodiment, it is preferred that the coupling circuit includes a coupling capacitor and a bias circuit. There is an additional advantage that any abnormal oscillation is suppressed. The coupling circuit may include a voltage follower circuit. There is an additional advantage that the operation at -Is- high frequency ranges can be stable.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the present invention may be readily carried into effect, it will now be described with reference to the accompanying drawings.

Fig. 1 is a block diagram showing the basic configuration of a conventional electric-field strength detection circuit applicable to a mobile communication system.

Fig. 2 is a circuit diagram showing the differential amplifier and the rectifier located at the first stage of the conventional electric-field strength detection circuit shown in Fig. 1.

Fig. 3 is a circuit diagram showing a conventional twostage electric-field strength detection circuit having the basic configuration of Fig. 1, in which two ones of the combination of the differential amplifiers and the rectifiers shown in Fig. 2 are cascade- connected.

Fig. 4 is a circuit diagram showing the basic configuration of an electric-field strength detection circuit according to a first embodiment of the present invention.

Fig. 5 is a circuit diagram showing the configuration of the electricfield strength detection circuit according to the first embodiment of Fig. 4.

Fig. 6 is a circuit diagram showing the configuration of a third load used in an electric-f ield strength detection circuit according to a second embodiment of the present invention.

Fig - 7 is a circuit diagram showing the configuration of an electric-f ield strength detection circuit according to a third embodiment of the present invention.

Fig. 8 is a circuit diagram showing the configuration of an electric-field strength detection circuit according to a fourth embodiment of the present invention.

Fig. 9 is a circuit diagram showing a differential pair of the two bipolar transiators to explain the operation of the electric-f ield strength detection circuit according to the first embodiment of Fig. 5.

Fig. 10 is a graph showing the input-output characteristic of the differential pair shown in Fig. 9.

Figs. 11A to 11C are waveform diagrams of the base voltages of the f irst and second transistors, the base-to-emittex voltage of the third traniistor, and the collector currents of the first to third trainsistors, respectively.

Fig. 12A is a waveform diagram of the collector currents of the first and second third transistors.

Fig. 12B is a waveform diagram of the collector current of the third transistor.

Figs - 13A to 13D are waveform diagrams of the collector currents of the first and second transistors at the different levels of the input voltage, respectively.

Figs. 14A to 14D are waveform diagrams of the collector current of the third transistor at the different levels of the input voltage, respectively.

Fig. 15 is a graph showing the input-output characteristic of the electric-field strength detection circuit of the electric-f ield strength detection circuit according to the first embodiment of Fig. 5.

Fig. 16 is a block diagram showing the generalized configuration of the electric-field strength detection circuit according to the third and fourth embodiments of Figs. 7 and B.

Fig. 17 is a graph showing the input-output characteristic of the electric-field strength detection circuit having the generalized configuration of Fig. 16.

Fig. 18 is a circuit diagram showing the configuration of an electricfield strength detection circuit according to a fifth embodiment of the present invention.

Fig. 19 is a circuit diagram showing the configuration of an electricfield strength detection circuit according to a sixth embodiment of the present invention.

Fig. 20 is a circuit diagram showing a subcircuit of the three bipolar transistors to explain the operation of the electric-field strength detection circuit according to the f if th embodiment of Fig. 18.

Fig. 21A to 21D are waveform diagrams of the collector currents of the first and second transistors at the different levels of the input voltage, respectively.

Fig. 22A to 22D are waveform diagrams of the sum current of the collector currents of the first and second transistors at the different levels of the input voltage, respectively.

Fig. 23 is a graph showing the input-output characteristic of the electric-field strength detection circuit according to the fifth embodiment of Fig. 18.

Fig. 24 is a circuit diagram showing the configuration of an electricfield strength detection circuit according to a seventh embodiment of the present invention.

is Fig. 25 is a circuit diagram showing the configuration of an electric-field strength detection circuit according to an eighth embodiment of the present invention.

- Fig. 26 is a graph showing the input-output characteristic of the electric-field strength detection circuit having the generalized configuration of Fig. 16 and the circuit configuration of Fig. 18 or 19.

Fig. 27 is a circuit diagram showing the configuration of an electricfield strength detection circuit according to a ninth embodiment of the present invention.

Fig. 28 is a circuit diagram showing the configuration of a coupling circuit used in an electric-f ield strength detection circuit according to a tenth embodiment of the present invention.

Fig. 29 is a circuit diagram showing the configuration of an electricfield strength detection circuit according to an eleventh embodiment of the present invention.

Fig. 30 is a circuit diagram showing the configuration of an electricfield strength detection circuit according to a thirteenth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described in detail below while referring to the drawings attached.

FIRST EMBODIMENT An electric-field strength detection circuit according to a first embodiment of the present invention is comprised of the basic configuration shown in Fig. 4.

In Fig. 4, the electric-field strength detection circuit according to the first embodiment is comprised of three npn-type bipolar transistors Q1, Q2, and Q3 whose emitters are coupled together, a constant current sink 14 for sinking a constant current 10 which is connected to the coupled emitters of the transistors Q1, Q2, and Q3, a first load 11 connected to a collector of the transistor 01, a second load 12 connected to a collector of the transistor Q2, a third load 20 connected to a collector of the transistor Q3, and a reference voltage source 13 supplying a fixed reference voltage Vref.

The three emitter-coupled transistors Q1, Q2, and Q3 are driven by the common constant current or tail current Io generated by the constant current sink 14, which constitute a known "triple-tail cell". Also, the combination of the triple-tail cell, the first and second loads 11 and 12, and the reference voltage source 13 is referred as an "amplifier-rectifier circuit 10" below. Therefore, it can be said that the electric-field strength detection circuit according to the first embodiment is constituted by the amplifier-rectifier circuit 10 and the third load 20 including the integrator 21.

An IF input voltage VIN is applied across bases of the transistors Q1 and Q2 while the reference voltage Vr,f is applied to a base of the transistor 03. An IF output current IR551 of the electric- field strength detection circuit of Fig. 4 is derived from the third load 20 including the integrator 21. The output current Ips51 is then sent to the controller referred in Fig. 1. On the other hand, an IF amplified output voltage VouT is derived from the

collectors of the transistors Q1 and Q2. The amplified output voltage VWT is then sent to the demodulator referred in Fig. 1.

Fig. 5 shows a concrete circuit conf iguration of the electric-f ield strength detection circuit according to the first embodiment of Fig- 4.

In Fig. 5, resistors R1 and R2 are used as the first and second loads 11 and 12, respectively. A current mirror circuit 22 formed by two pnp-type bipolar transistors Q4 and Q5 is included in the third load 20, in addition to the integrator 21. The integrator circuit 21 provided in the third load 20 is formed by a resister R3 and a capacitor C3 connected in parallel.

The collector of the transistor QI is connected to a power supply line applied with a power supply voltage Vcc: through the load resistor R1. The collector of the transistor Q2 is connected to the power supply line of Vcc through the load resistor R2. The collector of the transistor Q3 is connected to the Dower supply 15 line of Vcc through the 'cur.-ent mirror circuit 22.

A base and a collector of the transistor Q4 are coupled together to be connected to the collector of the transistor Q3. The coupled base and collector of the transistor Q4 are connected to a base of the transistor Q5. Emitters of the transistors Q4 20 and Q5 are directly connected to the power supply line of Vcc. A collector of the transistor Q5 is connected to one terminal of the integrator 21. The other terminal of the integrator 21 is connected to the ground.

The amplifier-rectifier circuit 10 serves as a dif f erential amplif ier and a f ull-wave rectif ier. The amplif ied output voltage VOUT with respect to the input voltage VIN is generated between the collectors of the transistors Q1 and Q2, because collector currents 1c, and IC2 Of the transistors Q1 and Q2 flow through the load resistors RI and R2, respectively. A f ull-wave rectified current with respect to the input voltage VIN is produced as a collector current IC3 of the transistor Q3.

A mirror current of the f ull-wave rectified current 1c3, which is generated by the current mirror circuit 22, flows into the integrator circuit 21 to be integrated with time and smoothed, thereby outputting the IF output current IRssi.

Next, the operation principle of the electric-field strength detection circuit according to the first embodiment of Fig. 5 is explained below with reference to Figs. 9 and 10.

Fig. 9 shows a dif ferential pair f ormed by the transistors Q1 and Q3, which corresponds to the configuration obtained by removing the transistor Q2 in the triple-tail cell of the emitter-coupled transistors Q1, 02, and Q3 in Fig. 5. This is made for the purpose of simplification of explanation.

in Fig. 9, when base voltages of the transistors Q1 and Q2 are respectively defined as V31 and VB2 while a base voltage of the transistor Q3 is equal to the reference voltage V,,f with respect to the ground, t.he following well-known equations (1) and (2) are established for the differential pair of the transistors Q1 and Q3.

+ exp VB I - V111f ( - vr (1) IC3 = 10 1 + exp ( (2) Similarly, the following equations (3) and (4) are established for the differential pair of the transistors Q2 and Q3.

IC2 = 10 1 + exp ( VB (3) 1C3 9= + exp ( Vs 2 vr VI-ef (4) In the equations (1) to (4), VT is the thermal voltage defined as (KT/q), where K is the Baltzmann's constant, T is absolute temperature in degrees Kelvin, and q is the charge of an electron. It is known that VT has a value of approximately is equal to 26 mV at 25 C.

Fig. 10 shows the input-output characteristic of the differential pair shown in Fig. 9 according to the above equations (1) to (4). The abscissa is the voltage of (VEsi - V,ef) and the ordinate is the collector currents Ic, and 1C3 for the differential pair of the transistors Q1 and Q3. The abscissa is the voltage Of (Va2 - Vref) and the ordinate is the collector currents 1c2 and IC3 for the differential pair of the transistors Q2 and Q3.

As seen from Fig. 10, only the transistor Q3 is active and almost all the tail current 10 flows through only the transistor Q3 as the collector current 1C3 in the region A where the reference voltage Vet is pretty higher than the base voltage VB1. Also, only the transistor Q1 is active and almost all the tail current Io flows through only the transistor Q1 as the collector current Ic, in the region C where the reference voltage V,,,f is pretty lower than the base voltage VB1. On the other hand, in the intervening region 3, both the transistors Q1 and Q3 are active or operated- It is clear that -t'he same relationship as above is established when the transi'stor Qi is replaced with the transistor Q2 in Fig. 9, in other words, the differential pair is formed by the transistors Q2 and Q3.

The operation of the transistors Q1 and Q3 of the differential pair in the region B of Fig. 10 is explained below with reference to Figs. 11A to 11C and Figs - 12A and 12B. In these figures, tI, t2, t3, t4, and t5 denote arbitrary times.

If a sinusoidal input voltage is applied to the base of the transistor Q1 while the base of the transistor Q3 is applied with the constant reference voltage V,,f, the base voltage Val of the transistor Q1 varies sinusoidally, as shown in Fig. 11A, and at the. same time, the base-to-emitter voltage VBE3 of the transistor Q3 varies sinusoidally in opposite phase to the base voltage VBI, as shown in Fig. 11B. According to this change, the collector currents Ic, and IC3 Of the transistors Q1 and Q3 vary in opposite phases to one another, as shown in Fig. 11C.

The same result as above is obtained for the case where the transistor Q1 is replaced with the transistor Q2, as shown in Figs. 11A to 11C.

If the same sinusoidal input voltage as above is differentially applied across the bases of the transistors Q1 and Q2 of the triple-tail cell formed by the transistors Q1, Q2, and Q3 while the base of the transistor Q3 is applied with the constant reference voltage V...f, the collector currents Ic, and IC2 of the transistors Q1 and Q2 vary in opposite phases to one another, as shown in Fig. 12A. In this case, the collector current Ic3 of the transistor Q3 varies as shown in Fig. 12B, which represents the fact that the collector current 11-3 is a full-wave rectified current. This may be easily derived from Fig. 11C if the collector is currents Ir-1 and IC2 are changed independently.

The reason why the collector current 1C3 is a full-wave rectified current with respect to the sinuscidal input voltage is explained in more detail below with reference to Figs. 13A to 13D and Figs. 14A to 14D.

Fig. 13A shows the change of the collector currents Ic, and 1c2 of the transistors Q1 and Q2 and Fig. 14A shows the change of the collector current 1c3 of the transistor Q3 when the differential input voltage VIN is zero. rigs. 13B to 13D show the change of the collector currents 1c, and IC2 and Figs. 14B to 14D show the change of the collector current 1C3 when the 'Level or amplitude of the differential input voltage VIN is gradually increased from zero.

Since the sum of the collector currents Icl, Ic2, and IC3 does not exceed the con.stant current lo, the collector currents 1c, and IC2 Will saturate when the amplitude of the input voltage VIN iS greater than a specified value, as seen from Fig. 13D. Corr,esponding to the saturation of the collector currents Ic, and IC2, the collector current Ic3 yaries and saturates with the increasing input voltage as shown in Fig. 14D. It is seen from Figs. 14A to 14D that the collector current Ic3 is a full-wave rectified current.

Thus, the output current IR551 of the electric-field strength detection circuit according to the first embodiment of

Fig. 5, which is equal to the integration result of the collector current IC3 of the transistor Q3, will gradually decrease after the level or amplitude of the differential input voltage V,g exceeds the specified value. The change of the output current 5 Ips51 is shown in Fig. IS.

As seen from Fig. 15, the output current IRssi is kept constant when the amplitude of the input voltage VIN is equal to or less than the specif ic value, and it decreases logarithmically when the amplitude of the input voltage VIN is greater than the specific value.

With the electric-field strength detection circuit according to the first embodiment of Fig. 5, there are the following advantages.

First, the electric-field strength detection circuit according to the first embodiment of Fig. 5 is constituted by the three bipolar transistors Q1, Q2, and Q3, the constant current sink 14, the reference voltage source 13, the two load resistors R1 and R2 for the transistors Q1 and Q2, and the third load 20 including the integrator circuit 21 for the transistor Q3.

Therefore, the number of the necessary electronic components or devices is drastically decreased and at the same time, the input/output interfaces are simplified. As a result, the possibility or danger of selfoscillation is extremely low.

Contrary to the electric-field strength detection circuit according to the first embodiment of Fig. 5, a conventional IF amplifier has in general a high gain of 100 dB or greater and consequently, it tends to oscillate easily unless care are taken for the input/output wiring and isolation configurations. In other words, the more the coupling circuits between the individual amplifier stages 111 and the interfaces for the rectifier circuits 112 in the conventional electric-f ield strength detection circuit 101 of Fig. 1 become complicated, the more the possibility of self -oscillation of the conventional circuit 101 becomes high.

Second, since the number of the necessary electronic components or devices is drastically decreased and the input/output interfaces are. simplified, the electric-field strength detection circuit according to the first embodiment of Fig. 5 can be integrated on a larger scale than that of the conventional circuit 101.

- Third, because the circuit configuration is drastically simplified, the power dissipation can be reduced conspicuously.

SECOND EMBODIMENT Fig. 6 shows the circuit configuration of a third load 20' used in an electric-field strength detection circuit according to a second embotliment of the present invention, in which the polarity of the output current IRs51 is inverted with respect to the that of the first embodiment of Fig. 5.

The third load 20r shown in Fig. 6 has a configuration obtained by adding a current mirror circuit 23 formed by two npntype bipolar transistors Q6 and Q7 to the third load 20 shown 5 in Fig. 5.

Specifically, a base and a collector of the transistor Q7 are coupled together to be connected to the collector of the transistor Q5. The coupled base and collector of the transistor Q7 are connected to a base of the transistor Q6- Emitters of the transistors Q7 and Q6 are directly connected to the ground. A collector of the transistor Q6 is connected to one terminal of the integrator 21. The other terminal of the integrator 21 is connected to the power supply line of Vec.

with the electric-field strength detection circuit according to the second embodiment, needless to say, there are the same advantages as those in the first embodiment of Fig. 5 except that the output current 1",51 is opposite in phase to that of the first embodiment.

THIRD EMBODIMENT Fig. 7 shows the circuit configuration of an electric-field strength detection circuit according to a third embodiment of the present invention, in which an amplifier rectifier circuit 10' is added to the electric-field strength detection circuit according to the first embodiment of Fig. 5_ The amplifier-rectifier circuit 10' has the same configuration as that of the amplifier-rectifier circuit 10 shown in Fig. 5.

The amplifier-rectifier subcircult 10' has three npntype bipolar transistors QV, Q2', and Q31 whose emitters are coupled together, a constant current sink 14' for sinking a constant current 10' which is connected to the coupled emitters of the transistors Ql', Q21, and Q31, a load resistor Rl' connected to a collector of the transistor Ql' serving as a first load 111, a load resistor R2' connected to a collector of the transistor Q21 serving as a second load 12', and a reference voltage source 13' supplying a constant reference voltage V,,fl. The emitter-coupled transistors Q11, Q21, and Q3' are driven by the common constant current le' generated by the constant current sink 14'. The reference voltage V.. f'. is applied to a base of the transistor Q31.

The collector of the transistor Ql' is connected to the power supply line of V= through the load resistor RV. The collector of the transistor Q21 is connected to the power supply line of vcc through the load resistor R2'. The collector of the transistor Q3' is connected to the power supply line of Vcc through the current mirror circuit 22 together with the collector of the transistor Q3.

The collectors of the transistors Q1 and Q2 of the amplifier-rectifier circuit 10 located at the first stage are connected to the bases of the transistors Ql' and Q21 of the amplifier- rectifier circuit 101 located at the second stage, respectively. The differential output voltage AV generated between the collectors of the transistors Q1 and Q2 is applied across the bases of the transistors Q1' and Q2' of the amplifier-rectifier circuit 101.

Since the collectors of the transistors Q3 and Q31 are connected in common to the current mirror circuit 22 of the third load 20, a sum current 1C3"" Of the collector currents IC3 and 1C3' of the transistors Q3 and Q3'flows, through the current mirror circuit 22 instead of the collector current IC3.

With the electric-field strength detection circuit according to the third embodiment of Fig. 7, there are an additional advantage that the level of the output current IRss, is raised compared with that of the first embodiment of Fig. 4 along with the same advantages as those in the first embodiment. FOURTH EMBODIMENT Fig. 8 shows the circuit configuration of an electric-field strength detection circuit according to a fourth embodiment of the present invention, which has the same circuit conf iguration as that of the third embodiment of Fig - 7 other than that the integrator 21 itself is used as the third load 20 and no current mirror circuit is used. The configuration and connection of the integrator 21 are the same as those shown in Fig. 6.

Needless to say, there are the same advantages as those in the third embodiment of Fig. 7 except that the output current Ipss, is opposite in phase to that of the third embodiment.

Although each of the electric-field strength detection circuits according to the third and forth embodiments of Figs. 7 and 8 comprises the two amplifier-rectifier circuits 10 and 101 and the common load 20, it may comprise three or more amplifier-rectifier circuits cascade -connected. The circuit configuration of this case is shown in Fig. 16.

In Fig- 16, the electric-f ield strength detection circuit comprises five cascade-connected amplifier-rectifier circuits 10a, 10b, 10c, 10d, and 10e at first to fifth stages, an adder 30, and a load 20a. Each of the cascade-connected amplifier- rectifier circuits 10a, 10b, 10c, 10d, and 10e has the same configuration as that of the amplif ier-rectif ier circuit 10 shown in Fig. 5. The load 20a includes an integrator 21a. Each of the load 20a and the integrator 21a may have the same configuration as those used in the above-described first to fourth embodiments.

The amplifier-rectifier circuit 10a located at the first stage receives the input voltage V11g and produces an output voltage AV., and an output current Ic3.. The amplifier-rectifier circuit 10b located at the second stage receives the output voltage AV, of the circuit 10a and produces an ou tput voltage AVb and an output -33- current Ic3b. Similarly, the amplifier-rectifier circuit 10c located at the third stage receives the output voltage AVb of the circuit 10b and produces an output voltage AVc and an output current IC3c, the amplifier- rectifier circuit 10d located at the fourth stage receives the output voltage AV,, of the circuit 10c and produces an output voltage AVd and an output current IC3d, and the amplifier-rectifier circuit 10e located at the fifth stage receives the output voltage AVd Of the circuit 10d and produces an output voltage VocT to the demodulator and an output current 1 C) IC3..

The adder 30 receives the five output currents IC3a, 1C3b, IC3C, 1C3d, and IC3. thus produced and outputs an output current ladd equal to the sum of these currents IC3a, IC3b, 1C3c, 1C3d, and IC3e to the load 21a. The integrator 21a of the load 20a. integrates the output current Iadd from the adder 30 with time and produces an output current IRssr of the electricfield strength detection circuit of Fig. 16.

In the circuit configuration shown in Fig. 16, the amplitude of the input voltage VIN becomes larger with the ascending order of the stages. However, the maximum amplitude of the output voltages AV,, AVk>, AV,, AVd, and vouT does not exceed the power supply voltage Vcc. Thus, the large-amplitude Dart of the input voltage VIt, will not be amplified but saturate.

Fig. 17 shows the input-output characteristic of the circuit configuration of Fig. 16. As explained with reference to Fig. 15, the output level decreases with the increasing input voltage VIm when the input voltage VIN is equal to or greater than a specific value. Since" the applied voltage AVd to the amplif ier-rectif ier circuit 10e at the fifth stage is the maximum in the output voltages AVa, AVb, AV,, and AVd, the output current IC3, of the circuit 10e saturates at the lowest input level- In contrast, the applied voltage V1g to the amplifier-rectifier circuit 10a at the first stage is the minimum, the output current 1C3a of the circuit 10a saturates at the highest input level. The output current IpLs51 from.the integrator 21a is kept constant when the input voltage VIN is equal to or less than a specific value and decreases logarithmically proportional to the increasing input voltage VI-g when the input voltage VIN is greater than the specific value.

FIFTH EMBODIMENT Fig. 18 shows the circuit configuration of an electric-field strength detection circuit according to a fifth embodiment of the present invention, which has the same configuration as that of the first embodiment of Fig. 5 except that an amplifier- rectifier' circuit 10A is used instead of the amplifier-rectifier circuit 10 of Fig. 5.

The amplifier-rectifier circuit 10A is the same in configuration and operation principle as the amplif ier-rectif ier circuit 10 other than that (a) the collector of the bipolar transistor Q3 is directly connected to the power supply line of Vec, (b) the collectors of the transistors Q1 and Q2 are coupled together at a point P through the load resistors RI and R2, and (c) the third load 20 is connected between the connection point P of the resistors Rl and R2 and the supply voltage line Vcc.

Fig. 20 shows the triple-tail cell of the transistors Q1, Q2, and Q3 shown in Fig. 18. In Fig. 20, the above-described equations (1) to (4) are established and the input-output characteristic is the same as shown in Fig. 10. Also, similar to the above-described first to fourth embodiments, the collector current Ic] is a full-wave rectified current.

is Unlike the above-described first to fourth embodiments, the collector currents Ic, and Ic2 are added to one another to form a sum current IC4 in the fifth embodiment of Fig. 18. Therefore, the change of the sum current lc, is different from the collector current IC3, as explained below.

Fig. 21A shows the change of the collector currents cl and 1C2 of the transistors Q1 and Q2 and Fig. 22A shows the change of the sum current IC4 when the differential input- voltage VIN iS zero. Figs. 21B to 21D show the change of the collector currents Ic, and IC2 and Figs. 223 to 22D show the change of the sum current 1C4 when the differential input voltage VIN is gradually increased from zero.

Since the sum current IC4 has a relationship with the collector currents Ic, and Ic2 as 1C4 = ICI + IC2, the sum current Ic4 will saturate when the amplitude of the input voltage vr N is greater than a specified value, as seen from Fig. 22A to 22D. Corresponding to the saturation of the collector currents Ic, and IC2, the sum current Ic4 varies and saturates with the increasing input voltage VIN, as shown in Figs. 22A to 22D. It is seen from Figs. 22A to 22D that the sum current Ic, is a f ull-wave rectified current- The change of the output current IRSSI. of the electric-field strength detection circuit according to the f if th embodiment of Fig. 18 is shown'in Fig. 23. As seen from Fig. 23, the output current IRSSI is kept constant when the amplitude of the input voltage V1s is equal to or less than a specific value, and it increases logarithmically with the increasing input voltage Vib: when the amplitude of the input voltage VIm is greater than the specific value.

with the electric-field strength detection circuit according to the fifth embdiment of Fig. 160, as seen from the above explanation, there are the same advantages as those in the first embodiment of Fig. 5 except that the change of the output current IRSSI is opposite to that of the first embodiment, as shown in Figs. 15 add 23.

SIXTH EMBODIMENT Fig. 19 shows the circuit configuration of an electric-field strength detection circuit according to a sixth embodiment of the present Invention, which has the same configuration as that of the fifth embodiment of Fig. 18 except that the integrator 21 is connected between the connection point P and the power supply line of Vcc. The integrator 21 itself serves as the load 20.

The operation of the sixth embodiment is substantially the same as that of the fifth embodiment of Fig. 18 other than that the phase of the output current IRs51 is the same as that of the input voltage V1g.

The electric-field strength detection circuit according to the sixth embodiment of Fig. 19 has substantially the same advantages as those in the first embodiment of Fig. 5.

SEVENTH EMBODIMENT Fig. 24 shows the circuit configuration of an electric-f ield strength detection circuit according to a seventh embodiment of the present invention, in which an amplifierrectifier subcircuit 10A' having the same configuration as that of the amp lif ierrecti fier subcircuit 10A of Fig. 18 is added to the electric-field strength detecl"ion circuit according to the fifth embodiment of Fig. 18.

The amplifier-rectifier subcircuit 10A' has three npn-type bipolar transistors Ql', Q2', and Q3' whose emitters are coupled together, a constant current sink 14' for sinking a constant current Iol which is connected to the coupled emitters of the transistors Q11, Q21, and Q31, a load resistor Rl' serving as a first load 111 and connected to a collector of the transistor Qir, a load resistor R2' serving as a second load 12 and connected to a collector of the transistor Q2', and a reference voltage source 131 supplying a constant reference voltage Vret'. The emitter-coupled transistors QV, Q2', and Q31 are driven by the common constant current 101 generated by the constant current sink 14'. The reference voltage Vret' is applied to a base of the transistor Q31.

The collector of the transistor Q3' is directly connected 15 to the power supply line of Vee. The collectors of the transistors Ql' and Q2' are coupled together at a point P' through the load resistors Rl' and R2'. The third load 20 is connected between the connection point P' of the resistors Rl' and R21 and the supply voltage line Vcc.

The collectors of the transistors Q1 and Q2 of the amplifierrectifier circuit 10A located at the first stage are connected to the bases of the.transistors Ql' and Q21 of the amplifier-rectifier circuit 10A1 located at the second stage, respectively. The differential output voltage AV generated between the collectors of the transistors Q1 and Q2 of the circuit 10A is applied across the bases of the transistors Q1' and Q21 of the circuit 1M.

The sum currents Ic4 and IC4' of the circuits 10A and 10A' are added to one another at a connection point Q to form a sum current IC4". The sum current Ic4" is sent to th e current mirror circuit 22 of the third load 20 instead of the collector current IC4, outputting the output current IRS51 from the integrator 21.

The operation of the seventh embodiment is substantially the same as that of the fifth embodiment of Fig. 18.

With the electric-field strength detection circuit according to the seventh embodiment of Fig. 24, there are an additional advantage that the level of the output current IRss, is raised compared with that of the fifth embodiment of Fig. 18 along with the same advantages as those in the first embodiment of Fig. 5.

EIGHTH EMBODIMENT Fig. 25 shows the circuit configuration of an electric-field strength detection circuit according to an eighth embodiment of the present invention, which has the same configuration as that of the seventh embodiment of Fig. 24 except that the integrator 21 is connected between the connection point Q and the power supply line of Vc:c. The integrator 21 itself serves as the load 20.

The operation of the eighth embodiment is the same as that of the seventh embodiment of Fig. 24 other than that the phase cf the output current IRss, is the same as that of the input voltage VIN - The electric-field strength detection circuit according to the eighth embodiment has the same advantages as those in the first embodiment of Fig. 5.

Although each of the electric-field strength detection circuits according to the seventh and eighth embodiments of Figs.

24 and 25 comprises two amplifier-rectifier circuits 10A and 10AI, it may comprise three or more amplifier-rectifier circuits cascade-connected, as shown in Fig. 16.

Fig. 26 shows the input-output characteristic of the circuit configuration of Fig. 16, where the electric-field strength detection circuit according to the fifth or sixth embodiment of Fig. 18 or 19 is used as each of the five amplifier-rectifier circuits 10a, 10b, 10c, 10d, and 10e shown in Fig. 16.

As already shown in Fig. 23, the output level increases with the increasing input voltage VrN until the input voltage VIN is equal to a specific value. Since the applied voltage AVd to the amplifier-rectifier circuit 10e at the fifth stage is the maximum, the output current 1C41 of the circuit 10e saturates at the lowest input level. On the contrary, the applied voltage VIN to the amplifier-rectifier circuit 10a at the first stage is the minimum, the output current IC4, Of the circuit 10a saturates at the highest input level. The output current IR5s, from the integrator 21a increases logarithmically proportional to the increasing input voltage V:N when the input voltage VIN is less than a specific value, and saturates at a constant value when the input voltage Via is equal to or greater than the specific value.

NINTH EMBODIMENT Fig. 27 shows the circuit configuration of an electric-field strength detection circuit according to a ninth embodiment of the present invention, which has a configuration obtained by adding two bias circuits 41 and 42 and two coupling capacitors Cl and C2 to the electric-field strength detection circuit according to the third embodiment of Fig. 7 as a coupling circuit 40 for the amplifier-rectifier circuits 10 and 10'.

The capacitor Cl is connected to the collector of the transistor Q2 of the amplifier-rectifier circuit 10 at the first stage and the base of the transistor Q21 of the amplifier- rectifier circuit 101 at the second stage. The bias circuit 41 20 is connected to the connection point of the capacitor Cl and the base of the transistor Q2'.

Similarly, the capacitor C2 is connected to the collector of the transistor Q1 of the amplif ier-rectif ier circuit 10 at the first stage and the base of the transistor Ql' of the amplifier-rectifier circuit 101 at the second stage. The bias circuit 42 is connected to the connectionpoint of the capacitor C2 and the base of the transistor Q11.

The output voltage AV of the amplifier-rectifier circuit 10 at the first stage is turned into a voltage. AV' by the coupling circuit 40 and then, applied across the bases of the transistors 01' and Q2' of the amplifier-rectifier circuit 101 at the second stage.

The operation of the ninth embodiment of Fig. 27 is 10 substantially the same as that of the third embodiment of Fig. 7 With the electric-field strength detection circuit according to the ninth embodiment of Fig. 27, there is an additional advantage that any abnormal oscillation is suppressed along with the same advantages as those in the third embodiment of Fig. 7.

TENTH EMBODIMENT Fig. 28 shows a coupling circuit 401 used in an electric-field strength detection circuit according to a tenth embodiment of the present invention. The coupling circuit 401 is comprised of two voltale-follower circuits 43 and 44.

The voltage f ollowr circuits 43 and 4 4 are added instead of the combination of the coupling capacitor Cl and the bias circuit 41 and the combination of the coupling capacitor C2 and -43- the bias circuit 42 in the electric-field strength detection circuit according to the ninth embodiment of Fig. 27.

The operation of the tenth embodiment is substantially the same as that of the third embodiment of Fig. 7.

There is an additional advantage that the circuit operation at high frequency ranges can be stable because each of the voltage follower circuits 43 and 44 has a high input impedance and a low output impedance, along with the same advantages as those in the third embodiment of Fig. 7.

ELEVENTH EMBODIMENT Fig. 29 shows the circuit configuration of an electric-field strength detection circuit according to an eleventh exnbodiment of the present invention, which has a configuration obtained by adding the coupling circuit 40 shown in Fig. 27 to the electric-field strength detection circuit according to the eighth embodiment of Fig. 25.

The connection of the capacitors Cl and C2 and the bias circuits 41 and 42 in the coupling circuit 40 are the same as that of Fig. 27. The output voltage AV of the amplifier-rectifier circuit 10A at the first stage is turned into the voltage AV' by the coupling circuit 40 and then, applied across the bases of the transistors Ql' and Q2' of the amplifier-rectifier circuit 10A' at the second stage.

The operation of the eleventh embodiment is substantially the same as that of the eighth embodiment of Fig. 25.

There is an additional advantage that any abnormal oscillation is suppressed, along with the same advantages as those 5 in the eighth embodiment of Fig. 27.

TWELFTH EMBODIMENT Although not illustrated here, an electric-field strength detection circuit according to a twelfth embodiment of the present invention has a configuration obtained by replacing the coupling circuit 40 in the electric-field strength detection circuit according to the eleventh embodiment of Fig. 29 with the coupling circuit 401 of Fig. 28.

There is an additional advantage that the circuit operation at high frequency ranges can be stable.

THIRTEENTH EMBODIMENT Fig. 30 shows an electric-field strength detection circuit according to a thirteenth embodiment of the present invention, which has a configuration obtained by replacing the three npn-type bipolar tzansistors Q1, Q2, and Q3 in the electric-f ield strength detection circuit according to the first embodiment of Fig. 4 with three n-channel MOSFETs M1, M2, and M3, respectively.

Unlike a bipolar transistor having a collector current with an exponential characteristic, a drain current of a MOSFET has a square-law characteristic. However, in this case, as known well, two amplified output voltages are generated at the drains of the MOSFETs M1 and M2, respectively, and at the same time, a rectified output current is generated at the drain of the MOSFET M3. Therefore, the MOS electricfield strength detection circuit according to the thirteenth embodiment of Fig. 30 is operated according to the same operation principle as that shown in the bipolar electric-field strength detection circuits according to the first to twelfth embodiments.

Although not illustrated here, it is needless to say that the bipolar transistors used in the electric-field strength detection circuits according to the second to twelfth embodiments may be replaced with MOSFETs, respectively, as shown in Figs. 30 and 4.

While the preferred forms of the present invention have been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention. The scope of the invention, therefore, is to be determined solely by the following claims.

Claims

1. An electric-field strength detection circuit comprising:

(a) first, second, and third transistors whose emitters/sources are coupled together; said first, second, and third transistors being driven by a common constant current; (b) a constant current source/sink for supplying /sinking said common constant current; said constant current source/sink being connected to said coupled emitters /sources of said first, second, and third transistors; (c) a first load connected to a collector /drain of said first transistor; (d) a second load corihected to a collector/drain of said second transistor; (e) a third load connected to a collector/drain of said third transistor; said third load Lticluding an integrator; and (f) a reference voltage source for supplying a reference voltage; wherein an input voltage is applied across bases of said first and second transistors while said reference voltage is applied to a base of said third transistor; and wherein a rectified output current with respect to said input voltage is generated at said collector/drain of said third transistor and integrated by said integrator in said third load, thereby producing an output of said electric-field strength 5 detection circuit proportional to a level of said input voltage.

2. The circuit as claimed in claim 1, wherein said third load includes a current mirror circuit; said rectified output current flowing to said integrator through said current mirror circuit.

3. The circuit as claimed in claim 1, wherein said the integrator itself serves as said third load.

4. An electric-field strength detection circuit comprising:

(a) first to n-th cascade-connected amplifier-rectifier circuits for generating first to n-th amplified output signals and first to n-th rectified output signals, respectively, where n is an integer greater than unity:

(b) an adder for adding said first to n-th rectified output signals and producing an added output signal; and (c) a load having an integrator for integrating said added output signal to generate an output of said electric-field strength detection circuit; I wherein each of said first to n-th amplifier-rectifier circuits comprises (a- 1) f irst, second, and third transistors whose 1 1 emitters/sources are coupled together; i 5 l 1 said first, second, and third transistors being driven by a common constant current; (a-2) a constant current source/sink for supplying ls inking said common constant current; 1 1 said constant current source/sink being connected to said coupled emitters /sources of said first, second, and third transistors; (a-3) a first load connected to a collector/drain of said first transistor; (a-4) a second load connected to a collector/drain of said second transistor; and 1 1 (a-5) a reference voltage source for supplying a reference 1 voltage; 1 and wherein an input voltage is applied across bases of said first and second transistors while said reference voltage is applied to a base of said third transistor in said first i i amplifier-rectifier circuit; and wherein said output of said electric-field strength detection circuit is proportional to the level of said input voltage.

5. The circuit as claimed in claim 4, wherein said (n - 1) -th amplifierrectifier circuit is directly connected to said n-th amplifier-rectifier circuit.

6. The circuit as claimed in claim 4, wherein said (n - 1) -th amplifierrectifier circuit is connected to said n-th amplifier-rectifier circuit through a coupling circuit.

7. The circuit as claimed in claim 6, wherein said coupling circuit includes a coupling capacitor and a bias circuit.

8. The circuit as claimed in claim 6, wherein said coupling circuit includes a voltage follower circuit.

is

9. An electric-field strength detection circuit comprising:

(a) first, second, and third transistors whose emitters/sources are coupled together; said first, second, and third transistors being driven by a common constant current; (b) a constant current source/sink for supplying/sinking said common constant current; said constant current source/sink being connected to said coupled emitters/ sources of said first, second, and third 1 transistors; (c) a f irst load connected to a collector/drain of said f irst transistor; (d) a second load connected to a collector/drain of said second transistor; said second load being connected to said first load at a connection point; (e) a third load connected to said connection point of said first and second loads; said third load including an integrator; and (f) a reference voltage source for supplying a reference voltage; wherein an input voltage is applied across bases of said first and second transistors while said reference voltage is applied to a base of.said-third transistor; and wherein a rectified outiDut current with respect to said input voltage is generated at the connection point of said first and second loads and is integrated by said integrator in said third load, thereby producing an output proportional to the level of said input voltage.

10. The circuit as claimed in claim 9, wherein said third load includes a current mirror circuit; said rectified output current flowing to said integrato through said current mirror circuit.

11. The circuit as claimed in claim 9, wherein said the integrator itself serves as said third load.

12. An electric-field strength detection circuit comprising:

(a) first to n-th ca s cade- connected amplifier-rectifier circuits for generating first to n-th amplified output signals and first to n-th rectified output signals, respectively, where n is an integer greater than unity; (b) an adder for adding said first to n-th rectified output signals and producing an added output signal; and (c) a load having an integrator for integrating said added output signal to generate an output of said electric-field strength detection circuit; wherein each of said first to n-th amplifier-rectifier 2 circuits comprises (a-1) first, second, and third transistors whose 0 emitters/sources are coupled together; said the first, second, and third transistors being driven by a common constant current; (a-2) a constant current source/sink for supplying/ sinking said common constant current; 2 1 said constant current source/sink being connected to said coupled emitters/ sources of said first, second, and third transistors; (a-3) a first load connected to a collector/drain of said first transistor; (a-4) a second load connected to a collector/drain of said second transistor; said second load being connected to said first load at a connection point; and (a-5) a reference voltage source for supplying a reference voltage; wherein an input voltage is applied across bases of said first and second transistors while said reference voltage is applied to a base of said third transistor in said first amplifierrectifier circuit; and wherein said output of said electric-field strength detection circuit is proportional to the level of said input voltage.

0

13. The circuit as claimed in claim 12, wherein said (n - 1) -th amplifier-rectifier circuit is directly connected to said n-th amplifierrectifier circuit.

14. The circuit as claimed in claim 12, wherein said (n - 1) -th amplifier-rectifier circuit is connected to said n-th amplifier-rectifier circuit through a coupling circuit.

15. The circuit as claimed in claim 14, wherein said coupling circuit includes a coupling capacitor and a bias circuit.

16. The circuit as claimed in claim 14, wherein said coupling circuit includes a voltage follower circuit.

17. An electric-field strength detection circuit substantially as any of the embodiments herein described with reference to the drawings.

1