JP2001066344A - Load current output circuit to electronic device and ic tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately measure signal rising and falling even when a device output signal to be detected is at a high speed by leading (supplying) a specific current value from (to) a transmission line when a detection voltage level is low (high). SOLUTION: In a dynamic current load circuit 41, an input terminal 4b is connected to a point B (connection point 4a), and the output signal of a device (DuT) 5 to be detected is inputted via a transmission line 1. A comparator 412 compares the voltage of the point B with a reference voltage VTH at I/O switching timing for judging whether the voltage of the point B is lower or higher than the reference voltage. Then, when the voltage of the point B is lower than the reference voltage VTH, it is assumed that the output signal of an I/O terminal 5a of the DuT 5 is shifted to a high level next for changing the connection of a switch circuit 413 to the side (terminal P2) of a constant current source 415, and switching control is made so that a current value IOH is allowed to sink. On the other hand, when the voltage of the point B is higher than the reference voltage VTH, it is assumed that the output signal of the I/O terminal 5a is shifted to a low level next for changing the connection of the switch circuit 413 to the side (terminal P1) of a constant current source 414, and a current value IOL is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load current output circuit for an electronic device and an IC tester, and more particularly, to a dynamic current load circuit for flowing or sinking a load current to an output terminal of a device under test (hereinafter, DUT). The present invention relates to a dynamic current load circuit and an IC tester that can accurately measure a signal rise time tr or a fall time tf even when an output signal of a DUT becomes faster. Note that the load current output here includes the case of the pull operation for sinking the current from the DUT.

[0002]

2. Description of the Related Art An IC tester applies a pulse waveform signal of a preset voltage to a predetermined terminal of a DUT, and after a predetermined time, an output terminal (or an input / output terminal,
The same applies to the waveform of the signal output from
The determination circuit determines whether the signal is at the H level (hereinafter “H”) or the LOW level (hereinafter “L”) according to a strobe signal generated at a predetermined timing (hereinafter, a determination mode). In this determination mode, when the IC tester measures the signal rise time tr or the fall time tf, a strobe signal of a predetermined cycle is added to the determination circuit to change from "L" to "H" or from "H" to "L". Measure the time to become. In addition, an operation test, a performance test, and the like of the DUT are performed by comparing the determination result with an expected value.

At the time of time measurement, in order to imitate a state in which another device is connected to the DUT, a predetermined current value, for example, a load current of several mA to several tens mA is supplied to a specific output terminal. Is determined as "H" or "L". For this purpose, a load current is supplied to the output terminal of the DUT in the determination mode in the IC tester (the current supply includes a negative current supply, that is, a current sink).
Dynamic current load circuit (load current output circuit)
Is provided. This dynamic current load circuit is normally connected to an output terminal via a diode switch circuit provided inside. In addition, as this type of apparatus, for example, JP-A-62-116272,
JP-A-2-128176, JP-A-6-82527 and the like can be mentioned.

A dynamic current load circuit of this kind is:
As shown in FIG. 5, the output signal of the DUT changes from "L" to "L".
When transitioning to "H", the current IOH is drawn from the DUT,
When the output signal of the DUT changes from “H” to “L”, the current IOL is supplied to the DUT. Thereby, IC
The tester can imitate the current value and the current direction when another device is connected to the output terminal of the DUT during the IC test. Generally, a diode switch circuit is configured by a diode bridge, and turns on a diode in accordance with an output signal of “H” or “L” of an output signal terminal.
/ OFF to supply the load current as described above.

FIG. 6 shows a dynamic current load circuit of a conventional IC tester of this kind. As shown in FIG. 6, the dynamic current load circuit 40 is connected to a DUT 5 via a transmission line 1 together with a driver 2, an analog comparator circuit (hereinafter, a comparator) 3 and the like. Further, it has a constant current source IOL connected to the positive power supply + VCC and discharging current with a current value IOL, and a constant current source IOH connected to the negative power supply -VEE and current sink with a current value IOH. Here, the comparator 3 operates in the determination mode, receives the strobe signal generated at a predetermined timing, and compares the comparison reference voltage VTH with the input voltage to make it “H” or “L” as described above. Circuit. Reference numeral 4 denotes an input / output switching I / O switch circuit.
O is the control bit signal. 5a is an input / output terminal (I / O terminal) of the DUT 5, and VS is a switching control voltage signal of the diode switch.

[0006]

SUMMARY OF THE INVENTION Such a conventional IC
In the tester, the DUT 5 and the dynamic current load circuit 40
Since there is a delay time τ due to the transmission line between
When the output signal of No. 5 becomes high-speed (high-frequency signal), the signal rise time tr at which the output signal transitions from “L” to “H” becomes smaller than the transmission line delay time τ (tr <τ). , The dynamic current load circuit 40
Before sinking current IOH in response to the transition of UT5, DU
The transition of the output signal of T5 to "H" is completed. At this time, the dynamic current load circuit 40 of FIG.
At the time of transition from “L” to “H”, on the contrary, the current IOL
Is supplied to the DUT 5. This supply current is DU
This acts to speed up the rise of the signal at T5. Therefore, the dynamic current load circuit 40
Not only does it not operate as the original load current output circuit, but also adversely affects the measurement. This is the same when the output signal of the DUT 5 transitions from “H” to “L”. Therefore, when the output signal of the DUT 5 becomes faster, the signal rise time tr or fall time t
There is a problem that f cannot be measured accurately. An object of the present invention is to solve such a problem of the related art, and to accurately measure a signal rise time tr or a fall time tf even when an output signal of a DUT becomes faster. It is an object of the present invention to provide a dynamic current load circuit and an IC tester.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, a dynamic current load circuit and an IC tester according to the present invention are characterized in that the output signal is received from a DUT via a transmission line or another transmission line. And a detection circuit for detecting the voltage level of the line. When the voltage level detected by the detection circuit is the LOW level, a predetermined current value is drawn from the transmission line or another transmission line, and the detected voltage level is set to the HIGH level. In the case of, a predetermined current value which is the same as or different from the above is supplied to a transmission line or another transmission line.

[0008]

As described above, the present invention provides a DUT
To detect the current voltage level of the side receiving the output signal from the transmission line or another transmission line, and in response to this detection,
If the current voltage level is "L", the next transition is from "L" to "H". For example, when the output signal of the DUT transitions from "L" to "H", Prior to the transition time, the dynamic current load circuit draws a predetermined current value IOH into the DUT in advance, and if the current voltage level is "H", the next transition is from "H" to "L". Similarly, when the output signal of the DUT transitions from “H” to “L”, the dynamic current load circuit similarly applies a predetermined current value IOL to the DUT before the transition time. Supply. Therefore, in the dynamic current load circuit and the IC tester connected to the DUT by the transmission line, when the output signal of the DUT transitions from “L” to “H” or transitions from “H” to “L”, the delay of the delay line It is possible to source or sink current to the DUT without being affected by time. As a result, even when the output signal of the DUT becomes faster, the signal rise time tr or fall time tf can be accurately measured.

[0009]

1 is a block diagram mainly showing a dynamic current load circuit in an IC tester to which the present invention is applied. Note that the same components as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, FIG.
A dynamic current load circuit 41 is provided in place of the dynamic current load circuit 40 of FIG. DUT5 is
The driver 2, the comparator 3, and the dynamic current load circuit 41 are connected via the transmission line 1. The dynamic current load circuit 41 includes the waveform formatter 6
From I / O switch ON / OFF control bit signal I / O
Receive. The data of the comparison reference value is sent from the CPU 7 controlling the tester to the register 41 via the bus 8.
Receive 0. The bit signal I / O of the I / O switch ON / OFF control is usually generated by a predetermined logical operation between the control signal of the pattern generator and the timing signal of the timing generator, and is output from the waveform formatter 6. Is generated directly or separately from another circuit or a circuit such as a pattern generator or a timing generator, not from the waveform formatter 6, and the dynamic current load circuit 4
1 may be supplied.

The dynamic current load circuit 41 includes a register 410, a D / A conversion circuit (D / A) 411, an analog comparator (COM) 412, and a switch circuit 41.
3, a constant current source 414 connected to the positive power supply + Vcc for discharging current with a current value IOL, and a constant current source 415 connected to the negative power supply -VEE with a current sink for current value IOH. 6 corresponding to "H" and "L" at the connection point 4a (point B) between the output terminal of the I / O switch circuit 4 (driver 2) and the transmission line 1 is opposite to the dynamic current load circuit 40 of FIG. Switch operation. The connection point 4a is a wiring line on the side that receives an output signal from the DUT 5 via the transmission line 1 from the DUT 5. A / D411
Receives the data from the register 410, converts the data value into an analog value, and outputs the analog value to one input terminal of the comparator 412 as the reference voltage VTH. The other terminal of the comparator 412 is connected to the input / output terminal 4b. The comparator 412 compares the voltage level of the input / output terminal 4 b (point B) with the output voltage level of the A / D 411, and sends the comparison result to the switch circuit 413. The switch circuit 413 has one terminal of the switch circuit 413 connected to the point B (connection point 4a) via the input / output terminal 4b, and three terminals P1, P2,. P3, one of which is selected and connected to point B (connection point 4a). The terminal P1 is connected to the constant current source 414, and the terminal P2 is connected to the constant current source 415.
, And the terminal P3 is a terminal that is not connected to anywhere (or kept at a high resistance).

The dynamic current load circuit 41
The input / output terminal 4b is connected to point B (connection point 4a),
When a point B (connection point 4a), which is an output terminal of the I / O switch circuit 4 (driver 2), receives an output signal from the DUT 5, the circuit 41 performs input / output switching timing (I / O switching).
Bit signal I / O of O switch ON / OFF control is "L"
), The comparator 412 determines whether the voltage at the point B is “H” or “L”. When the voltage is “H”, the output signal of the input / output terminal 5a of the DUT 5 is subsequently “L”.
Then, the connection of the switch circuit 413 is switched to the constant current source 414 side (terminal P1) to supply the current value IOL. When the voltage at the point B is "L", the output of the input / output terminal 5a of the DUT 5 is output. Assuming that the signal next transitions to "H", the connection of the switch circuit 413 is switched to the constant current source 415 side (terminal P2) and switching control is performed so as to sink the current value IOH. The output terminal 4 of the I / O switch circuit 4
An output waveform is generated from the driver 2 at the point B which is a
The timing at which it is applied to the input terminal 5a of T5 (I
When the bit signal I / O for the / O switch ON / OFF control is “H”, the bit signal I / O is transmitted to the control terminal 416.
Then, the connection of the switch circuit 413 is switched to the high impedance terminal (terminal P3) side so that the point B becomes high impedance (Hi-Z).

Here, the switch circuit 413 controls the bit signals I / O to “H” and “L” and the output signal of the comparator 412 to “H” as control signals for selecting one of the three terminals P 1, P 2 and P 3. And "L", the switching operation described above is performed. Therefore, the point at which point B is connected to the constant current source 414 or the constant current source 415 by the switch circuit 413 is that the bit signal I / O of the I / O switch ON / OFF control, which is the output wait timing of the DUT 5, is “ L ”. The determination as to whether the voltage at the point B is “H” or “L” is made by the comparator 412 comparing the reference voltage VTH with the voltage at the point B.
Prior to the start of the test, the data sent from the CPU 7 is set in the register 410, and this data is stored in the D / A 411.
, And the converted value VTH is received by the comparator 412 as the determination reference voltage VTH. When the voltage at the point B is equal to or higher than the voltage VTH, the voltage at the point B is set to “H”, the comparator 412 outputs a determination result of “H”, and is applied to the switch circuit 413, and the bit signal I / O becomes “L”. When the constant current source 414 is selected and the voltage at the point B is lower than VTH, the voltage at the point B is set to “L”, the comparator 412 outputs a determination result of “L”, and is applied to the switch circuit 413. When the bit signal I / O is “L”, the constant current source 415 is selected.

As the overall test operation, first,
As a test procedure of the DUT 5, a predetermined waveform signal is output from the driver 2 in response to the "H" output of the bit signal I / O for the I / O switch ON / OFF control from the waveform formatter 6.
Output to UT5, then I / O switch ON / OFF
A signal output from the input / output terminal 5a of the DUT 5 is transmitted to the comparator 3 via the transmission line 1 after a predetermined time according to the "L" output of the control bit signal I / O. The comparator 3 receives the signal and determines “H” and “L” on the waveform of the signal output from the DUT 5. When measuring the signal rise time tr or the fall time tf with respect to the waveform, the comparator 3 receives the strobe signal ST having a predetermined cycle and operates accordingly to determine whether the signal is “H” or “L”. The determination is made corresponding to the strobe signal ST, and the time from "L" to "H" (signal rise time tr) or from "H" to "L" (fall time tf) is "H", "L". Is measured by this IC tester according to the judgment result of. The comparator 3 determines whether the signal is “H” or “L” in accordance with the strobe signal ST at a predetermined timing, and further compares the result of determination with an expected value sent from a pattern generator (not shown). Is used to judge a fail bit or the like.

As described above, when the output waveform of the DUT 5 is determined by the comparator 3, a predetermined load current is applied to the output terminal of the DUT 5 in order to imitate a state in which another device is connected to the DUT 5. Provided by circuit 41. When the voltage at the point B (connection point 4a) is "L", the dynamic current load circuit 41 draws the current IOH from the DUT 5 through the point B and the transmission line 1 prior to the output of the DUT 5, and outputs the current IOH from the point B (connection point 4a). When the voltage of 4a) is "H", the current IOL is supplied to the DUT 5 via the transmission line 1 at the point B.

Next, as an explanation of the operation and effect of the present invention,
When the delay time τ of the delay line 1 becomes a problem with respect to the output signal, the dynamic current load circuit 41 and the DUT
5 will be described. DUT
5 and the dynamic current load circuit 41 are connected via the transmission line 1, so that the output signal of the DUT 5 reaches the dynamic current load circuit 41 with a delay of time τ. Therefore, when the rise time tr of the output signal of the DUT 5 is smaller than the delay time τ of the transmission line 1 (when it is fast), when the output signal of the DUT 5 transitions from “L” to “H”, the dynamic current load is reduced. Although the voltage at the point B (connection point 4a), which is the input / output terminal of the circuit 41, remains at "L", as described above, the dynamic current load circuit 41 of the present invention performs the I / O switch ON / OFF control. The current IOH is drawn from the DUT 5 from the input / output terminal (connection point 4a) from the timing when the bit signal I / O becomes "L". As a result, when the output signal of the DUT 5 transitions from “L” to “H”, the dynamic current load circuit 41 draws the current IOH from the DUT 5. Similarly, when the output signal of the DUT changes from “H” to “L”, the current IOL is supplied to the DUT 5.

Thus, this IC tester is not affected by the delay time τ of the transmission line 1 at the time of waveform determination.
In particular, the strobe signal ST having a predetermined period is supplied to the comparator 3
When the rise time tr or the fall time tf of the output signal is measured in addition to the above, the time from "L" to "H" or from "H" to "L" can be accurately measured. In the above case, the point B is "L".
Is completely changed to “H”, the dynamic current load circuit 41 determines that the output signal of the DUT 5 is “H” next.
The switch circuit 413 is switched and connected to the constant current source 414 (terminal P1) assuming that the current state changes from "L" to "L".
Will be supplied. In this case, since the dynamic current load circuit 41 has an operation delay, even if switching to supply the current value IOL is performed due to the point B becoming “H”, the measurement itself of the signal rise time tr has no influence. I do not receive. Conversely, when the point B completely transitions from “H” to “L”, the dynamic current load circuit 41 determines that the output signal of the DUT 5 transitions from “L” to “H” next. 413 is switched (terminal P2) to the constant current source 415 to sink the current value IOH. In this case as well, the measurement itself of the fall time tf is not affected as described above. Note that the expected value and “H”, “L”
Is determined, the dynamic current load circuit 4
In No. 1, it is sufficient that a delay circuit having a delay time enough to make this determination is positively provided between the point B and the switch circuit 413, and the comparison with the expected value is not affected.

FIG. 2 is a block diagram of another embodiment showing a partial configuration of an IC tester provided with a dynamic current load circuit according to the present invention. The I / O switch circuit 4, the driver 2, the comparator 3, and the dynamic current load circuit 42 are connected to the DUT 5 via the transmission line 1. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The same applies to the following embodiments. The dynamic current load circuit 42 here is
Switch circuit 413 of dynamic current load circuit 41
Instead of this, a switch configuration including a switch circuit 413a and a switch circuit 413b for two-terminal switching is adopted. Other configurations are the same as those of the dynamic current load circuit 41. The switch circuit 413a is inserted between the point B and the switch circuit 413b, and the I / O switch ON /
It is turned ON / OFF according to “H” and “L” of the bit signal I / O for OFF control. The switch circuit 413a is turned off when the bit signal I / O is at "H". When the bit signal I / O is turned off, the point B is set to a high impedance (Hi-Z )
Set to. The switch circuit 413a is turned on when the bit signal I / O is "L", and when it is turned on, the point B is connected to the switch circuit 413b.

The switch circuit 413b includes the comparator 4
12 according to the “H” and “L” signals of the constant current source 41.
4 and 415 are connected to the terminals P1 and P2 to select B
A switch that connects to a point. That is, the bit signal I /
When O is “L”, the comparator 4
12 generates a judgment output of "H", whereby the current source 4
14 is selected, and the comparator 412 generates an “L” determination output, whereby the constant current source 415 is selected.
The operation of the dynamic current load circuit 42 as a whole
The operation is the same as that of the dynamic current load circuit 41.

FIG. 3 shows still another embodiment, and is an explanatory diagram of another switch configuration of a dynamic current load circuit and its control circuit. In FIG. 3, a dynamic current load circuit 43 is provided in place of the dynamic current load circuit 41. Other configurations are the same as those in FIG. The dynamic current load circuit 43 is provided with a switch circuit composed of a two-terminal switching switch circuit 413c and a switch circuit 413d, instead of the switch circuit 413 of the dynamic current load circuit 41, and further as a control circuit 417 for controlling these switch circuits. A gate circuit is provided. Other configurations are the same as those of the dynamic current load circuit 41. The switch circuit 413c is a switch circuit for connecting the constant current source 414 to either the point B and the ground GND terminal, and the switch circuit 413d is for connecting the constant current source 415 to either the point B or the ground GND terminal. Switch circuit.

A control circuit 417 for controlling each of the switch circuits 413c and 413d includes a two-input AND gate 417a,
417b and inverters 418a, 418b, 418c
Consists of A bit signal I / O for I / O switch ON / OFF control is input to AND gates 417a and 417b via inverters 418a and 418b, respectively. Therefore, when this is received from the DUT 5 side, that is, the bit signal I / O of the I / O switch ON / OFF control
Is "L", it is the inverter 418a, 418b
To "H", and the AND gate 417
The gate of a, 417b opens and becomes valid. When this becomes valid, the judgment result of the comparator 412 becomes “H”.
In this case, "H" is added to the AND gate 417a to output "H", whereby the switch circuit 413c is switched to the point B side. As a result, the current IOL from the constant current source 414 can be supplied to the DUT 5 via the input / output terminal 4b, the point B, and the transmission line 1. At this time, the “L” level is applied to the AND gate 417b via the inverter 418c.
Is added, the output of the AND gate 417b becomes “L”, and the switch circuit 413d is connected to the ground GND.
Connected to the side.

When the judgment result of the comparator 412 is "L", "H" is added to the AND gate 417b via the inverter 418c, and the switch circuit 413d is similarly switched to the point B, and the constant current source 414 The current IOH is drawn from the DUT 5. At this time, since “L” is added to the AND gate 417a, the output of the AND gate 417a becomes “L”, and the switch circuit 413
c is connected to the ground GND side. On the other hand, when a predetermined waveform signal is output from the driver 2 to the input / output terminal 5a of the DUT 5, the bit signal I / O of the I / O switch ON / OFF control becomes "H", and the AND gate 417a,
"L" is input to 417b, each gate is closed, the switch circuits 413c and 413d are connected to the ground GND side, and the point B becomes high impedance (Hi-Z) (the switching connection state of the illustrated switch) ). The operation of the dynamic current load circuit 43 as a whole is the same as the operation of the dynamic current load circuit 41.

FIG. 4 shows a specific example of a dynamic current load circuit which can select the same operation as the conventional dynamic current load circuit 40 of FIG. 6 when the delay time of the transmission line 1 does not matter. is there. The dynamic current load circuit itself further embodies the switch configuration of the dynamic current load circuit 43 of FIG. 3 and its control circuit. In the dynamic current load circuit 44 shown in FIG. 4, the switch circuit 413c shown in FIG. 3 is constituted by a current switching circuit (current switch) composed of PNP bipolar transistors Q1 and Q2 receiving a current IOL from a constant current source 414. Switch circuit 413d
Is constituted by a current switching circuit composed of NPN type bipolar transistors Q3 and Q4 receiving the current IOH from the constant current source 415. A control circuit 419 corresponding to the control circuit 417 of FIG. 3 includes a coincidence detection circuit (NOT-EXOR gate) 420 and an inverter 421, and a level shift circuit between the switch circuits 413 c and 413 d and the control circuit 420. 422 and 423 are provided respectively. Further, a buffer amplifier (or voltage follower) 424 having a high impedance input is provided between the comparator 412 and the point B.

Here, the level shift circuits 422, 423
Is a circuit for converting the level of “H” or “L” into a drive signal for a transistor, receives a bit signal I / O for I / O switch ON / OFF control via an input terminal 420b, and outputs the signal “L”. Set to enable when. Level shift circuit 422 receives the output of match detection circuit 420, and level shift circuit 423 receives the output of match detection circuit 420 via inverter 421. Therefore,
These level shift circuits 422 and 423 are “H”,
Upon receiving the inverted signal of “L”, the operation is reversed.
When receiving the input of “H” from the coincidence detection circuit 420, the level shift circuit 422 sets the transistor Q1 to O
N, the transistor Q2 is turned off and the constant current source 41
4, the current IOL is supplied to the point B, and when "L" is received, the transistor Q1 is turned off and the transistor Q2 is turned on to flow the current IOL to the ground GND. When the level shift circuit 423 receives the input of “H” from the coincidence detection circuit 420 via the inverter 421, it turns on the transistor Q3, turns off the transistor Q4, and outputs the current IOH from the point B by the constant current source 415. When sinking to the negative power supply -VEE and receiving the input of "L", the transistor Q3 is turned off and the transistor Q4
Is turned on and the current IOL is supplied from the ground GND to the negative power supply -V.
Sync to EE. The level shift circuits 422 and 423
When the bit signal I / O of the I / O switch ON / OFF control is “H”, even if the signal on the input side is “H”, each receives the input signal of “L” on the input side. Fixed to This allows the transistors Q1, Q3
Becomes OFF and the point B becomes high impedance (Hi-
Z).

Here, the coincidence detection circuit 420 has a selection terminal 420a at one input, and receives a selection signal SEL from the CPU 7. The other input has a comparator (C
OM) 412 is input. In the following, DUT5
, Ie, I / O switch ON /
The operation will be described assuming that the bit signal I / O for OFF control is “L”. When the selection signal SEL is set to "H" when receiving the output of the DUT 5, the following operation is performed. When the comparator 412 is at "H", that is, when the point B is at "H", the coincidence detection circuit 420 outputs "H" and the level shift circuit 4
“H” is input to 22 and “L” is input to the level shift circuit 423. As a result, the transistor Q1 turns on, the transistor Q3 turns off, and the current IOL is supplied to the point B from the constant current source 414. At this time, the transistor Q2 is off and the transistor Q4 is on. On the other hand, when the comparator 412 is “L”, that is, when the point B is “L”, the coincidence detection circuit 420 outputs “L” and the level shift circuit 422
And “H” is input to the level shift circuit 423. As a result, the transistor Q1 is turned off, the transistor Q3 is turned on, and the current IOH is sunk from the point B by the constant current source 415. At this time, the transistor Q2 is ON, and the transistor Q4 is OFF.
It has become. Therefore, the operation is similar to that of the embodiment of FIG.

When receiving the output of the DUT 5, the selection signal S
When EL is set to "L", the operation is reversed. As a result, the operation becomes similar to that of the related art shown in FIG.
That is, when the point B is at “H”, the comparator 412 is at “H”, and the coincidence detection circuit 420 outputs “L”. Therefore, the level shift circuit 422 outputs “L”.
However, “H” is input to the level shift circuit 423.
As a result, the transistor Q3 is turned on, the transistor Q1 is turned off, and the current IOH is sunk from the point B by the constant current source 415. On the other hand, when the point B is “L”, the comparator 412 is “L”, and the coincidence detection circuit 420 outputs “H”. Accordingly, contrary to the above, “H” is input to the level shift circuit 422 and “L” is input to the level shift circuit 423. As a result, the transistor Q3 is turned off, and the transistor Q1 is turned on.
, The current IOL is supplied from the constant current source 414 to the point B. In the latter case, the dynamic current load circuit 44 discharges the current IOL when the point B is "L", and outputs the current IOH when the point B is "H".
Therefore, the operation is the same as that of the dynamic current load circuit 40 shown in FIG. "H" and "L" of the selection signal SEL input to the input terminal 420a
Since the output can be freely set by the output from U7, in this embodiment, the conventional one shown in FIG. 6 and the circuit of the present invention can be selected. Accordingly, the direction of the current output from the dynamic current load circuit 44 can be controlled regardless of the voltage at the point B (connection point 4a).
When a) is connected to the DUT 5 via the transmission line 1, the DU
When the rising and falling speeds of the output signal of the T5 are such that the delay time of the transmission line 1 does not matter, the latter can be selected, and the correct direction is selected according to the speed of the output signal of the DUT5. A load current can be supplied to the DUT 5.

As described above, in the embodiment, the dynamic current load circuit is configured so that the input / output terminal of the dynamic current load circuit becomes high impedance in response to the bit signal I / O of the I / O switch ON / OFF control. However, the present invention is not limited to switching based on the bit signal I / O of the I / O switch ON / OFF control, and the input / output is controlled according to another control signal. The impedance of the output terminal may be switched. In the embodiment, the output signal is obtained from the input / output terminal of the DUT. However, if the output signal is connected to the output dedicated to the output terminal of the DUT via another transmission line, only the output signal is received. Switching by a signal such as a bit signal I / O for O switch ON / OFF control is unnecessary.

[0027]

As described above, according to the present invention, when the output signal of the DUT changes from "L" to "H" in the dynamic current load circuit and the IC tester connected to the DUT by the transmission line. Alternatively, at the time of transition from “H” to “L”, current can be discharged to or sink from the DUT without being affected by the delay time of the delay line. As a result, even when the output signal of the DUT becomes faster, the signal rise time tr or fall time tf can be accurately measured.

[Brief description of the drawings]

FIG. 1 is a block diagram focusing on a dynamic current load circuit in an IC tester to which the present invention is applied.

FIG. 2 is a block diagram mainly showing a dynamic current load circuit in another embodiment to which the present invention is applied.

FIG. 3 is a block diagram mainly showing a dynamic current load circuit in still another embodiment to which the present invention is applied.

FIG. 4 is an explanatory diagram of a specific example of a dynamic current load circuit in which an operation similar to the conventional dynamic current load circuit of FIG. 6 can be selected when the delay time of a transmission line does not matter; FIG.

FIG. 5 is an explanatory diagram of an output voltage-current characteristic of a DUT.

FIG. 6 is a block diagram focusing on a dynamic current load circuit in a conventional IC tester.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmission line, 2 ... Driver, 3 ... Converter, 4 ... I
/ O switch circuit, 5: DUT, 6: waveform formatter, 7: CPU, 8: bus, 410: register, 411
... D / A conversion circuit (D / A), 412 ... Comparator (COM), 413, 413a, 413b, 413c,
413d: switch circuit, 414, 415: constant current source,
416: control circuit, 417a, 417b: 2-input AND gate, 418a, 418b, 418c: inverter,
40, 41, 42, 43, 44... Dynamic current load circuits.

Claims (13)

[Claims] A predetermined waveform is output from a driver to a device under test via a transmission line.
The electronic device under test in an IC tester that receives an output signal that transitions from a GH level to a LOW level or an output signal that transitions from a LOW level to a HIGH level via the transmission line or another transmission line and inspects the state of an output waveform. A load current output circuit that outputs a load current to a device, comprising a detection circuit that detects a voltage level of a line that receives the output signal from the device under test via the transmission line or the other transmission line, When the voltage level detected by the detection circuit is a LOW level, a predetermined current value is drawn from the transmission line or the other transmission line, and when the detected voltage level is a HIGH level, the predetermined current value is the same as or different from the above. An electronic device for supplying a current value to the transmission line or the other transmission line. Load current output circuit to the chair. 2. A current value to be discharged when the device under test is at a HIGH level corresponding to a transition of a HIGH level output when a voltage level on the side receiving the output signal detected by the detection circuit is at a LOW level. LOW is drawn from the transmission line or the other transmission line by a predetermined current value, and transits when the voltage level on the side receiving the output signal is HIGH level.
2. A current supply circuit for supplying a predetermined current value to the transmission line or the other transmission line with respect to a current value to be sunk when the device under test is at a LOW level corresponding to a level output. A load current output circuit to the electronic device described in the above. 3. The detection circuit according to claim 1, wherein the detection circuit receives a predetermined reference voltage and detects whether the voltage level is a LOW level or a HIGH level. The current supply circuit responds to a detection result of the comparison circuit. To draw the current value
3. The load current output circuit for an electronic device according to claim 2, comprising: a constant current source for the electronic device; and a second constant current source for discharging the current value. And a control signal for switching between a state in which the driver outputs the predetermined waveform and a state in which the driver receives an output signal from the device under test, and a comparison result of the comparison circuit. 4. The switch circuit according to claim 3, further comprising a switch circuit that switches to and connects to one of the first and second constant current sources according to a comparison result of the comparison circuit when a control signal indicates a state of receiving the output signal. Load current output circuit for electronic devices. 5. The switch circuit according to claim 1, wherein said switch circuit is switchable to high impedance, and said switch circuit is switched to high impedance when said control signal indicates a state of outputting said predetermined waveform. Item 4
A load current output circuit to the electronic device described in the above. 6. A D / A conversion circuit, further comprising a register and a D / A conversion circuit, wherein the predetermined reference voltage converts data set in the register from outside the load current output circuit by the D / A conversion circuit. 6. The load current output circuit for an electronic device according to claim 5, wherein the comparison circuit generates a low-level output or a high-level output as a comparison result. 7. The load current output circuit for an electronic device according to claim 6, further comprising a control circuit for generating a signal for reversing the comparison result of said comparison circuit. 8. The electronic device according to claim 7, wherein the control circuit is a coincidence detection circuit that receives a low-level or high-level control signal received from outside the load current output circuit and an output of the comparison circuit. Load current output circuit. 9. A predetermined waveform is output from a driver to a device under test via a transmission line.
An IC tester that receives an output signal that transitions from a GH level to a LOW level or an output signal that transitions from a LOW level to a HIGH level through the transmission line or another transmission line and inspects the state of an output waveform. And a comparator that determines whether the voltage level is high or low, and detects a voltage level of a line that receives the output signal from the device under test via the transmission line or the other transmission line. A predetermined current value is drawn from the transmission line or the other transmission line when the voltage level detected by the detection circuit is the LOW level, and when the detected voltage level is the HIGH level. The same or different predetermined current value is supplied to the transmission line or the other transmission line. IC tester, characterized in that it comprises a load current output circuit to the electronic device, wherein, the that. 10. A current value to be discharged when the device under test is at a HIGH level in response to a transition of a HIGH level output when a voltage level on the side receiving the output signal detected by the detection circuit is at a LOW level. A predetermined current value from the transmission line or the other transmission line, and transit when the voltage level on the side receiving the output signal is HIGH level.
The device under test is LOW in response to the W level output.
10. The IC tester according to claim 9, further comprising a current supply circuit that supplies a predetermined current value to the transmission line or the other transmission line with respect to a current value that sinks at the time of a level. 11. The detection circuit is a comparison circuit that receives a predetermined reference voltage and detects whether the voltage level is a LOW level or a HIGH level. The current supply circuit responds to a detection result of the comparison circuit. 11. The IC tester according to claim 10, comprising a first constant current source that draws the current value and a second constant current source that discharges the current value. 12. The control circuit according to claim 1, further comprising a control signal for switching between a state in which the driver outputs the predetermined waveform and a state in which the driver receives an output signal from the device under test, and a comparison result of the comparison circuit. 12. The I circuit according to claim 11, further comprising a switch circuit for switching and connecting to one of the first and second constant current sources according to a comparison result of the comparison circuit when a signal indicates a state of receiving the output signal.
C tester. 13. The switch circuit can be switched to a high impedance state, and when the control signal indicates a state of outputting the predetermined waveform, the switch circuit is switched to a high impedance state. Item 13. The IC tester according to Item 12.