JPS58115868A - Manufacture of field-effect transistor - Google Patents

Manufacture of field-effect transistor

Info

Publication number
JPS58115868A
JPS58115868A JP21122481A JP21122481A JPS58115868A JP S58115868 A JPS58115868 A JP S58115868A JP 21122481 A JP21122481 A JP 21122481A JP 21122481 A JP21122481 A JP 21122481A JP S58115868 A JPS58115868 A JP S58115868A
Authority
JP
Japan
Prior art keywords
gate electrode
film
opening
region
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21122481A
Other languages
Japanese (ja)
Inventor
Masanori Ishii
正典 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21122481A priority Critical patent/JPS58115868A/en
Publication of JPS58115868A publication Critical patent/JPS58115868A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To improve high frequency characteristics, the dielectric strength between each electrode and leak current characteristics as well as to obtain the excellent interfacial condition of the Schottky interface of a Schottky barrier gate electrode by a method wherein the gate length of the titled transistor is sufficiently reduced and the recess thereof is fully widened. CONSTITUTION:The first aperture 7' is formed on a gate electrode forming region by removing the second insulating film 7 consisting of silicon nitride and the like by applying a plasma etching method and the like, and through the intermediary of said aperture, a solution such as a hydrofluoric acid and the like is contacted and etched to the first insulating film 6 consisting of silicon dioxide and the like, and the second aperture 6' is formed on the gate electrode forming region. Then, the etching mask consisting of a photoresist film 8 is removed, a solution and the like containing hydrogen peroxide and potassium hydroxide is contacted to and etching on the surface layer part of the semiconductor active layer 3 such as gallium arsenide and the like, and after a wide concave region 31 has been formed at the lower part of the gate electrode forming region, a metal film such as aluminum and the like is vapor-deposited on the whole surface. Said metal film is deposited only on the region corresponding to the first aperture 7', the region other than the above is left over as a cavity, and the Schottky barrier gate 9 is formed by performing a patterning.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は電界効果トランジスタの製造方法に関する。特
に、活性層の表層部に形成された比較的広い凹部(す+
ス)上に形成されたシ冒ットキノ々リヤゲート電極を有
する電界効果トランジスタの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a field effect transistor. In particular, the relatively wide recesses formed in the surface layer of the active layer
The present invention relates to a method of manufacturing a field effect transistor having a gate electrode formed on a metal layer.

(2)技術の背景 電界効果トランジスタ特に4 GHz以上の超高周波用
に使用される電界効果トランジスタにおいては、ゲート
長が極力短いことが望ましい。伝達コンダクタンスが大
きくなるからフある。また、ゲート電極特にシ四ットキ
ノ々リヤゲート電極にありては、これが半導体活性層上
に直接形成されているの1はなく半導体活性層表層に堀
り込まれた広いリセス上に形成されていることが望まし
い。これはソース電極またはドレイン電極とゲート電極
との間の絶縁耐力が大きくなりゲート電極の漏れ電流が
小さくなるから〒ある。そこ〒、砒化ガリエウム(Ga
As)等電子移動度の大きな半導体をもって製造され高
周波用に適する電界効果トランジスタにあってはリセス
構造を有する電界効果トランジスタが望ましい。
(2) Background of the Technology In field effect transistors, particularly field effect transistors used for ultra-high frequencies of 4 GHz or higher, it is desirable that the gate length be as short as possible. This is because the transfer conductance increases. Furthermore, in the case of gate electrodes, in particular, gate electrodes, they are not formed directly on the semiconductor active layer, but rather on wide recesses dug into the surface layer of the semiconductor active layer. is desirable. This is because the dielectric strength between the source or drain electrode and the gate electrode is increased and the leakage current of the gate electrode is decreased. There, gallium arsenide (Ga
As) A field effect transistor having a recessed structure is preferable for a field effect transistor manufactured using a semiconductor having high electron mobility and suitable for high frequency applications.

(3)  従来技術と問題点 従来、リセス構造を有する電界効果トランジスタを構造
するために一般に使用されている方法は下rのとおりで
ある。
(3) Prior Art and Problems Conventionally, methods generally used to construct a field effect transistor having a recessed structure are as follows.

半導体活性層上にソース電極とドレイン電極とを形成し
た後、全面に二酸化シリコン(810,)等の絶縁膜を
形成し、更に、フォトレジスト膜を形成し、このフォト
レジスト膜のゲート電極形成領域にゲート電極の形状を
有する開口を形成してエツチング用マスクを形成し、こ
のエツチング用マスクを使用して上記の絶縁膜をエツチ
ングして開口を形成し、この絶縁膜に設けられた開qを
介して半導体活性層をエツチングして凹部(リセス)を
形成し、全面にゲート電極用金属膜を形成し、リフトオ
フ法を使用してゲート電極を形成するもの1ある。そこ
で、この従来の製造方法によれば、半導体活性層表層に
形成きれるリセスの長さとリフトオフ法を使用して形成
されるゲート、電極の長さとの差は、上記の半導体活性
層に対しなされるエツチングにおけるサイドエッチング
の量によって決定されることになる。したがつて、リセ
スな十分効果あらしめるためには上記の差を十分大きく
する必要があるにもかかわらず、従来技術に係るリセ、
スミ界効果トランジスタの製造方法を実施する場合は、
リセスな十分広くすることは困難であり、満足すべき特
性を有するリセス構造の電界効果トランジスタを製造す
ることが1きないという欠点があった。更に副次的欠点
として、シ■ットキノ々リヤ瓢ゲート電極の形成にあた
ってり7トオ7mを使用しているため十分なプリベーク
が困難でシ胃ットキノ々リヤゲート電極用金属膜の形成
される領域が十分清浄化されず、界面状態が不良  □
になることと、ゲート電極用金属膜を形成するための蒸
着工程においてレジスト膜の溶融変形にもとづくゲート
電極形状の不整化が惹起されることとが数えられる。
After forming a source electrode and a drain electrode on the semiconductor active layer, an insulating film such as silicon dioxide (810,) is formed on the entire surface, and a photoresist film is further formed, and a gate electrode formation area of this photoresist film is formed. An etching mask is formed by forming an opening in the shape of a gate electrode, and using this etching mask, the above insulating film is etched to form an opening, and the opening q provided in this insulating film is etched. There is one method in which a recess is formed by etching the semiconductor active layer through the etching process, a metal film for a gate electrode is formed on the entire surface, and a gate electrode is formed using a lift-off method. Therefore, according to this conventional manufacturing method, the difference between the length of the recess that can be formed on the surface layer of the semiconductor active layer and the length of the gate and electrode formed using the lift-off method is It will be determined by the amount of side etching in the etching. Therefore, although it is necessary to make the above difference sufficiently large in order to obtain a sufficient recess effect, the recess according to the prior art,
When implementing the manufacturing method of Sumi field effect transistor,
It is difficult to make the recess sufficiently wide, and there is a drawback that it is impossible to manufacture a field effect transistor having a recessed structure with satisfactory characteristics. Furthermore, as a secondary drawback, since 7 to 7 m is used to form the sheet metal gourd gate electrode, sufficient pre-baking is difficult, and the area where the metal film for the sheet metal film for the rear gate electrode is formed is not sufficient. Not cleaned and the interface condition is poor □
In addition, the shape of the gate electrode may become irregular due to melting and deformation of the resist film in the vapor deposition process for forming the metal film for the gate electrode.

(4)  発明の目的 本発明の目的はこれらの欠点を解消することにあり、0
)ゲート長とは無関係にリセスの長さを十分長くするこ
とができ、したがって、ゲート長は十分短く、リセスは
十分広くなすことができて、高周波特性と各電極間の絶
縁耐力とリーク電流特性とを向上することが!き、(ロ
)シロットキノ々リヤゲート電極のシ曹ットキ界面の界
面状態を良好にすることができ、(ハ)ゲート電極の形
成精度を良好にすることができる、リセス構造を有する
電界効果トランジスタの製造方法を提供することにある
(4) Purpose of the invention The purpose of the present invention is to eliminate these drawbacks.
) The recess length can be made sufficiently long regardless of the gate length. Therefore, the gate length can be made sufficiently short and the recess can be made sufficiently wide to improve high frequency characteristics, dielectric strength between each electrode, and leakage current characteristics. And to improve! (b) production of a field effect transistor having a recessed structure, which can improve the interface condition of the cylindrical interface of the cylindrical gate electrode; and (c) improve the formation accuracy of the gate electrode. The purpose is to provide a method.

(5)発明の構成 本発明の構成は、(ハ)砒化ガリ瓢9ム(eaAs)等
の半導体活性層上に金・ゲルマニエウム(ムu、Go)
等の薄層を形成の上これをパターニングしてソースil
!極とドレイン電極とを形成し、―)二職化シリコン(
810,)等比較的エッチされやすい絶縁物よりなる第
1の絶縁膜を形成し、f今更に、窒化シリコン(813
N、)等比較的エッチされにくい絶縁物よりなる第2の
絶縁膜を形成して二重層とし、に)フォトレジストを塗
布してフォトレジスト膜を形成した後フォトリソグラフ
ィー法を使用してゲート電極形成領域に開口を形成して
エツチング用マスクを形成し、(ホ)このエツチング用
マスクを使用して上記の窒化シリコン(81slJ4)
等よりなる第2の絶縁膜にプラズ!エツチング法等を適
用して窒化シリコン(813N、)等よりなる第2の絶
縁膜をゲート電極形成領域から除去してゲート電極形成
領域に第1の開口を形成し、(へ)この第1の開口を介
して弗酸等の溶液等を二酸化シリコン(S10□)等よ
りなる第1の絶縁膜に接触させてこれをエッチしてゲー
ト電極形成領域に第2の開口を形成し、このとき、サイ
ドエッチにより第2の開口は第1の開口より大きなもの
として第2の絶縁膜でひさし状突出部を形成し、(ト)
上記のフォトレジスト膜よりなるエツチングマスクを除
去し、■第1の開口と第2の開口とを介して過酸化水素
(HgO黛)と水酸化カリウム(KOIi)とを含む水
溶液等を砒化ガリニウム(()aAs)勢の半導体活性
層の表層部に接触させてこれをエッチしてゲート電極形
成領域下部に広い凹部領域を形成した後、全面にアル々
工晶つム(ムt)等の金属膜を蒸着し、このとき、この
金属膜は上記の広い凹部領域の一部分のみに堆積させ、
すなわち、第1の開口に和尚する領域のみに堆積させて
それ以外の領域は空洞として残留させ、(す)上記の金
属膜をパターニングしてシ嘗ットキノ々リヤゲート電極
を形成することにある。
(5) Structure of the Invention The structure of the present invention is as follows:
After forming a thin layer such as
! The electrode and the drain electrode are formed, and -) dual-purpose silicon (
A first insulating film made of an insulator that is relatively easily etched, such as silicon nitride (813, ), is formed.
A second insulating film made of an insulating material that is relatively difficult to etch, such as N. An opening is formed in the formation region to form an etching mask, and (e) the above silicon nitride (81slJ4) is etched using this etching mask.
Plas! on the second insulating film made of etc. A second insulating film made of silicon nitride (813N) or the like is removed from the gate electrode formation region by applying an etching method or the like to form a first opening in the gate electrode formation region; A solution such as hydrofluoric acid is brought into contact with the first insulating film made of silicon dioxide (S10□) or the like through the opening and etched to form a second opening in the gate electrode formation region, and at this time, By side etching, the second opening is made larger than the first opening, and an eave-like protrusion is formed in the second insulating film.
The etching mask made of the above photoresist film is removed, and an aqueous solution containing hydrogen peroxide (HgO) and potassium hydroxide (KOIi) is applied to gallium arsenide (gallium arsenide) through the first and second openings. After contacting and etching the surface layer of the semiconductor active layer of ()aAs) to form a wide concave region at the bottom of the gate electrode formation region, the entire surface is covered with a metal such as alkaline crystal. depositing a film, the metal film being deposited only on a portion of the wide recessed region;
That is, the metal film is deposited only in the region that fits into the first opening, leaving the other regions as a cavity, and (2) the above-mentioned metal film is patterned to form a blank gate electrode.

本発明の着想は、ソース電極・ドレイン電極の形成され
た活性層の上に化学的性質の異なる材料をもって二重層
を形成し、この二重層の下層のみを選択的にエッチして
上層をもってひさし状突出部を形成し、その下部領域に
非方向性エツチング法を適用して空洞を形成し、この空
洞中に非方向性エツチング法を適用して活性層表層に面
積の大きなりセスを形成し、一方、このリセス上に形成
され1   るシ曹ットキ・々リヤ電極の電極長は上記
のひさし状突出部の間隙長によって決定されて非常に短
くなしうるということであり、更に、従来技術において
使用されていたフォトレジストよりなるエツチングマス
クを高温に耐える材料例えば窒化シリコン(81,N4
)等に変更することにより、シリベークを可能にしてシ
菖ットキ界面を良好にし、かつ、ゲート電極の形成精度
を向上しうるということfある。
The idea of the present invention is to form a double layer using materials with different chemical properties on the active layer on which source and drain electrodes are formed, and then selectively etch only the lower layer of this double layer to create a canopy shape with the upper layer. forming a protrusion, applying a non-directional etching method to the lower region of the protrusion to form a cavity, applying a non-directional etching method to the cavity to form a groove with a large area on the surface layer of the active layer; On the other hand, the electrode length of the capillary electrode formed on this recess is determined by the gap length of the eaves-like projections and can be made very short. The etching mask made of previously used photoresist is replaced with a material that can withstand high temperatures, such as silicon nitride (81, N4).
) etc., it is possible to make silibake possible, improve the cylindrical interface, and improve the precision of forming the gate electrode.

したがって、本発明の最大の特徴は、上記の第1の開口
より上記の広い凹部領域をはるかに広くし、一方、シ璽
ットキゲート電極が半導体活性層の表面と接触する面積
すなわちゲート長は短くしたことにある。
Therefore, the greatest feature of the present invention is that the above-mentioned wide recessed region is made much wider than the above-mentioned first opening, while the area where the gate electrode contacts the surface of the semiconductor active layer, that is, the gate length is shortened. There is a particular thing.

そこ1、本発明は半導体活性層の材料、第1の絶縁膜の
材料、第2の絶縁膜の材料等によって多数の実施態様が
ありうるが、第1の絶縁膜と第2の絶縁膜との組合せは
、上側の二酸化シリコン(810,)と窒化シリコン(
81N)との組合せに加えて、ノンドープの二酸化シリ
コン(810,)又は燐ドープされた二酸化シリコン(
P−8iO,)と−酸化シリコン(810)との組合せ
、窒化アルミ(ムlN)と多結晶シリコン(POLY−
81)との組合せ等の実施1m襟が試作の上確認されて
いる。各エツチング工程において使用されるエツチング
方法は上記の絶縁膜の材料によって決定される0例え、
ば前記−酸化シリコン、多結晶シリコンのエツチング法
としてはプラズマエツチング法が適用され、ノンドープ
の二酸化シリコン、燐ドープの二酸化シリコンは弗酸(
Hν)系エツチング法によってエツチングされ得、更に
窒化アルミニウムは燐酸(pH,:po4)系エツチン
グ液によってエツチングされる0又、半導体活性層はい
ずれの材料をもっても製造可能〒はあるが、高周波特性
にすぐれている砒化ガリ凰つム(GaAs)が特にすぐ
れている。
First, the present invention can be implemented in many ways depending on the material of the semiconductor active layer, the material of the first insulating film, the material of the second insulating film, etc. The combination of upper silicon dioxide (810,) and silicon nitride (
In addition to combinations with undoped silicon dioxide (810,) or phosphorus-doped silicon dioxide (81N),
A combination of P-8iO, ) and -silicon oxide (810), aluminum nitride (MlN) and polycrystalline silicon (POLY-
A 1m collar in combination with 81) has been prototyped and confirmed. The etching method used in each etching step is determined by the material of the insulating film mentioned above.
For example, plasma etching is applied as the etching method for silicon oxide and polycrystalline silicon, and for non-doped silicon dioxide and phosphorus-doped silicon dioxide, hydrofluoric acid
Furthermore, aluminum nitride can be etched by a phosphoric acid (pH: PO4) based etching method.Also, the semiconductor active layer can be manufactured using any material, but the high frequency characteristics Particularly excellent is arsenide gallium oxide (GaAs).

(6)  発明の実施例 以下、図面を参照しつつ、本発明の一実施例について説
明する。
(6) Embodiment of the invention Hereinafter, an embodiment of the invention will be described with reference to the drawings.

一例として、クローム(Or)等を含有して中絶縁性の
砒化ガリ具つム(Gaム−)基板上にメサ状に形成され
たnllの砒化ガリエウム(Gaム−)Ir8層を使用
してシ冒ットキーリャグート麗電界効果トランジスタを
製造する場合について述べる〇第1図参照 牛絶縁性砒化ガリ&ウム(GaAs)基板l上に形成さ
れ不純物を含有しない砒化ガリ為つム(GaAs)より
なる/セラフッ層2上にメサ上に形成され101ワ13
程度にrsWlの不純物を含有し厚さが0.6μm程度
の砒化ガリ具つム(GaAs)活性層3上に金・ダルマ
ニ^ウム(ムu−Ge )膜を蒸着し、これをソース電
極4とドレイン電極5の形状にノ臂ターニングし、熱処
理を施してソース電極4とドレイン電極5と活性層3と
の間をオーミックに接続する。
As an example, an NLL gallium arsenide (Ga) Ir8 layer formed in a mesa shape on a moderately insulating gallium arsenide (Ga) substrate containing chromium (Or) etc. is used. The case of manufacturing field effect transistors will be described below. See Figure 1. Made of gallium arsenide (GaAs) which is formed on an insulating gallium arsenide (GaAs) substrate and does not contain impurities. / Formed on mesa on Cerafluor layer 2 101 Wa 13
A gold-darmanium (mu-Ge) film is deposited on a gallium arsenide (GaAs) active layer 3 containing impurities of rsWl and having a thickness of about 0.6 μm, and this is used as a source electrode 4. Turning is performed to form the shape of the drain electrode 5, and heat treatment is performed to ohmically connect the source electrode 4, the drain electrode 5, and the active layer 3.

第2図参照 プラズwOVD法を使用して、二酸化シリコン(810
g)膜6と窒化シリコン(alsxa)膜7とを重ねて
形成する。厚さは各々zooo X程度が適轟1ある。
Silicon dioxide (810
g) Form the film 6 and the silicon nitride (ALSXA) film 7 in an overlapping manner. The thickness of each is about 1 x zoooo.

反応性物質は、前者に対してはモノシラン(81i14
)と酸素(Os)との混合ガスが、後者に対してはモノ
シラン(81H4)と−酸化窒素(NO)または窒素(
M、)との混合ガスが適めである。つづいて、フォトレ
ジストを塗布してフォトレジスト膜$を形成する。
For the former, the reactive substance is monosilane (81i14
) and oxygen (Os); for the latter, monosilane (81H4) and -nitrogen oxide (NO) or nitrogen (
A mixed gas with M, ) is suitable. Subsequently, a photoresist is applied to form a photoresist film $.

第3図参照 ゲート電極と活性層3とがシ胃ットキ接触される領域に
和尚する領域に透光部を有するフォトマスクを使用して
、この領域を露光した後露光された7オトレジストII
sを除去して開口8′を形成する。この開口の一辺また
は直径は約1μmが追歯1ある。この開口8′を有する
フォトレジスト膜8をエツチング用マスクとしてプラズ
マエツチング法を適用して窒化シリコン(81N)膜7
をエツチングして開ロア′を形成する。反応性ガスは四
弗化炭素(OF4)と水素Cll5)との混合ガスが追
歯フある。
7 Photoresist II exposed after exposing this area using a photomask having a light-transmitting part in the area where the gate electrode and the active layer 3 are in contact with each other, see FIG.
s is removed to form an opening 8'. One side or diameter of this opening is approximately 1 μm, and there is an additional tooth 1. The silicon nitride (81N) film 7 is etched by applying a plasma etching method using the photoresist film 8 having the opening 8' as an etching mask.
is etched to form an open lower ′. The reactive gas is a mixed gas of carbon tetrafluoride (OF4) and hydrogen (Cl15).

この工程においては、窒化シリコン(81N)膜のみな
らず二酸化シリコン(810,)膜6もエツチングされ
るが垂直性にのみエツチングされる。したがって開ロア
′の一辺または直径は1μms!度である。
In this step, not only the silicon nitride (81N) film but also the silicon dioxide (810,) film 6 is etched, but only vertically. Therefore, one side or diameter of the open lower ′ is 1 μms! degree.

つづいて、弗酸系溶液例えば弗酸(IP) 1容と弗1
    化7パ′″す”c″′8・約10容2″混合液
211′触させ、二酸化シリコン(sio、)膜7を横
方向にエッチし、図に6′をもりて示す領域に空洞6′
を形成する。その結果、窒化シリコン(stli4)I
Iがひさし状に残留することになる。6′の長さはα7
5μm程度となる。
Next, add 1 volume of hydrofluoric acid solution such as 1 volume of hydrofluoric acid (IP) and 1 volume of hydrofluoric acid (IP).
The silicon dioxide (SIO) film 7 is etched in the lateral direction by contacting the silicon dioxide (SIO) film 7 with a mixture of about 10 volumes and 211', creating a cavity in the area indicated by 6' in the figure. 6'
form. As a result, silicon nitride (stli4) I
I will remain in the form of a canopy. The length of 6' is α7
It will be about 5 μm.

第4図参照 フォトレジスト膜8を除去した後過酸化水素(!hot
)と水酸化カリウム([011)とを含む水溶液を上記
の開口8′と開ロア′と開口6′とを介して活性層3と
接触させ、活性層3表層にリセス3′を形成する。
Refer to FIG. 4 After removing the photoresist film 8, use hydrogen peroxide (!hot).
) and potassium hydroxide ([011) is brought into contact with the active layer 3 through the opening 8', the open lower part' and the opening 6' to form a recess 3' in the surface layer of the active layer 3.

第5図参照 アルミニ具つム(ム1)IIIPの金属を厚さ1μm程
度に真空蒸着する。リセス3′の底部のソース−ドレイ
ン方向の長さは1.9〜LOsm@変に頂部のソース−
ドレイン方向の長さはz5〜26μm@度になる。
Refer to FIG. 5. A metal of aluminum material IIIP is vacuum-deposited to a thickness of about 1 μm. The length of the bottom of the recess 3' in the source-drain direction is 1.9~LOsm
The length in the drain direction is z5 to 26 μm@degree.

ここで、活性層3上に堆積するアルミニニウム(ムl)
等の金属層の長さは窒化シリコン(li!1sN4)膜
7の開ロア′の長さによって決定されるから、約1μm
となり、その周囲に長さがα75μm程度の余地が残留
することになる。アル電工龜つム(ムI)岬の金属層を
長さ2〜3μmにノリーニングしてシ璽ットキ/9リヤ
ゲート電極9を完成する。
Here, aluminum (mul) deposited on the active layer 3
The length of the metal layer is determined by the length of the open lower part of the silicon nitride (li!1sN4) film 7, so it is approximately 1 μm.
Therefore, a margin with a length of about α75 μm remains around it. The metal layer of ALDENKO GUTSUM (MUI) is re-nealed to a length of 2 to 3 μm to complete the rear gate electrode 9.

以上の工程によって、(ツー辺または直径がlβm程度
のシ冒ットキノぐリヤゲート電極が一辺または直径が2
5μm程度のリセス上に形成されることになり、(ロ)
ゲート電極用金属の蒸着時にはフォトレジスト膜が不存
在であるから良好なシiットキ接触が段進され、f→ゲ
ート電極用金属の蒸着時には窒化シリコンCB1N)H
がマスクとして機能するので、ダート形状も正確に制御
することができる。
Through the above process, (one side or two diameters of the cut plate rear gate electrode with two sides or a diameter of about 1βm) is formed.
It will be formed on a recess of about 5 μm, (b)
Since there is no photoresist film when depositing the metal for the gate electrode, good contact is achieved, and when depositing the metal for the gate electrode, f→silicon nitride CB1N)H is formed.
functions as a mask, the dart shape can also be precisely controlled.

(7;  発明の詳細 な説明せるとおり、0)ゲート長とは無関係にリセスの
長さを十分長くすることができ、ゲート長は十分短く、
リセスは十分広くなすことができ、結果的に、高周波特
性を良好にすることができソース電極・ゲート電極間ま
たはrレイン電極°ゲート電極間の絶縁耐力を高くリー
ク電流を低くすることが1き、(ロ)シ璽りト中バリヤ
ゲート電極のシ冒ットキ界面の界面状態を良好にするこ
とができ、eウゲート形状の形成積置を良好にすること
ができる、リセス構造を有する電界効果トランジスタの
製造方法を提供することが?きる。
(7; As described in the detailed description of the invention, 0) The recess length can be made sufficiently long regardless of the gate length, and the gate length is sufficiently short.
The recess can be made sufficiently wide, and as a result, the high frequency characteristics can be improved, and the dielectric strength between the source electrode and the gate electrode or between the r-rain electrode and the gate electrode can be increased, and leakage current can be reduced. (b) A field effect transistor having a recessed structure, which can improve the interface condition of the cut interface of the barrier gate electrode during shredding and improve the formation and stacking of the e-gate shape. Can you provide manufacturing methods? Wear.

【図面の簡単な説明】[Brief explanation of drawings]

第1.2・3.4.5図は本発明の一実施例に係る、メ
サ状砒化ガリ為りム活性層を使用してリセス構造を有す
るシ冒ットキAリヤゲート型電界効果トランジスタを製
造する方法の各主要工程完了後の概念的断面図である。 l・・・早絶縁性基板、2・・・ノtツ77層、3・・
・nil砒化ガリ凰りム活性層、4・・・ソース電極、
5・・・rレイン電極、6・・・第1の絶縁層(二酸化
シリコン層)、7−・・第2の絶縁層(窒化シリコン層
)、8・・・7オトレジスト膜、81 +m・フォトレ
ジスト膜よりなるエツチング用マスクの開口、7′・・
・第1の開口CII化シリコン層に形成された開口)、
6′・・・第2の開口(二酸化シリコン層に形成された
空洞)、3・・・リセX(活性層に形成された凹部)、
9・・・シ璽ットキノ9リヤゲート電極。 第5図
Figures 1.2 and 3.4.5 show how to fabricate a recessed structure-type rear gate field effect transistor using a mesa-shaped arsenide gallium active layer according to an embodiment of the present invention. Figure 3 is a conceptual cross-sectional view after each main step of the method has been completed; l... Quickly insulating substrate, 2... 77 layers, 3...
・Nil arsenide gallium active layer, 4... source electrode,
5...r rain electrode, 6...first insulating layer (silicon dioxide layer), 7-...second insulating layer (silicon nitride layer), 8...7 photoresist film, 81 +m photo Opening of etching mask made of resist film, 7'...
- first opening (opening formed in CII silicon layer),
6'... Second opening (cavity formed in the silicon dioxide layer), 3... Recess X (recess formed in the active layer),
9... Shitkino 9 rear gate electrode. Figure 5

Claims (1)

【特許請求の範囲】[Claims] (1)半導体活性層上に形成されたソース電極とドレイ
ン電極とを挾む領域に形成された凹部領域にシ冒ットキ
ノ々リヤゲート電極の形成されてなる電界効果トランジ
スタの製造方法において、前記ソース電極と前記ドレイ
ン電極とを形成した後、前記生導体活性層上に第1の皮
膜並びに該第1の皮膜とは同一エツチング剤に対する被
エツチング量を異にする第2の皮膜を重ねて形成し、次
い1前記第2α夜膜を前記ゲート電極形成領域から除去
して前!Pゲート電極形成領域に第1の開口を形成し、
次い!該第1の開口を介して前記第1の皮膜をエツチン
グして該第1の皮膜に前記第1の開口より大きな第2の
開口を形成し、前記第1の開口と前記第2の開口とを介
して前記半導体活性層の表層部をエツチングして前記凹
部領域を形成し、全面に金属膜を蒸着した後肢金属膜な
ノ9ターニングして前記凹部領域に前記シ冒ットキノ々
リヤゲート電極を形成することを特徴とする電界効果ト
ランジスタの製造方法。
(1) In a method of manufacturing a field effect transistor, a trench gate electrode is formed in a recessed region formed in a region sandwiching a source electrode and a drain electrode formed on a semiconductor active layer, wherein the source electrode and the drain electrode, a first film and a second film having a different amount of etching with the same etching agent than the first film are stacked on the raw conductor active layer, Next, the second α film is removed from the gate electrode formation region. forming a first opening in the P gate electrode formation region;
Next! etching the first film through the first opening to form a second opening in the first film that is larger than the first opening; and forming a second opening larger than the first opening; etching the surface layer of the semiconductor active layer to form the recessed region, and forming a rear gate electrode on the etched surface in the recessed region by turning the rear metal film with a metal film deposited on the entire surface; A method for manufacturing a field effect transistor, characterized in that:
JP21122481A 1981-12-28 1981-12-28 Manufacture of field-effect transistor Pending JPS58115868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21122481A JPS58115868A (en) 1981-12-28 1981-12-28 Manufacture of field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21122481A JPS58115868A (en) 1981-12-28 1981-12-28 Manufacture of field-effect transistor

Publications (1)

Publication Number Publication Date
JPS58115868A true JPS58115868A (en) 1983-07-09

Family

ID=16602338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21122481A Pending JPS58115868A (en) 1981-12-28 1981-12-28 Manufacture of field-effect transistor

Country Status (1)

Country Link
JP (1) JPS58115868A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178571A (en) * 1982-04-14 1983-10-19 Nec Corp Semiconductor device
JPS61113281A (en) * 1984-11-08 1986-05-31 New Japan Radio Co Ltd Manufacture of fet
JPS6237973A (en) * 1985-08-13 1987-02-18 Matsushita Electronics Corp Metal-electrode forming method
JPH03177028A (en) * 1989-12-06 1991-08-01 Nippon Mining Co Ltd Manufacture of semiconductor device
JPH03206624A (en) * 1990-01-08 1991-09-10 Nec Corp Semiconductor device
JPH04199518A (en) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp Field-effect transistor and manufacture thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178571A (en) * 1982-04-14 1983-10-19 Nec Corp Semiconductor device
JPS61113281A (en) * 1984-11-08 1986-05-31 New Japan Radio Co Ltd Manufacture of fet
JPS6237973A (en) * 1985-08-13 1987-02-18 Matsushita Electronics Corp Metal-electrode forming method
JPH03177028A (en) * 1989-12-06 1991-08-01 Nippon Mining Co Ltd Manufacture of semiconductor device
JPH03206624A (en) * 1990-01-08 1991-09-10 Nec Corp Semiconductor device
JPH04199518A (en) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp Field-effect transistor and manufacture thereof

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