JPS58114629A - Logical gate circuit - Google Patents
Logical gate circuitInfo
- Publication number
- JPS58114629A JPS58114629A JP21124181A JP21124181A JPS58114629A JP S58114629 A JPS58114629 A JP S58114629A JP 21124181 A JP21124181 A JP 21124181A JP 21124181 A JP21124181 A JP 21124181A JP S58114629 A JPS58114629 A JP S58114629A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- level
- pull
- circuit
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00353—Modifications for eliminating interference or parasitic voltages or currents in bipolar transistor circuits
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
(1) 発明の技術分針
本発明はTTL回路の駆動部に係り、過渡時におけるス
パイク電流を抑えるようにL&新規な回路に関するもの
である0
伐) 発明の背景
TTL回路は電源Vco とグランドの間に種々の素
子を接続して構成される。TTL @路は種々のIC回
路で使用され、例えばTTL回路を利用したICメモリ
のアドレスゲート等に使用され、同一タイ電ングで多数
のアドレスゲートが動作する場合がある0
但)従来技術と問題点
第1mの抵抗ドライブ蓋のTTL j回路の駆動回路は
、位相分割トランジスタQ1と出力プルダウントランジ
スタQ3及びドライブ用抵抗R1より構成される。この
回路は入力INがLレベルのIIQI、Q倉がオフとな
りVec より抵抗R1を介して出力端子0υTに接
続される負荷を駆動する。[Detailed description of the invention] (1) Technique of the invention Minute hand The present invention relates to a drive section of a TTL circuit, and relates to a novel circuit for suppressing spike current during transient periods.Background of the invention TTL circuit is constructed by connecting various elements between the power supply Vco and ground. TTL @ circuits are used in various IC circuits, for example, in address gates of IC memories using TTL circuits, and many address gates may operate with the same tie voltage.However, prior art and problems The drive circuit of the TTL j circuit of the resistor drive lid at point 1m is composed of a phase splitting transistor Q1, an output pull-down transistor Q3, and a drive resistor R1. In this circuit, when the input IN is at L level, IIQI and Q output are turned off, and Vec drives the load connected to the output terminal 0υT via the resistor R1.
このドライブ能力を上げるためにはRI を小さくする
必要があり、一方RIが小さいと、入力INがHレベル
の時、Q1#QlがオンしテVcc −′IL+ −Q
m −GND 2−mh411flitl大となり消費
電流が大となり好ましくない。In order to increase this drive capability, it is necessary to reduce RI. On the other hand, if RI is small, when the input IN is at H level, Q1#Ql is turned on and the voltage Vcc -'IL+ -Q
m-GND 2-mh411flitl becomes large, resulting in large current consumption, which is not preferable.
このような点を解決する回路として、第2図に示すよう
なオフバフフッ回路付の駆動回路がある。つまり第1図
のドライブ用抵抗R1の代りにオフバッファ回路として
出カブルアツブトランジスタQs ダイオードDを設け
ている。そして入力INがLレベルのと亀は、Qs、D
のみオンし十分な駆動能力をもりて出力端子〇[JT
Km絖される負荷をドライブし1人力INかHレベルの
ときはQl、Q1オンLQI、Dをオフにして、第1図
の回路の如自消費電力大なることを防いでいる。As a circuit that solves this problem, there is a drive circuit with an off-buff circuit as shown in FIG. That is, in place of the drive resistor R1 in FIG. 1, an output-capable transistor Qs and diode D are provided as an off-buffer circuit. And when the input IN is L level, the turtle is Qs, D
Only turn on the output terminal 〇[JT
When driving a load that is connected by Km and the power is at IN or H level, Ql, Q1 on, LQI, and D are turned off to prevent the power consumption of the circuit shown in FIG. 1 from increasing.
ところがこの回路は、定常時ではQm、Qsのいずれか
一方がオンし他方がオフしているが、入力INがL→■
と変化する過渡状態においては、Qffi 、Qm共に
オンする状態が生じる。その時Vco−Qs−D−Q雪
−GNDとスパイク状の大電流が流れる。特に前述した
ように多数のアドレスゲートが同時に上記スパイク電流
を発生すると、TTL回路が形成されているICチップ
を収容しているパッケージ等の電源Woo パターン
やGNDパターン等にそれらを合計した大電流が流れ、
一時的にICチップ内でのWoe レベルが下がり、
且つGNDレベルが上がるという現象が生じる口すると
TTL回路動作に支障をきたしてしまう。また多数のI
Cを実装しているプリント板においても好ましくない・
(4)発明の目的
本発明は一定常状1て消費電力小でドライブ能力に優れ
たオフバッファ付のTTL lid路の駆動回路におい
て、上記過渡状態でのスパイクノイズを抑えた回路を提
供することを目的とする。However, in this circuit, in steady state, one of Qm and Qs is on and the other is off, but when the input IN is L→■
In a transient state in which Qffi and Qm change, a state occurs in which both Qffi and Qm are turned on. At that time, a large spike-like current flows through Vco-Qs-D-Q snow-GND. In particular, as mentioned above, when many address gates generate the spike currents at the same time, the sum of these large currents flows through the power supply pattern, GND pattern, etc. of the package that houses the IC chip on which the TTL circuit is formed. flow,
The Woe level in the IC chip temporarily decreases,
In addition, if a phenomenon in which the GND level increases occurs, it will impede the operation of the TTL circuit. Also, many I
(4) Purpose of the Invention The present invention provides a drive circuit for a TTL lid path with an off-buffer that has low power consumption and excellent drive ability in a constant state. The purpose of the present invention is to provide a circuit that suppresses spike noise under certain conditions.
(5) 発明の構成
本発明は、位相分劉トランジスタのコレクタ電位により
制御され、電源に接続された出カブルアツブトランジス
タと、該位相分割トランジスタのエミッタ電位により制
御され、I!I地点lIc1a読された出力プルダウン
トランジスタと、験両トランジスタの一接続点Kil続
された出力端子とを具備するamゲート回路において、
該出カブルアツブトランジスタと該接続点との関Kll
流制限用抵抗を設け、過液時において電源よ**出カブ
ルアツブトランジスタ及び出力プルダウントランジスタ
を介して接地点に流れるスパイク電流を抑えるようにし
たことを特徴とする。(5) Structure of the Invention The present invention is controlled by the collector potential of a phase splitting transistor, an outputtable transistor connected to a power supply, and the emitter potential of the phase splitting transistor. In an am gate circuit comprising an output pull-down transistor read from point IIc1a and an output terminal connected to one connection point Kil of both test transistors,
The connection between the output-capable transistor and the connection point
A current limiting resistor is provided to suppress the spike current flowing from the power supply to the ground point via the output pull-down transistor and the output pull-down transistor in the event of overflow.
(6)発明の実施例
第5.$、7gFi本発明の実施例を示す回路図で、各
集゛施例共に、出カブルアツブトランジスタQs とQ
s、Qmの接続点との間に電流制限用抵抗飢8を設けて
いる。第5,6゜7図におけるオフバッフ7回路は、そ
れぞれQs、Qm、QsとQsよりなり、動作は同様で
ある。(6) Embodiment 5 of the invention. $,7gFi This is a circuit diagram showing an embodiment of the present invention, and each embodiment includes outputtable transistors Qs and Q.
A current limiting resistor 8 is provided between the connection point of s and Qm. The off-buffer 7 circuits shown in FIGS. 5 and 6-7 each consist of Qs, Qm, Qs and Qs, and operate in the same way.
すなわち定常状sにおいてa、Q”@Qaいずれ春一方
がオンで他方がオフであるため消費電流燻小である。That is, in the steady state s, one of a and Q''@Qa is on and the other is off, so the current consumption is small.
tた過渡状sにおいては%Ql#QI%/hずれもオン
L&と11抵抗Rs K ヨl Va e −eGND
の電流祉抑見られるため、従来の機な大暑なスパイク電
流が流れること#11に−・そしてQ・オンしたと龜の
1駆動能力は若干下がる%ee最低第11iiと同程度
にした場合で1、十分スパイク電流を抑えることがで自
−しかも第1図の場合よ)消費電流を少なくすることが
で自る。In the transient state s where %Ql#QI%/h deviation is also on L& and 11 resistance Rs K Yol Va e -eGND
Because the current welfare is suppressed, a large spike current flows like in the conventional machine. #11 - And when the Q is turned on, the drive capacity of the barrel decreases slightly. If the %EE is at least the same as No. 11 II. 1. By sufficiently suppressing the spike current, it is possible to reduce the current consumption (as in the case of Fig. 1).
本実施例のILsは伺えif 500〜1にΩ程度を使
用した。For the ILs of this example, approximately Ω was used with a value of 500 to 1.
本発明で祉凰−をシランジスタQ−とQsaQlの接続
点に設けたが、単にスパイク電流を抑えるだけなら第8
i1!IK示すようにオ7パyフv ellj32ルア
ツブトランジスタQsOコレクタとV(1(1との閏に
電流制限抵抗シを設けることも考えられる。In the present invention, a filter is provided at the connection point between the silane resistor Q- and QsaQl, but if only to suppress the spike current, the
i1! As shown in IK, it is also conceivable to provide a current limiting resistor between the collector of the transistor QsO and V(1) as shown in FIG.
しかしながら第411に示すように入力11tTがL→
■レベルになると完接を生じ易−1すなわちQtがオン
し、N2点が上昇し、Q諺をtンすることにより、Vc
c−Rm−D−Qs −Ql−GNDと電流が流れ、比
較的大吉な抵抗(第2図のrよりはるかに大)勧の電圧
降下によJ)Nsのレベルが下が6N10レベル以下に
なる。するとQsのベース・コレクタ間が順方向バイア
スされQsが一時的に飽和状態になる。その結果図に示
すように抵抗Rsに11) 、 Ic+ 、Icm 、
Iceの電流が流れる。However, as shown in No. 411, the input 11tT is L→
■When reaching the level, complete connection is likely to occur -1, that is, Qt turns on, the N2 point rises, and by turning on the Q proverb, Vc
A current flows from c-Rm-D-Qs-Ql-GND, and due to the voltage drop across the relatively auspicious resistance (much larger than r in Figure 2), the level of J)Ns drops below the 6N10 level. Become. Then, a forward bias is applied between the base and collector of Qs, and Qs becomes temporarily saturated. As a result, as shown in the figure, the resistance Rs is 11), Ic+, Icm,
Ice current flows.
C+はQaのコレクタに接続される寄生容量。C+ is a parasitic capacitance connected to the collector of Qa.
C!は出力端子0UTK接続される負荷容量であり、電
流Icm、IcsによりQ雪のベース電流Ibが不足し
出力端OUT が再び上昇する。その結果N1のレベル
も上昇り、Q−は再度非飽和となる。そしてOUTが下
がり・・・・ と発珈する。C! is the load capacitance connected to the output terminal 0UTK, and the base current Ib of the Q snow becomes insufficient due to the currents Icm and Ics, and the output terminal OUT rises again. As a result, the level of N1 also rises, and Q- becomes unsaturated again. Then, the OUT goes down... and the signal goes off.
従って本発明では出カブルア、プトランジスタQs と
Qa、Qsの接続点の間に電流制限抵抗kLsを設け、
上記の弊害をまぬがれている0
(7) 発明の効果
本発明によれば、定常状態における消費電力が小なるオ
フバッフT付駆動回路の過渡状態における大なるスパイ
ク電流を防止することができ、安定な回路動作を得るこ
とができる0Therefore, in the present invention, a current limiting resistor kLs is provided between the output blue transistor Qs and the connection point between Qa and Qs.
(7) Effects of the Invention According to the present invention, it is possible to prevent a large spike current in a transient state of a drive circuit with an off-buff T, which consumes little power in a steady state, and to maintain a stable state. 0 which can obtain the circuit operation
第1.2.8図は従来の回路図、第4図kA第8図の動
作を説明するレベル図、第5.6.7図は本発明の一実
施例を示す回路図である。
図中、QIは位相分割トランジスタ、Qgi1出力プル
ダウントランジスタ、Qsは出カブルア、プトランジス
タ、OUTは出力m子、 Vc(・はi!源である。
1fJj図 第2図
83回 名4図1.2.8 is a conventional circuit diagram, FIG. 4kA is a level diagram explaining the operation of FIG. 8, and FIG. 5.6.7 is a circuit diagram showing an embodiment of the present invention. In the figure, QI is a phase division transistor, Qgi1 output pull-down transistor, Qs is an output pull-down transistor, OUT is an output m-channel, and Vc (・ is an i! source.
Claims (1)
電[*統された出カブルアツブトランジスタと、該位相
分割トランジスタのエミッタ1位によや制御され、接地
点に接続された出力プルダウントランジスタと、該両ト
ランジスタの接続点に接続された出力端子とを具備する
#i/1城ゲート回路において、該出カブルアツブトラ
ンジスタと該接続点との間に電流制限用抵抗を設け、過
渡時にお−て電源より該出カブルア、プトランジスタ及
び出力プルダウントランンスタを介し″′C接地点に流
れるスパイク電流を抑えるようにしたことを特徴とする
111j1ゲ一ト回路。Controlled by the collector potential of the phase splitting transistor,
An output pull-down transistor controlled by the first emitter of the phase splitting transistor and connected to the ground, and an output terminal connected to the connection point of both transistors. In the #i/1 gate circuit, a current limiting resistor is provided between the output pull-up transistor and the connection point, and the output pull-down transistor and the output pull-down are connected from the power supply during a transient state. A 111j1 gate circuit characterized in that a spike current flowing to the ``'C grounding point via a transistor is suppressed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21124181A JPS58114629A (en) | 1981-12-28 | 1981-12-28 | Logical gate circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21124181A JPS58114629A (en) | 1981-12-28 | 1981-12-28 | Logical gate circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58114629A true JPS58114629A (en) | 1983-07-08 |
Family
ID=16602619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21124181A Pending JPS58114629A (en) | 1981-12-28 | 1981-12-28 | Logical gate circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58114629A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0817383A2 (en) * | 1991-09-20 | 1998-01-07 | Motorola, Inc. | Driver circuit |
-
1981
- 1981-12-28 JP JP21124181A patent/JPS58114629A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0817383A2 (en) * | 1991-09-20 | 1998-01-07 | Motorola, Inc. | Driver circuit |
EP0817383A3 (en) * | 1991-09-20 | 1998-01-28 | Motorola, Inc. | Driver circuit |
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